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arm, arm926ejs: Do cpu critical inits only for boards that require it
This patch reverts commit ca4b55800e
"arm, arm926ejs: always do cpu critical inits" since it impacts all
arm926ejs based configurations and caused problems, e.g., with
the hawkboard.
Instead the patch removes the CONFIG_SKIP_LOWLEVEL_INIT defines
from the board configurations that need low level initialization.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
parent
eb93524224
commit
27b66622b5
4 changed files with 4 additions and 10 deletions
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@ -194,7 +194,9 @@ reset:
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* we do sys-critical inits only at reboot,
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* we do sys-critical inits only at reboot,
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* not when booting from ram!
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* not when booting from ram!
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*/
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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bl cpu_init_crit
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bl cpu_init_crit
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#endif
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/* Set stackpointer in internal RAM to call board_init_f */
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/* Set stackpointer in internal RAM to call board_init_f */
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call_board_init_f:
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call_board_init_f:
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@ -353,6 +355,7 @@ _dynsym_start_ofs:
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*
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*
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*************************************************************************
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*************************************************************************
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*/
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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cpu_init_crit:
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cpu_init_crit:
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/*
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/*
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* flush v4 I/D caches
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* flush v4 I/D caches
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@ -371,15 +374,14 @@ cpu_init_crit:
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orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
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orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
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mcr p15, 0, r0, c1, c0, 0
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mcr p15, 0, r0, c1, c0, 0
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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/*
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/*
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* Go setup Memory and board specific bits prior to relocation.
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* Go setup Memory and board specific bits prior to relocation.
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*/
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*/
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mov ip, lr /* perserve link reg across call */
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mov ip, lr /* perserve link reg across call */
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bl lowlevel_init /* go setup pll,mux,memory */
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bl lowlevel_init /* go setup pll,mux,memory */
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mov lr, ip /* restore link */
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mov lr, ip /* restore link */
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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mov pc, lr /* back to my caller */
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mov pc, lr /* back to my caller */
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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#ifndef CONFIG_SPL_BUILD
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#ifndef CONFIG_SPL_BUILD
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/*
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/*
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@ -275,12 +275,6 @@
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000
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/*
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* U-Boot is a 3rd stage loader and if booting with spl, cpu setup is
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* done in board_init_f from c code.
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*/
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#define CONFIG_SKIP_LOWLEVEL_INIT
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/* for UBL header */
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/* for UBL header */
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#define CONFIG_SYS_UBL_BLOCK (CONFIG_SYS_NAND_PAGE_SIZE)
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#define CONFIG_SYS_UBL_BLOCK (CONFIG_SYS_NAND_PAGE_SIZE)
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@ -42,7 +42,6 @@
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#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
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#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
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#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
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#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_TEXT_BASE 0xc1080000
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#define CONFIG_SYS_TEXT_BASE 0xc1080000
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/*
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/*
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@ -45,7 +45,6 @@
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#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
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#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
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#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
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#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_DA850_LOWLEVEL
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#define CONFIG_DA850_LOWLEVEL
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_DA8XX_GPIO
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#define CONFIG_DA8XX_GPIO
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