mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 21:21:37 +00:00
Merge git://git.denx.de/u-boot-marvell
This commit is contained in:
commit
2959f936c5
5 changed files with 155 additions and 161 deletions
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@ -214,32 +214,40 @@ static void setup_usb_phys(void)
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int arch_cpu_init(void)
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{
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#ifndef CONFIG_SPL_BUILD
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if (mvebu_soc_family() == MVEBU_SOC_A38X) {
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struct pl310_regs *const pl310 =
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(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
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/*
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* Only with disabled MMU its possible to switch the base
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* register address on Armada 38x. Without this the SDRAM
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* located at >= 0x4000.0000 is also not accessible, as its
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* still locked to cache.
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*
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* So to fully release / unlock this area from cache, we need
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* to first flush all caches, then disable the MMU and
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* disable the L2 cache.
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*/
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icache_disable();
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dcache_disable();
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mmu_disable();
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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}
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#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMADA_38X)
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/*
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* Only with disabled MMU its possible to switch the base
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* register address on Armada 38x. Without this the SDRAM
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* located at >= 0x4000.0000 is also not accessible, as its
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* still locked to cache.
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*/
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mmu_disable();
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#endif
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/* Linux expects the internal registers to be at 0xf1000000 */
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writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
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set_cbar(SOC_REGS_PHY_BASE + 0xC000);
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#if !defined(CONFIG_SPL_BUILD)
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/*
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* From this stage on, the SoC detection is working. As we have
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* configured the internal register base to the value used
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* in the macros / defines in the U-Boot header (soc.h).
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*/
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if (mvebu_soc_family() == MVEBU_SOC_A38X) {
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struct pl310_regs *const pl310 =
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(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
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/*
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* To fully release / unlock this area from cache, we need
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* to flush all caches and disable the L2 cache.
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*/
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icache_disable();
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dcache_disable();
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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}
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#endif
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/*
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* We need to call mvebu_mbus_probe() before calling
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* update_sdram_window_sizes() as it disables all previously
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@ -41,7 +41,7 @@
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#define timestamp gd->arch.tbl
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#define lastdec gd->arch.lastinc
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static int init_done;
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static int init_done __attribute__((section(".data"))) = 0;
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/* Timer reload and current value registers */
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struct kwtmr_val {
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@ -17,89 +17,6 @@
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#include <stdint.h>
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#include "kwbimage.h"
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#define ALIGN_SUP(x, a) (((x) + (a - 1)) & ~(a - 1))
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/* Structure of the main header, version 0 (Kirkwood, Dove) */
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struct main_hdr_v0 {
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uint8_t blockid; /*0 */
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uint8_t nandeccmode; /*1 */
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uint16_t nandpagesize; /*2-3 */
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uint32_t blocksize; /*4-7 */
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uint32_t rsvd1; /*8-11 */
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uint32_t srcaddr; /*12-15 */
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uint32_t destaddr; /*16-19 */
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uint32_t execaddr; /*20-23 */
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uint8_t satapiomode; /*24 */
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uint8_t rsvd3; /*25 */
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uint16_t ddrinitdelay; /*26-27 */
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uint16_t rsvd2; /*28-29 */
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uint8_t ext; /*30 */
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uint8_t checksum; /*31 */
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};
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struct ext_hdr_v0_reg {
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uint32_t raddr;
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uint32_t rdata;
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};
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#define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg))
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struct ext_hdr_v0 {
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uint32_t offset;
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uint8_t reserved[0x20 - sizeof(uint32_t)];
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struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT];
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uint8_t reserved2[7];
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uint8_t checksum;
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};
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/* Structure of the main header, version 1 (Armada 370, Armada XP) */
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struct main_hdr_v1 {
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uint8_t blockid; /* 0 */
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uint8_t reserved1; /* 1 */
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uint16_t reserved2; /* 2-3 */
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uint32_t blocksize; /* 4-7 */
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uint8_t version; /* 8 */
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uint8_t headersz_msb; /* 9 */
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uint16_t headersz_lsb; /* A-B */
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uint32_t srcaddr; /* C-F */
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uint32_t destaddr; /* 10-13 */
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uint32_t execaddr; /* 14-17 */
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uint8_t reserved3; /* 18 */
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uint8_t nandblocksize; /* 19 */
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uint8_t nandbadblklocation; /* 1A */
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uint8_t reserved4; /* 1B */
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uint16_t reserved5; /* 1C-1D */
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uint8_t ext; /* 1E */
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uint8_t checksum; /* 1F */
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};
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/*
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* Header for the optional headers, version 1 (Armada 370, Armada XP)
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*/
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struct opt_hdr_v1 {
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uint8_t headertype;
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uint8_t headersz_msb;
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uint16_t headersz_lsb;
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char data[0];
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};
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/*
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* Various values for the opt_hdr_v1->headertype field, describing the
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* different types of optional headers. The "secure" header contains
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* informations related to secure boot (encryption keys, etc.). The
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* "binary" header contains ARM binary code to be executed prior to
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* executing the main payload (usually the bootloader). This is
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* typically used to execute DDR3 training code. The "register" header
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* allows to describe a set of (address, value) tuples that are
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* generally used to configure the DRAM controller.
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*/
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#define OPT_HDR_V1_SECURE_TYPE 0x1
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#define OPT_HDR_V1_BINARY_TYPE 0x2
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#define OPT_HDR_V1_REGISTER_TYPE 0x3
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#define KWBHEADER_V1_SIZE(hdr) \
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(((hdr)->headersz_msb << 16) | (hdr)->headersz_lsb)
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static struct image_cfg_element *image_cfg;
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static int cfgn;
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@ -173,17 +90,6 @@ struct image_cfg_element {
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#define IMAGE_CFG_ELEMENT_MAX 256
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/*
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* Byte 8 of the image header contains the version number. In the v0
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* header, byte 8 was reserved, and always set to 0. In the v1 header,
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* byte 8 has been changed to a proper field, set to 1.
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*/
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static unsigned int image_version(void *header)
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{
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unsigned char *ptr = header;
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return ptr[8];
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}
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/*
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* Utility functions to manipulate boot mode and ecc modes (convert
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* them back and forth between description strings and the
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135
tools/kwbimage.h
135
tools/kwbimage.h
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@ -29,6 +29,94 @@
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#define IBR_HDR_UART_ID 0x69
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#define IBR_DEF_ATTRIB 0x00
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#define ALIGN_SUP(x, a) (((x) + (a - 1)) & ~(a - 1))
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/* Structure of the main header, version 0 (Kirkwood, Dove) */
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struct main_hdr_v0 {
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uint8_t blockid; /*0 */
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uint8_t nandeccmode; /*1 */
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uint16_t nandpagesize; /*2-3 */
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uint32_t blocksize; /*4-7 */
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uint32_t rsvd1; /*8-11 */
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uint32_t srcaddr; /*12-15 */
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uint32_t destaddr; /*16-19 */
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uint32_t execaddr; /*20-23 */
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uint8_t satapiomode; /*24 */
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uint8_t rsvd3; /*25 */
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uint16_t ddrinitdelay; /*26-27 */
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uint16_t rsvd2; /*28-29 */
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uint8_t ext; /*30 */
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uint8_t checksum; /*31 */
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};
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struct ext_hdr_v0_reg {
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uint32_t raddr;
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uint32_t rdata;
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};
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#define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg))
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struct ext_hdr_v0 {
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uint32_t offset;
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uint8_t reserved[0x20 - sizeof(uint32_t)];
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struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT];
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uint8_t reserved2[7];
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uint8_t checksum;
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};
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struct kwb_header {
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struct main_hdr_v0 kwb_hdr;
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struct ext_hdr_v0 kwb_exthdr;
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};
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/* Structure of the main header, version 1 (Armada 370, Armada XP) */
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struct main_hdr_v1 {
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uint8_t blockid; /* 0 */
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uint8_t reserved1; /* 1 */
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uint16_t reserved2; /* 2-3 */
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uint32_t blocksize; /* 4-7 */
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uint8_t version; /* 8 */
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uint8_t headersz_msb; /* 9 */
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uint16_t headersz_lsb; /* A-B */
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uint32_t srcaddr; /* C-F */
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uint32_t destaddr; /* 10-13 */
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uint32_t execaddr; /* 14-17 */
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uint8_t reserved3; /* 18 */
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uint8_t nandblocksize; /* 19 */
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uint8_t nandbadblklocation; /* 1A */
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uint8_t reserved4; /* 1B */
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uint16_t reserved5; /* 1C-1D */
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uint8_t ext; /* 1E */
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uint8_t checksum; /* 1F */
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};
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/*
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* Header for the optional headers, version 1 (Armada 370, Armada XP)
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*/
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struct opt_hdr_v1 {
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uint8_t headertype;
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uint8_t headersz_msb;
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uint16_t headersz_lsb;
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char data[0];
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};
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/*
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* Various values for the opt_hdr_v1->headertype field, describing the
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* different types of optional headers. The "secure" header contains
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* informations related to secure boot (encryption keys, etc.). The
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* "binary" header contains ARM binary code to be executed prior to
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* executing the main payload (usually the bootloader). This is
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* typically used to execute DDR3 training code. The "register" header
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* allows to describe a set of (address, value) tuples that are
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* generally used to configure the DRAM controller.
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*/
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#define OPT_HDR_V1_SECURE_TYPE 0x1
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#define OPT_HDR_V1_BINARY_TYPE 0x2
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#define OPT_HDR_V1_REGISTER_TYPE 0x3
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#define KWBHEADER_V1_SIZE(hdr) \
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(((hdr)->headersz_msb << 16) | (hdr)->headersz_lsb)
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enum kwbimage_cmd {
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CMD_INVALID,
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CMD_BOOT_FROM,
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CFG_DATA1
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};
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/* typedefs */
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typedef struct bhr_t {
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uint8_t blockid; /*0 */
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uint8_t nandeccmode; /*1 */
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uint16_t nandpagesize; /*2-3 */
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uint32_t blocksize; /*4-7 */
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uint32_t rsvd1; /*8-11 */
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uint32_t srcaddr; /*12-15 */
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uint32_t destaddr; /*16-19 */
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uint32_t execaddr; /*20-23 */
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uint8_t satapiomode; /*24 */
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uint8_t rsvd3; /*25 */
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uint16_t ddrinitdelay; /*26-27 */
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uint16_t rsvd2; /*28-29 */
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uint8_t ext; /*30 */
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uint8_t checkSum; /*31 */
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} bhr_t, *pbhr_t;
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struct reg_config {
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uint32_t raddr;
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uint32_t rdata;
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};
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typedef struct extbhr_t {
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uint32_t dramregsoffs;
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uint8_t rsrvd1[0x20 - sizeof(uint32_t)];
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struct reg_config rcfg[KWBIMAGE_MAX_CONFIG];
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uint8_t rsrvd2[7];
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uint8_t checkSum;
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} extbhr_t, *pextbhr_t;
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struct kwb_header {
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bhr_t kwb_hdr;
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extbhr_t kwb_exthdr;
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};
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/*
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* functions
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*/
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void init_kwb_image_type (void);
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/*
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* Byte 8 of the image header contains the version number. In the v0
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* header, byte 8 was reserved, and always set to 0. In the v1 header,
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* byte 8 has been changed to a proper field, set to 1.
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*/
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static inline unsigned int image_version(void *header)
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{
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unsigned char *ptr = header;
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return ptr[8];
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}
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#endif /* _KWBIMAGE_H_ */
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@ -614,9 +614,10 @@ static int
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kwboot_img_patch_hdr(void *img, size_t size)
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{
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int rc;
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bhr_t *hdr;
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struct main_hdr_v1 *hdr;
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uint8_t csum;
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const size_t hdrsz = sizeof(*hdr);
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size_t hdrsz = sizeof(*hdr);
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int image_ver;
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rc = -1;
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hdr = img;
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@ -626,8 +627,20 @@ kwboot_img_patch_hdr(void *img, size_t size)
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goto out;
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}
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csum = kwboot_img_csum8(hdr, hdrsz) - hdr->checkSum;
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if (csum != hdr->checkSum) {
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image_ver = image_version(img);
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if (image_ver < 0) {
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fprintf(stderr, "Invalid image header version\n");
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errno = EINVAL;
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goto out;
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}
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if (image_ver == 0)
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hdrsz = sizeof(*hdr);
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else
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hdrsz = KWBHEADER_V1_SIZE(hdr);
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csum = kwboot_img_csum8(hdr, hdrsz) - hdr->checksum;
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if (csum != hdr->checksum) {
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errno = EINVAL;
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goto out;
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}
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@ -639,14 +652,18 @@ kwboot_img_patch_hdr(void *img, size_t size)
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hdr->blockid = IBR_HDR_UART_ID;
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hdr->nandeccmode = IBR_HDR_ECC_DISABLED;
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hdr->nandpagesize = 0;
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if (image_ver == 0) {
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struct main_hdr_v0 *hdr_v0 = img;
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hdr->srcaddr = hdr->ext
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? sizeof(struct kwb_header)
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: sizeof(*hdr);
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hdr_v0->nandeccmode = IBR_HDR_ECC_DISABLED;
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hdr_v0->nandpagesize = 0;
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hdr->checkSum = kwboot_img_csum8(hdr, hdrsz) - csum;
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hdr_v0->srcaddr = hdr_v0->ext
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? sizeof(struct kwb_header)
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: sizeof(*hdr_v0);
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}
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hdr->checksum = kwboot_img_csum8(hdr, hdrsz) - csum;
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rc = 0;
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out:
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||||
|
|
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