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phy: atheros: Use common functions for RGMII internal delays
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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4346df3392
commit
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1 changed files with 41 additions and 28 deletions
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@ -12,16 +12,45 @@
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#define AR803x_PHY_DEBUG_DATA_REG 0x1e
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#define AR803x_DEBUG_REG_5 0x5
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#define AR803x_RGMII_TX_CLK_DLY 0x100
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#define AR803x_RGMII_TX_CLK_DLY BIT(8)
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#define AR803x_DEBUG_REG_0 0x0
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#define AR803x_RGMII_RX_CLK_DLY 0x8000
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#define AR803x_RGMII_RX_CLK_DLY BIT(15)
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static void ar803x_enable_rx_delay(struct phy_device *phydev, bool on)
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{
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int regval;
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phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
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AR803x_DEBUG_REG_0);
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regval = phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG);
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if (on)
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regval |= AR803x_RGMII_RX_CLK_DLY;
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else
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regval &= ~AR803x_RGMII_RX_CLK_DLY;
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phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, regval);
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}
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static void ar803x_enable_tx_delay(struct phy_device *phydev, bool on)
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{
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int regval;
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phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
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AR803x_DEBUG_REG_5);
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regval = phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG);
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if (on)
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regval |= AR803x_RGMII_TX_CLK_DLY;
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else
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regval &= ~AR803x_RGMII_TX_CLK_DLY;
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phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, regval);
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}
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static int ar8021_config(struct phy_device *phydev)
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{
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phy_write(phydev, MDIO_DEVAD_NONE, 0x00, 0x1200);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
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phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
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AR803x_DEBUG_REG_5);
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phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, 0x3D47);
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phydev->supported = phydev->drv->features;
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return 0;
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@ -30,20 +59,12 @@ static int ar8021_config(struct phy_device *phydev)
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static int ar8031_config(struct phy_device *phydev)
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{
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
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phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
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AR803x_DEBUG_REG_5);
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phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
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AR803x_RGMII_TX_CLK_DLY);
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}
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phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
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ar803x_enable_tx_delay(phydev, true);
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
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phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
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AR803x_DEBUG_REG_0);
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phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
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AR803x_RGMII_RX_CLK_DLY);
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}
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phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
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ar803x_enable_rx_delay(phydev, true);
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phydev->supported = phydev->drv->features;
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@ -64,20 +85,12 @@ static int ar8035_config(struct phy_device *phydev)
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018));
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if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
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/* select debug reg 5 */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x5);
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/* enable tx delay */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x0100);
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}
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
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ar803x_enable_tx_delay(phydev, true);
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if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) {
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/* select debug reg 0 */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x0);
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/* enable rx delay */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x8000);
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}
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
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ar803x_enable_rx_delay(phydev, true);
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phydev->supported = phydev->drv->features;
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