mirror of
https://github.com/Fishwaldo/u-boot.git
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Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
This commit is contained in:
Albert ARIBAUD
commit
2a8c9c86b9
6 changed files with 102 additions and 13 deletions
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@ -10,6 +10,7 @@
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#include <asm/io.h>
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#include <common.h>
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#include <asm/arch/ddr3.h>
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#include <asm/arch/psc_defs.h>
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void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
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{
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@ -86,3 +87,77 @@ void ddr3_reset_ddrphy(void)
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tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
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__raw_writel(tmp, KS2_DDR3APLLCTL1);
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}
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#ifdef CONFIG_SOC_K2HK
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/**
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* ddr3_reset_workaround - reset workaround in case if leveling error
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* detected for PG 1.0 and 1.1 k2hk SoCs
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*/
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void ddr3_err_reset_workaround(void)
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{
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unsigned int tmp;
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unsigned int tmp_a;
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unsigned int tmp_b;
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/*
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* Check for PGSR0 error bits of DDR3 PHY.
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* Check for WLERR, QSGERR, WLAERR,
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* RDERR, WDERR, REERR, WEERR error to see if they are set or not
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*/
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tmp_a = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
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tmp_b = __raw_readl(KS2_DDR3B_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
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if (((tmp_a & 0x0FE00000) != 0) || ((tmp_b & 0x0FE00000) != 0)) {
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printf("DDR Leveling Error Detected!\n");
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printf("DDR3A PGSR0 = 0x%x\n", tmp_a);
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printf("DDR3B PGSR0 = 0x%x\n", tmp_b);
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/*
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* Write Keys to KICK registers to enable writes to registers
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* in boot config space
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*/
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__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
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__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
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/*
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* Move DDR3A Module out of reset isolation by setting
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* MDCTL23[12] = 0
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*/
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tmp_a = __raw_readl(KS2_PSC_BASE +
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PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
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tmp_a = PSC_REG_MDCTL_SET_RESET_ISO(tmp_a, 0);
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__raw_writel(tmp_a, KS2_PSC_BASE +
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PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
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/*
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* Move DDR3B Module out of reset isolation by setting
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* MDCTL24[12] = 0
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*/
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tmp_b = __raw_readl(KS2_PSC_BASE +
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PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
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tmp_b = PSC_REG_MDCTL_SET_RESET_ISO(tmp_b, 0);
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__raw_writel(tmp_b, KS2_PSC_BASE +
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PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
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/*
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* Write 0x5A69 Key to RSTCTRL[15:0] to unlock writes
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* to RSTCTRL and RSTCFG
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*/
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tmp = __raw_readl(KS2_RSTCTRL);
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tmp &= KS2_RSTCTRL_MASK;
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tmp |= KS2_RSTCTRL_KEY;
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__raw_writel(tmp, KS2_RSTCTRL);
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/*
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* Set PLL Controller to drive hard reset on SW trigger by
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* setting RSTCFG[13] = 0
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*/
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tmp = __raw_readl(KS2_RSTCTRL_RSCFG);
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tmp &= ~KS2_RSTYPE_PLL_SOFT;
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__raw_writel(tmp, KS2_RSTCTRL_RSCFG);
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reset_cpu(0);
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}
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}
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#endif
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@ -50,6 +50,7 @@ struct ddr3_emif_config {
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void ddr3_init(void);
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void ddr3_reset_ddrphy(void);
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void ddr3_err_reset_workaround(void);
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void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
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void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
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@ -121,9 +121,11 @@ typedef volatile unsigned int *dv_reg_p;
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#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE
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#define KS2_RSTCTRL_RSTYPE (KS2_PLL_CNTRL_BASE + 0xe4)
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#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8)
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#define KS2_RSTCTRL_RSCFG (KS2_PLL_CNTRL_BASE + 0xec)
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#define KS2_RSTCTRL_KEY 0x5a69
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#define KS2_RSTCTRL_MASK 0xffff0000
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#define KS2_RSTCTRL_SWRST 0xfffe0000
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#define KS2_RSTYPE_PLL_SOFT BIT(13)
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/* SPI */
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#define KS2_SPI0_BASE 0x21000400
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@ -81,4 +81,8 @@ void ddr3_init(void)
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while (1)
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;
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}
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/* Apply the workaround for PG 1.0 and 1.1 Silicons */
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if (cpu_revision() <= 1)
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ddr3_err_reset_workaround();
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}
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@ -115,6 +115,9 @@
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"nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
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"ip=dhcp\0" \
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"bootenv=uEnv.txt\0" \
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"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
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"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
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"source ${loadaddr}\0" \
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"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
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"importbootenv=echo Importing environment from mmc ...; " \
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"env import -t -r $loadaddr $filesize\0" \
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@ -142,17 +145,21 @@
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"mmcboot=mmc dev ${mmcdev}; " \
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"if mmc rescan; then " \
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"echo SD/MMC found on device ${mmcdev};" \
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"if run loadbootenv; then " \
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"echo Loaded environment from ${bootenv};" \
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"run importbootenv;" \
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"fi;" \
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"if test -n $uenvcmd; then " \
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"echo Running uenvcmd ...;" \
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"run uenvcmd;" \
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"fi;" \
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"if run loadimage; then " \
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"run mmcloados;" \
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"fi;" \
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"if run loadbootscript; then " \
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"run bootscript;" \
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"else " \
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"if run loadbootenv; then " \
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"echo Loaded environment from ${bootenv};" \
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"run importbootenv;" \
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"fi;" \
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"if test -n $uenvcmd; then " \
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"echo Running uenvcmd ...;" \
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"run uenvcmd;" \
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"fi;" \
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"if run loadimage; then " \
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"run mmcloados;" \
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"fi;" \
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"fi ;" \
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"fi;\0" \
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"spiboot=echo Booting from spi ...; " \
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"run spiargs; " \
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@ -101,10 +101,10 @@
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"vram=${vram} " \
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"root=${mmcroot} " \
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"rootfstype=${mmcrootfstype}\0" \
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"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
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"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
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"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
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"source ${loadaddr}\0" \
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"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
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"loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
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"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
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"env import -t ${loadaddr} ${filesize}\0" \
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"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
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