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mx31ads: fix 32kHz clock handling
According to schematics and to RedBoot sources, the MX31ADS uses a 32768Hz oscillator as a SKIL source. Fix previously wrongly assumed 32000Hz value. Also fix a typo when verifying a jumper configuration. While at it, make two needlessly global functions static. Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
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f3f3175746
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2ab02fd456
4 changed files with 7 additions and 9 deletions
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@ -220,7 +220,7 @@ lowlevel_init:
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mov r1, #CS4_BASE
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mov r1, #CS4_BASE
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ldrh r1, [r1, #0x2]
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ldrh r1, [r1, #0x2]
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/* Is 27MHz switch set? */
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/* Is 27MHz switch set? */
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ands r1, r1, #0x16
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ands r1, r1, #0x10
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/* 532-133-66.5 */
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/* 532-133-66.5 */
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ldr r0, =CCM_BASE
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ldr r0, =CCM_BASE
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@ -39,7 +39,7 @@ static u32 mx31_decode_pll(u32 reg, u32 infreq)
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(mfd * pd)) << 10;
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(mfd * pd)) << 10;
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}
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}
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u32 mx31_get_mpl_dpdgck_clk(void)
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static u32 mx31_get_mpl_dpdgck_clk(void)
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{
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{
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u32 infreq;
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u32 infreq;
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@ -51,7 +51,7 @@ u32 mx31_get_mpl_dpdgck_clk(void)
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return mx31_decode_pll(__REG(CCM_MPCTL), infreq);
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return mx31_decode_pll(__REG(CCM_MPCTL), infreq);
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}
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}
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u32 mx31_get_mcu_main_clk(void)
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static u32 mx31_get_mcu_main_clk(void)
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{
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{
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/* For now we assume mpl_dpdgck_clk == mcu_main_clk
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/* For now we assume mpl_dpdgck_clk == mcu_main_clk
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* which should be correct for most boards
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* which should be correct for most boards
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@ -24,9 +24,7 @@
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#ifndef __ASM_ARCH_MX31_H
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#ifndef __ASM_ARCH_MX31_H
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#define __ASM_ARCH_MX31_H
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#define __ASM_ARCH_MX31_H
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u32 mx31_get_mpl_dpdgck_clk(void);
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extern u32 mx31_get_ipg_clk(void);
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u32 mx31_get_mcu_main_clk(void);
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extern void mx31_gpio_mux(unsigned long mode);
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u32 mx31_get_ipg_clk(void);
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void mx31_gpio_mux(unsigned long mode);
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#endif /* __ASM_ARCH_MX31_H */
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#endif /* __ASM_ARCH_MX31_H */
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@ -28,7 +28,7 @@
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#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
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#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
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#define CONFIG_MX31 1 /* in a mx31 */
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#define CONFIG_MX31 1 /* in a mx31 */
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#define CONFIG_MX31_HCLK_FREQ 26000000 /* RedBoot says 26MHz */
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#define CONFIG_MX31_HCLK_FREQ 26000000 /* RedBoot says 26MHz */
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#define CONFIG_MX31_CLK32 32000
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#define CONFIG_MX31_CLK32 32768
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_DISPLAY_BOARDINFO
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@ -139,7 +139,7 @@
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#define CFG_LOAD_ADDR CONFIG_LOADADDR
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#define CFG_LOAD_ADDR CONFIG_LOADADDR
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#define CFG_HZ 32000
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#define CFG_HZ CONFIG_MX31_CLK32 /* use 32kHz clock as source */
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#define CONFIG_CMDLINE_EDITING 1
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#define CONFIG_CMDLINE_EDITING 1
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