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* Fix PHY address argument passing with mii info command

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Patch by Andrew Dyer, 28 Dec 2004

* Cleanup: fix broken builds
This commit is contained in:
Wolfgang Denk 2005-09-24 21:54:50 +02:00
parent 9ea4b5886a
commit 2b792afcc5
10 changed files with 108 additions and 46 deletions
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5
CHANGELOG
View file

@ -2,6 +2,11 @@
Changes for U-Boot 1.1.4:
======================================================================
* Cleanup: fix broken builds
* Fix PHY address argument passing with mii info command
Patch by Andrew Dyer, 28 Dec 2004
* Cleanup (PPC4xx is AMCC now)
* esd CPCI2DP board added

53
board/esd/cpci5200/Makefile Normal file
View file

@ -0,0 +1,53 @@
#
# (C) Copyright 2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
# Objects for Xilinx JTAG programming (CPLD)
# CPLD = ../common/xilinx_jtag/lenval.o \
# ../common/xilinx_jtag/micro.o \
# ../common/xilinx_jtag/ports.o
# OBJS = $(BOARD).o flash.o $(CPLD)
OBJS = $(BOARD).o strataflash.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

3
board/sandburst/karef/karef.c
View file

@ -242,7 +242,7 @@ int checkboard (void)
sys_info_t sysinfo;
unsigned char brd_rev, brd_id;
unsigned short sernum;
unsigned char scan_rev, scan_id, ofem_rev, ofem_id;
unsigned char scan_rev, scan_id, ofem_rev=0, ofem_id=0;
unsigned char ofem_brd_rev, ofem_brd_id;
KAREF_FPGA_REGS_ST *karef_ps;
OFEM_FPGA_REGS_ST *ofem_ps;
@ -349,7 +349,6 @@ int misc_init_r (void)
char envstr[255];
KAREF_FPGA_REGS_ST *karef_ps;
OFEM_FPGA_REGS_ST *ofem_ps;
unsigned char ofem_id;
if(NULL != getenv("secondserial")) {
puts("secondserial is set, switching to second serial port\n");

11
common/cmd_mii.c
View file

@ -414,7 +414,7 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
char op;
unsigned char addrlo, addrhi, reglo, reghi;
unsigned char addr = 0, reg = 0;
unsigned char addr, reg;
unsigned short data;
int rcode = 0;
@ -456,12 +456,12 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
* Look for any and all PHYs. Valid addresses are 0..31.
*/
if (argc >= 3) {
start = addr; end = addr + 1;
start = addrlo; end = addrhi;
} else {
start = 0; end = 32;
start = 0; end = 31;
}
for (j = start; j < end; j++) {
for (j = start; j <= end; j++) {
if (miiphy_info (j, &oui, &model, &rev) == 0) {
printf("PHY 0x%02X: "
"OUI = 0x%04X, "
@ -482,8 +482,7 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
"Error reading from the PHY addr=%02x reg=%02x\n",
addr, reg);
rcode = 1;
}
else {
} else {
if ((addrlo != addrhi) || (reglo != reghi))
printf("addr=%02x reg=%02x data=",
(uint)addr, (uint)reg);

1
include/configs/LANTEC.h
View file

@ -86,6 +86,7 @@
#define CONFIG_CMD_FULL (CFG_CMD_ALL & ~CFG_CMD_BEDBUG \
& ~CFG_CMD_BMP \
& ~CFG_CMD_BSP \
& ~CFG_CMD_DISPLAY \
& ~CFG_CMD_DOC \
& ~CFG_CMD_DTT \
& ~CFG_CMD_EEPROM \

21
include/configs/MPC8260ADS.h
View file

@ -48,7 +48,7 @@
* Figure out if we are booting low via flash HRCW or high via the BCSR.
*/
#if (TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */
# define CFG_LOWBOOT 1
# define CFG_LOWBOOT 1
#endif
@ -143,7 +143,7 @@
#define CFG_MDIO_PIN 0x00002000 /* PC18 */
#define CFG_MDC_PIN 0x00001000 /* PC19 */
#else
#define CFG_MDIO_PIN 0x00400000 /* PC9 */
#define CFG_MDIO_PIN 0x00400000 /* PC9 */
#define CFG_MDC_PIN 0x00200000 /* PC10 */
#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
@ -169,12 +169,12 @@
#define CFG_I2C_SLAVE 0x7F
#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
#define CONFIG_SPD_ADDR 0x50
#define CONFIG_SPD_ADDR 0x50
#endif
#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
#ifndef CONFIG_SDRAM_PBI
#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */
#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */
#endif
#ifndef CONFIG_8260_CLKIN
@ -187,16 +187,17 @@
#define CONFIG_BAUDRATE 115200
#define CFG_EXCLUDE CFG_CMD_BEDBUG | \
#define CFG_EXCLUDE CFG_CMD_BEDBUG | \
CFG_CMD_BMP | \
CFG_CMD_BSP | \
CFG_CMD_DATE | \
CFG_CMD_DISPLAY | \
CFG_CMD_DOC | \
CFG_CMD_DTT | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
CFG_CMD_EXT2 | \
CFG_CMD_FAT | \
CFG_CMD_FAT | \
CFG_CMD_FDC | \
CFG_CMD_FDOS | \
CFG_CMD_HWFLOW | \
@ -205,7 +206,7 @@
CFG_CMD_MMC | \
CFG_CMD_NAND | \
CFG_CMD_PCI | \
CFG_CMD_PCMCIA | \
CFG_CMD_PCMCIA | \
CFG_CMD_REISER | \
CFG_CMD_SCSI | \
CFG_CMD_SPI | \
@ -241,7 +242,7 @@
#endif
#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
/*
* Miscellaneous configurable options

57
include/configs/MPC8266ADS.h
View file

@ -31,13 +31,13 @@
*/
/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!! !!
!! !!
!! This configuration requires JP3 to be in position 1-2 to work !!
!! To make it work for the default, the TEXT_BASE define in !!
!! To make it work for the default, the TEXT_BASE define in !!
!! board/mpc8266ads/config.mk must be changed from 0xfe000000 to !!
!! 0xfff00000 !!
!! The CFG_HRCW_MASTER define below must also be changed to match !!
!! !!
!! !!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
*/
@ -139,23 +139,24 @@
* Definitions for Serial Presence Detect EEPROM address
* (to get SDRAM settings)
*/
#define SPD_EEPROM_ADDRESS 0x50
#define SPD_EEPROM_ADDRESS 0x50
#define CONFIG_8260_CLKIN 66000000 /* in Hz */
#define CONFIG_BAUDRATE 115200
#define CONFIG_COMMANDS ( CFG_CMD_ALL & ~( \
CFG_CMD_BEDBUG | \
#define CONFIG_COMMANDS ( CFG_CMD_ALL & ~( \
CFG_CMD_BEDBUG | \
CFG_CMD_BMP | \
CFG_CMD_BSP | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DHCP | \
CFG_CMD_DISPLAY | \
CFG_CMD_DOC | \
CFG_CMD_DTT | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
CFG_CMD_EXT2 | \
CFG_CMD_FDC | \
CFG_CMD_FDOS | \
@ -165,7 +166,7 @@
CFG_CMD_KGDB | \
CFG_CMD_MMC | \
CFG_CMD_NAND | \
CFG_CMD_PCMCIA | \
CFG_CMD_PCMCIA | \
CFG_CMD_REISER | \
CFG_CMD_SCSI | \
CFG_CMD_SPI | \
@ -178,8 +179,8 @@
/* Define a command string that is automatically executed when no character
* is read on the console interface withing "Boot Delay" after reset.
*/
#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
#ifdef CONFIG_BOOT_ROOT_INITRD
#define CONFIG_BOOTCOMMAND \
@ -457,7 +458,7 @@
/*-----------------------------------------------------------------------
* HIDx - Hardware Implementation-dependent Registers 2-11
* HIDx - Hardware Implementation-dependent Registers 2-11
*-----------------------------------------------------------------------
* HID0 also contains cache control - initially enable both caches and
* invalidate contents, then the final state leaves only the instruction
@ -489,7 +490,7 @@
* 0x80000000-0x9FFFFFFF 512MB outbound prefetchable PCI memory window
* 0xA0000000-0xBFFFFFFF 512MB outbound non-prefetchable PCI memory window
* 0xF0000000-0xF001FFFF 128KB MPC8266 internal memory
* 0xF4000000-0xF7FFFFFF 64MB outbound PCI I/O window
* 0xF4000000-0xF7FFFFFF 64MB outbound PCI I/O window
* 0xF8000000-0xF8007FFF 32KB BCSR
* 0xF8100000-0xF8107FFF 32KB ATM UNI
* 0xF8200000-0xF8207FFF 32KB PCI interrupt controller
@ -543,10 +544,10 @@
* in the bridge.
*/
#define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
#define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
#define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
#define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
#define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
#define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
#define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
#define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
#define CFG_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
/*
@ -555,11 +556,11 @@
* in the bridge.
*/
#define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
#define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
#define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
#define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
#define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
#define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
#define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
#define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
#define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
#define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
/*
* Master window that allows the CPU to access PCI IO space.
@ -567,11 +568,11 @@
* in the bridge.
*/
#define CFG_PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */
#define CFG_PCI_MSTR_IO_BUS 0xF4000000 /* PCI base */
#define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
#define CFG_PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */
#define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO)
#define CFG_PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */
#define CFG_PCI_MSTR_IO_BUS 0xF4000000 /* PCI base */
#define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
#define CFG_PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */
#define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO)
/*
* JFFS2 partitions

1
include/configs/RBC823.h
View file

@ -97,6 +97,7 @@
#define CONFIG_COMMANDS ( CFG_CMD_ALL & \
~CFG_CMD_BSP & \
~CFG_CMD_DATE & \
~CFG_CMD_DISPLAY& \
~CFG_CMD_DTT & \
~CFG_CMD_EXT2 & \
~CFG_CMD_FDC & \

1
include/configs/ep8260.h
View file

@ -299,6 +299,7 @@
CFG_CMD_BSP | \
CFG_CMD_DCR | \
CFG_CMD_DHCP | \
CFG_CMD_DISPLAY | \
CFG_CMD_DOC | \
CFG_CMD_DTT | \
CFG_CMD_EEPROM | \

1
include/configs/hymod.h
View file

@ -177,6 +177,7 @@
#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
CFG_CMD_BEDBUG | \
CFG_CMD_BMP | \
CFG_CMD_DISPLAY | \
CFG_CMD_DOC | \
CFG_CMD_EXT2 | \
CFG_CMD_FDC | \