mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 21:21:37 +00:00
am335x: fix GPMC config for NAND and NOR SPL boot
GPMC controller is common IP to interface with both NAND and NOR flash devices. Also, it supports max 8 chip-selects, which can be independently connected to any of the devices. But ROM code expects the boot-device to be connected to only chip-select[0]. Thus to resolve conflict between NOR and NAND boot. This patch: - combines NOR and NAND configs spread in board files to common gpmc_init() - configures GPMC based on boot-mode selected for SPL boot. Signed-off-by: Pekon Gupta <pekon@ti.com>
This commit is contained in:
parent
3f719069c8
commit
2c17e6d1d9
3 changed files with 30 additions and 41 deletions
|
@ -22,17 +22,6 @@
|
||||||
|
|
||||||
struct gpmc *gpmc_cfg;
|
struct gpmc *gpmc_cfg;
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_NAND)
|
|
||||||
static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
|
|
||||||
M_NAND_GPMC_CONFIG1,
|
|
||||||
M_NAND_GPMC_CONFIG2,
|
|
||||||
M_NAND_GPMC_CONFIG3,
|
|
||||||
M_NAND_GPMC_CONFIG4,
|
|
||||||
M_NAND_GPMC_CONFIG5,
|
|
||||||
M_NAND_GPMC_CONFIG6, 0
|
|
||||||
};
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
|
void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
|
||||||
u32 size)
|
u32 size)
|
||||||
|
@ -61,11 +50,34 @@ void gpmc_init(void)
|
||||||
{
|
{
|
||||||
/* putting a blanket check on GPMC based on ZeBu for now */
|
/* putting a blanket check on GPMC based on ZeBu for now */
|
||||||
gpmc_cfg = (struct gpmc *)GPMC_BASE;
|
gpmc_cfg = (struct gpmc *)GPMC_BASE;
|
||||||
|
#if defined(CONFIG_NOR)
|
||||||
#ifdef CONFIG_CMD_NAND
|
/* configure GPMC for NOR */
|
||||||
const u32 *gpmc_config = NULL;
|
const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
|
||||||
u32 base = 0;
|
STNOR_GPMC_CONFIG2,
|
||||||
|
STNOR_GPMC_CONFIG3,
|
||||||
|
STNOR_GPMC_CONFIG4,
|
||||||
|
STNOR_GPMC_CONFIG5,
|
||||||
|
STNOR_GPMC_CONFIG6,
|
||||||
|
STNOR_GPMC_CONFIG7
|
||||||
|
};
|
||||||
|
u32 size = GPMC_SIZE_16M;
|
||||||
|
u32 base = CONFIG_SYS_FLASH_BASE;
|
||||||
|
#elif defined(CONFIG_NAND)
|
||||||
|
/* configure GPMC for NAND */
|
||||||
|
const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1,
|
||||||
|
M_NAND_GPMC_CONFIG2,
|
||||||
|
M_NAND_GPMC_CONFIG3,
|
||||||
|
M_NAND_GPMC_CONFIG4,
|
||||||
|
M_NAND_GPMC_CONFIG5,
|
||||||
|
M_NAND_GPMC_CONFIG6,
|
||||||
|
0
|
||||||
|
};
|
||||||
|
u32 size = GPMC_SIZE_256M;
|
||||||
|
u32 base = CONFIG_SYS_NAND_BASE;
|
||||||
|
#else
|
||||||
|
const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
|
||||||
u32 size = 0;
|
u32 size = 0;
|
||||||
|
u32 base = 0;
|
||||||
#endif
|
#endif
|
||||||
/* global settings */
|
/* global settings */
|
||||||
writel(0x00000008, &gpmc_cfg->sysconfig);
|
writel(0x00000008, &gpmc_cfg->sysconfig);
|
||||||
|
@ -81,12 +93,6 @@ void gpmc_init(void)
|
||||||
*/
|
*/
|
||||||
writel(0, &gpmc_cfg->cs[0].config7);
|
writel(0, &gpmc_cfg->cs[0].config7);
|
||||||
sdelay(1000);
|
sdelay(1000);
|
||||||
|
/* enable chip-select specific configurations */
|
||||||
#ifdef CONFIG_CMD_NAND
|
enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
|
||||||
gpmc_config = gpmc_m_nand;
|
|
||||||
|
|
||||||
base = PISMO1_NAND_BASE;
|
|
||||||
size = PISMO1_NAND_SIZE;
|
|
||||||
enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
|
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
|
@ -68,9 +68,4 @@
|
||||||
#define PISMO2_NAND_CS0 7
|
#define PISMO2_NAND_CS0 7
|
||||||
#define PISMO2_NAND_CS1 8
|
#define PISMO2_NAND_CS1 8
|
||||||
|
|
||||||
/* make it readable for the gpmc_init */
|
|
||||||
#define PISMO1_NOR_BASE FLASH_BASE
|
|
||||||
#define PISMO1_NAND_BASE CONFIG_SYS_NAND_BASE
|
|
||||||
#define PISMO1_NAND_SIZE GPMC_SIZE_256M
|
|
||||||
|
|
||||||
#endif /* endif _MEM_H_ */
|
#endif /* endif _MEM_H_ */
|
||||||
|
|
|
@ -481,26 +481,14 @@ void sdram_init(void)
|
||||||
*/
|
*/
|
||||||
int board_init(void)
|
int board_init(void)
|
||||||
{
|
{
|
||||||
#ifdef CONFIG_NOR
|
|
||||||
const u32 gpmc_nor[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
|
|
||||||
STNOR_GPMC_CONFIG2, STNOR_GPMC_CONFIG3, STNOR_GPMC_CONFIG4,
|
|
||||||
STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 };
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CONFIG_HW_WATCHDOG)
|
#if defined(CONFIG_HW_WATCHDOG)
|
||||||
hw_watchdog_init();
|
hw_watchdog_init();
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||||
|
#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
|
||||||
gpmc_init();
|
gpmc_init();
|
||||||
|
|
||||||
#ifdef CONFIG_NOR
|
|
||||||
/* Reconfigure CS0 for NOR instead of NAND. */
|
|
||||||
enable_gpmc_cs_config(gpmc_nor, &gpmc_cfg->cs[0],
|
|
||||||
CONFIG_SYS_FLASH_BASE, GPMC_SIZE_16M);
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
Loading…
Add table
Reference in a new issue