From da0be4e176dcd86fb4d18a31b5be9822d5463f83 Mon Sep 17 00:00:00 2001 From: Jack Mitchell Date: Thu, 17 Sep 2020 10:42:06 +0100 Subject: [PATCH 01/19] clk: rockchip: rk3399: implement getting wdt/alive clocks In order to correctly calculate the designware watchdog timeouts, the watchdog clock is required. Implement required clocks to facilitate this. Signed-off-by: Jack Mitchell Reviewed-by: Philipp Tomsich Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_rk3399.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 22c373a623..44fb8ca956 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -233,6 +233,10 @@ enum { DCLK_VOP_DIV_CON_MASK = 0xff, DCLK_VOP_DIV_CON_SHIFT = 0, + /* CLKSEL_CON57 */ + PCLK_ALIVE_DIV_CON_SHIFT = 0, + PCLK_ALIVE_DIV_CON_MASK = 0x1f << PCLK_ALIVE_DIV_CON_SHIFT, + /* CLKSEL_CON58 */ CLK_SPI_PLL_SEL_WIDTH = 1, CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1), @@ -867,6 +871,17 @@ static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru, return set_rate; } +static ulong rk3399_alive_get_clk(struct rockchip_cru *cru) +{ + u32 div, val; + + val = readl(&cru->clksel_con[57]); + div = (val & PCLK_ALIVE_DIV_CON_MASK) >> + PCLK_ALIVE_DIV_CON_SHIFT; + + return DIV_TO_RATE(GPLL_HZ, div); +} + static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru) { u32 div, val; @@ -936,6 +951,10 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case ACLK_GIC_PRE: case PCLK_DDR: break; + case PCLK_ALIVE: + case PCLK_WDT: + rate = rk3399_alive_get_clk(priv->cru); + break; default: log_debug("Unknown clock %lu\n", clk->id); return -ENOENT; @@ -1502,6 +1521,7 @@ static ulong rk3399_pmuclk_get_rate(struct clk *clk) case PLL_PPLL: return PPLL_HZ; case PCLK_RKPWM_PMU: + case PCLK_WDT_M0_PMU: rate = rk3399_pwm_get_clk(priv->pmucru); break; case SCLK_I2C0_PMU: From cfac752dad9d1e975022c6274c9709c0d640aa91 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Fri, 4 Sep 2020 16:11:08 +0200 Subject: [PATCH 02/19] rockchip: dts: tinker: move i2c node to shared device tree The I2C EEPROM is present on Tinker Board S as well. Move the i2c node to the shared, U-Boot specific rk3288-tinker-u-boot.dtsi device tree. Cc: Jonas Karlman Signed-off-by: Stefan Agner Reviewed-by: Kever Yang --- arch/arm/dts/rk3288-tinker-u-boot.dtsi | 7 +++++++ arch/arm/dts/rk3288-tinker.dts | 7 ------- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/dts/rk3288-tinker-u-boot.dtsi b/arch/arm/dts/rk3288-tinker-u-boot.dtsi index 732aa4f91f..56d10c82ec 100644 --- a/arch/arm/dts/rk3288-tinker-u-boot.dtsi +++ b/arch/arm/dts/rk3288-tinker-u-boot.dtsi @@ -17,6 +17,13 @@ rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>; }; +&i2c2 { + m24c08@50 { + compatible = "at,24c08", "i2c-eeprom"; + reg = <0x50>; + }; +}; + &pinctrl { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/rk3288-tinker.dts b/arch/arm/dts/rk3288-tinker.dts index 4b8405fd82..338670123b 100644 --- a/arch/arm/dts/rk3288-tinker.dts +++ b/arch/arm/dts/rk3288-tinker.dts @@ -35,10 +35,3 @@ vbus-supply = <&vcc5v0_host>; status = "okay"; }; - -&i2c2 { - m24c08@50 { - compatible = "at,24c08", "i2c-eeprom"; - reg = <0x50>; - }; -}; From ee68c83d0a08dd80c82a2e31ec604e877075e366 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Fri, 4 Sep 2020 16:11:09 +0200 Subject: [PATCH 03/19] rockchip: dts: tinker: remove unnecessary node The property reg-shift with the same value is present in the base device tree already. Remove unnecessary node from rk3288-tinker.dts. Signed-off-by: Stefan Agner Reviewed-by: Kever Yang --- arch/arm/dts/rk3288-tinker.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/dts/rk3288-tinker.dts b/arch/arm/dts/rk3288-tinker.dts index 338670123b..8b1848c310 100644 --- a/arch/arm/dts/rk3288-tinker.dts +++ b/arch/arm/dts/rk3288-tinker.dts @@ -27,10 +27,6 @@ status = "okay"; }; -&uart2 { - reg-shift = <2>; -}; - &usb_host1 { vbus-supply = <&vcc5v0_host>; status = "okay"; From e6dcfff8e6f0ddd1358c9787639e91f7612992ab Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 29 Sep 2020 14:06:18 +0100 Subject: [PATCH 04/19] rockchip: Rock960: fix up USB support Fix up USB config options so keyboards and other USB devices work. Signed-off-by: Peter Robinson Reviewed-by: Kever Yang Change-Id: I34b0696e0ac7303186f20c83278dde340399b690 --- configs/rock960-rk3399_defconfig | 9 ++++++--- include/configs/rock960_rk3399.h | 2 ++ 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 1d997847c2..a5a50785c5 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -3,12 +3,12 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 CONFIG_TARGET_ROCK960_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960" CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" CONFIG_MISC_INIT_R=y CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -41,6 +41,8 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y CONFIG_NVME=y CONFIG_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y @@ -54,10 +56,11 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC3=y -CONFIG_ROCKCHIP_USB2_PHY=y +CONFIG_DM_KEYBOARD=y CONFIG_USB_KEYBOARD=y -CONFIG_USB_GADGET=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y diff --git a/include/configs/rock960_rk3399.h b/include/configs/rock960_rk3399.h index c6f9122154..2edad71028 100644 --- a/include/configs/rock960_rk3399.h +++ b/include/configs/rock960_rk3399.h @@ -15,4 +15,6 @@ #define SDRAM_BANK_SIZE (2UL << 30) +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #endif From 2db36c64bd5a8910112708c1c6b68bd3594517d3 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 1 Oct 2020 20:40:03 +0200 Subject: [PATCH 05/19] ram: rockchip: px30: add a config-based ddr selection The SRAM on the PX30 is not big enough to hold multiple DDR configs so it needs to be selected during build. So far simply the DDR3 config was always selected and getting DDR4 or LPDDR2/3 initialized would require a code modification. So add Kconfig options similar to RK3399 to allow selecting the DDR4 and LPDDR2/3 options instead, while DDR3 stays the default as before. Signed-off-by: Heiko Stuebner Reviewed-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/ram/rockchip/Kconfig | 21 +++++++++++++++++++++ drivers/ram/rockchip/sdram_px30.c | 8 ++++++++ 2 files changed, 29 insertions(+) diff --git a/drivers/ram/rockchip/Kconfig b/drivers/ram/rockchip/Kconfig index 8e97c2f49e..c459bbf5e2 100644 --- a/drivers/ram/rockchip/Kconfig +++ b/drivers/ram/rockchip/Kconfig @@ -22,6 +22,27 @@ config RAM_ROCKCHIP_DEBUG This is an option for developers to understand the ram drivers initialization, configurations and etc. +config RAM_PX30_DDR4 + bool "DDR3 support for Rockchip PX30" + depends on RAM_ROCKCHIP && ROCKCHIP_PX30 + help + This enables DDR4 sdram support instead of the default DDR3 support + on Rockchip PC30 SoCs. + +config RAM_PX30_LPDDR2 + bool "LPDDR2 support for Rockchip PX30" + depends on RAM_ROCKCHIP && ROCKCHIP_PX30 + help + This enables LPDDR2 sdram support instead of the default DDR3 support + on Rockchip PC30 SoCs. + +config RAM_PX30_LPDDR3 + bool "LPDDR3 support for Rockchip PX30" + depends on RAM_ROCKCHIP && ROCKCHIP_PX30 + help + This enables LPDDR3 sdram support instead of the default DDR3 support + on Rockchip PC30 SoCs. + config RAM_RK3399_LPDDR4 bool "LPDDR4 support for Rockchip RK3399" depends on RAM_ROCKCHIP && ROCKCHIP_RK3399 diff --git a/drivers/ram/rockchip/sdram_px30.c b/drivers/ram/rockchip/sdram_px30.c index fd5763d0a0..2f1f6e9c0c 100644 --- a/drivers/ram/rockchip/sdram_px30.c +++ b/drivers/ram/rockchip/sdram_px30.c @@ -125,7 +125,15 @@ u32 addrmap[][8] = { struct dram_info dram_info; struct px30_sdram_params sdram_configs[] = { +#if defined(CONFIG_RAM_PX30_DDR4) +#include "sdram-px30-ddr4-detect-333.inc" +#elif defined(CONFIG_RAM_PX30_LPDDR2) +#include "sdram-px30-lpddr2-detect-333.inc" +#elif defined(CONFIG_RAM_PX30_LPDDR3) +#include "sdram-px30-lpddr3-detect-333.inc" +#else #include "sdram-px30-ddr3-detect-333.inc" +#endif }; struct ddr_phy_skew skew = { From 127c8d85cf4420167ed577121ea62f56ce13635e Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak Date: Tue, 6 Oct 2020 23:39:51 +0300 Subject: [PATCH 06/19] video: rockchip: Add missing dpcd_write() call to link_train_ce() Found this by comparing it to the coreboot driver, a form of this call was introduced there in their commit b9a7877568cf ("rockchip/*: refactor edp driver"). This is copy-pasted from U-Boot's link_train_cr() slightly above it. Without this on a gru-kevin chromebook, I have: clock recovery at voltage 0 pre-emphasis 0 requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB using signal parameters: voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB using signal parameters: voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB using signal parameters: voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB using signal parameters: voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB using signal parameters: voltage 0.4V pre_emph 3.5dB channel eq failed, ret=-5 link train failed! rk_vop_probe() Device failed: ret=-5 With this, it looks like training succeeds: clock recovery at voltage 0 pre-emphasis 0 requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB using signal parameters: voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 0 voltage 0.4V pre_emph 6dB requested signal parameters: lane 1 voltage 0.4V pre_emph 6dB requested signal parameters: lane 2 voltage 0.4V pre_emph 6dB requested signal parameters: lane 3 voltage 0.4V pre_emph 6dB using signal parameters: voltage 0.4V pre_emph 6dB requested signal parameters: lane 0 voltage 0.4V pre_emph 0dB requested signal parameters: lane 1 voltage 0.4V pre_emph 0dB requested signal parameters: lane 2 voltage 0.4V pre_emph 0dB requested signal parameters: lane 3 voltage 0.4V pre_emph 0dB using signal parameters: voltage 0.4V pre_emph 0dB channel eq at voltage 0 pre-emphasis 0 config video failed rk_vop_probe() Device failed: ret=-110 The "config video failed" error also goes away when I disable higher log levels, and it claims to have successfully probed the device. Signed-off-by: Alper Nebi Yasak Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- drivers/video/rockchip/rk_edp.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c index 000bd48140..a032eb6889 100644 --- a/drivers/video/rockchip/rk_edp.c +++ b/drivers/video/rockchip/rk_edp.c @@ -559,6 +559,12 @@ static int rk_edp_link_train_ce(struct rk_edp_priv *edp) channel_eq = 0; for (tries = 0; tries < 5; tries++) { rk_edp_set_link_training(edp, edp->train_set); + ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET, + edp->train_set, + edp->link_train.lane_count); + if (ret) + return ret; + udelay(400); if (rk_edp_dpcd_read_link_status(edp, status) < 0) { From cffcd48109a650047fe5a3fcd3dec9bf5438e6da Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sat, 24 Oct 2020 01:27:22 +0530 Subject: [PATCH 07/19] rockchip: Enable Console MUX in ROCKPi N10 Enable Console multiplexing in ROCKPi N10 which would is required to video out the console buffer. Enable it. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- configs/rock-pi-n10-rk3399pro_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig index 3632ad77c7..8065897ed1 100644 --- a/configs/rock-pi-n10-rk3399pro_defconfig +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -11,7 +11,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEFAULT_DEVICE_TREE="rk3399pro-rock-pi-n10" CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set -# CONFIG_CONSOLE_MUX is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399pro-rock-pi-n10.dtb" CONFIG_MISC_INIT_R=y CONFIG_DISPLAY_BOARDINFO_LATE=y From dfec5a4ec035ada6fef0baa68ea12c007d598d0a Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sat, 24 Oct 2020 01:27:23 +0530 Subject: [PATCH 08/19] arm64: dts: rockchip: Add chosen node for ROCK-Pi N8 Add chosen node in -u-boot.dtsi for ROCK-Pi N8 board. This will help to get serial out messages. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi b/arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi index e9d7404ed9..538607dd73 100644 --- a/arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi +++ b/arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi @@ -5,6 +5,12 @@ #include "rk3288-u-boot.dtsi" +/{ + chosen { + stdout-path = &uart2; + }; +}; + &dmc { rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 From 9abece398513fdbfee6c3f84326e232d821088b0 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sat, 24 Oct 2020 01:27:24 +0530 Subject: [PATCH 09/19] video: rockchip: Support 4K resolution for rk3288, HDMI Like, rk3399 the rk3288 also supports 4K resolution. So, enable it for rk3288 with HDMI platforms. Right now, rockchip video drivers are supporting for rk3288, rk3399 SoC families, so mark the 4K resolution by default if it's an HDMI video out. Signed-off-by: Jagan Teki Cc: Anatolij Gustschin Reviewed-by: Kever Yang --- drivers/video/rockchip/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig index 5215a71f99..0ade631bd5 100644 --- a/drivers/video/rockchip/Kconfig +++ b/drivers/video/rockchip/Kconfig @@ -22,7 +22,7 @@ menuconfig VIDEO_ROCKCHIP config VIDEO_ROCKCHIP_MAX_XRES int "Maximum horizontal resolution (for memory allocation purposes)" depends on VIDEO_ROCKCHIP - default 3840 if ROCKCHIP_RK3399 && DISPLAY_ROCKCHIP_HDMI + default 3840 if DISPLAY_ROCKCHIP_HDMI default 1920 help The maximum horizontal resolution to support for the framebuffer. @@ -32,7 +32,7 @@ config VIDEO_ROCKCHIP_MAX_XRES config VIDEO_ROCKCHIP_MAX_YRES int "Maximum vertical resolution (for memory allocation purposes)" depends on VIDEO_ROCKCHIP - default 2160 if ROCKCHIP_RK3399 && DISPLAY_ROCKCHIP_HDMI + default 2160 if DISPLAY_ROCKCHIP_HDMI default 1080 help The maximum vertical resolution to support for the framebuffer. From d2ebd86d2e10370b4e27109b341ca0268c84f5c8 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sat, 24 Oct 2020 01:27:25 +0530 Subject: [PATCH 10/19] rockchip: Enable Console MUX in ROCKPi N8 Enable Console multiplexing in ROCKPi N8 which would is required to video out the console buffer. Enable it. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- configs/rock-pi-n8-rk3288_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/rock-pi-n8-rk3288_defconfig b/configs/rock-pi-n8-rk3288_defconfig index ce5c921066..7615f61031 100644 --- a/configs/rock-pi-n8-rk3288_defconfig +++ b/configs/rock-pi-n8-rk3288_defconfig @@ -15,7 +15,6 @@ CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set CONFIG_DEFAULT_FDT_FILE="rk3288-rock-pi-n8.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y From 29ef48efe131678a02750f0a8daa5b2b71530e87 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 24 Oct 2020 11:43:17 -0500 Subject: [PATCH 11/19] rockchip: mkimage: Remove host endianness dependency The Rockchip boot ROM expects little-endian values in the image header. When running mkimage on a big-endian machine, these values need to be byteswapped before writing or verifying the header. This change fixes cross-compiling U-Boot SPL for the RK3399 SoC from a big-endian ppc64 host machine. Signed-off-by: Samuel Holland Reviewed-by: Kever Yang --- tools/rkcommon.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/tools/rkcommon.c b/tools/rkcommon.c index 61c392e27d..d55cd2c2d5 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -221,12 +221,13 @@ bool rkcommon_need_rc4_spl(struct image_tool_params *params) static void rkcommon_set_header0(void *buf, struct image_tool_params *params) { struct header0_info *hdr = buf; + uint32_t init_boot_size; memset(buf, '\0', RK_INIT_OFFSET * RK_BLK_SIZE); - hdr->signature = RK_SIGNATURE; - hdr->disable_rc4 = !rkcommon_need_rc4_spl(params); - hdr->init_offset = RK_INIT_OFFSET; - hdr->init_size = spl_params.init_size / RK_BLK_SIZE; + hdr->signature = cpu_to_le32(RK_SIGNATURE); + hdr->disable_rc4 = cpu_to_le32(!rkcommon_need_rc4_spl(params)); + hdr->init_offset = cpu_to_le16(RK_INIT_OFFSET); + hdr->init_size = cpu_to_le16(spl_params.init_size / RK_BLK_SIZE); /* * init_boot_size needs to be set, as it is read by the BootROM @@ -237,11 +238,10 @@ static void rkcommon_set_header0(void *buf, struct image_tool_params *params) * for a more detailed explanation by Andy Yan */ if (spl_params.boot_file) - hdr->init_boot_size = - hdr->init_size + spl_params.boot_size / RK_BLK_SIZE; + init_boot_size = spl_params.init_size + spl_params.boot_size; else - hdr->init_boot_size = - hdr->init_size + RK_MAX_BOOT_SIZE / RK_BLK_SIZE; + init_boot_size = spl_params.init_size + RK_MAX_BOOT_SIZE; + hdr->init_boot_size = cpu_to_le16(init_boot_size / RK_BLK_SIZE); rc4_encode(buf, RK_BLK_SIZE, rc4_key); } @@ -294,14 +294,14 @@ static int rkcommon_parse_header(const void *buf, struct header0_info *header0, memcpy((void *)header0, buf, sizeof(struct header0_info)); rc4_encode((void *)header0, sizeof(struct header0_info), rc4_key); - if (header0->signature != RK_SIGNATURE) + if (le32_to_cpu(header0->signature) != RK_SIGNATURE) return -EPROTO; /* We don't support RC4 encoded image payloads here, yet... */ - if (header0->disable_rc4 == 0) + if (le32_to_cpu(header0->disable_rc4) == 0) return -ENOSYS; - hdr1_offset = header0->init_offset * RK_BLK_SIZE; + hdr1_offset = le16_to_cpu(header0->init_offset) * RK_BLK_SIZE; hdr1_sdmmc = (struct header1_info *)(buf + hdr1_offset); hdr1_spi = (struct header1_info *)(buf + rkcommon_offset_to_spi(hdr1_offset)); @@ -359,7 +359,7 @@ void rkcommon_print_header(const void *buf) struct header0_info header0; struct spl_info *spl_info; uint8_t image_type; - int ret, boot_size; + int ret, boot_size, init_size; ret = rkcommon_parse_header(buf, &header0, &spl_info); @@ -377,9 +377,10 @@ void rkcommon_print_header(const void *buf) printf("Image Type: Rockchip %s (%s) boot image\n", spl_info->spl_hdr, (image_type == IH_TYPE_RKSD) ? "SD/MMC" : "SPI"); - printf("Init Data Size: %d bytes\n", header0.init_size * RK_BLK_SIZE); + init_size = le16_to_cpu(header0.init_size) * RK_BLK_SIZE; + printf("Init Data Size: %d bytes\n", init_size); - boot_size = (header0.init_boot_size - header0.init_size) * RK_BLK_SIZE; + boot_size = le16_to_cpu(header0.init_boot_size) * RK_BLK_SIZE - init_size; if (boot_size != RK_MAX_BOOT_SIZE) printf("Boot Data Size: %d bytes\n", boot_size); } From 282ad86aaa57edd783ac81d2dcb19b1fe89c1bbe Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 28 Oct 2020 19:03:41 +0530 Subject: [PATCH 12/19] arm64: dts: rockchip: px30: Add Engicam EDIMM2.2 Starter Kit Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board. Genaral features: - LCD 7" C.Touch - microSD slot - Ethernet 1Gb - Wifi/BT - 2x LVDS Full HD interfaces - 3x USB 2.0 - 1x USB 3.0 - HDMI Out - Mini PCIe - MIPI CSI - 2x CAN - Audio Out SOM's like PX30.Core needs to mount on top of this Evaluation board for creating complete PX30.Core EDIMM2.2 Starter Kit. Add support for it. Signed-off-by: Jagan Teki Signed-off-by: Michael Trimarchi Reviewed-by: Kever Yang --- arch/arm/dts/px30-engicam-common.dtsi | 39 +++++++++++++++++++++++++ arch/arm/dts/px30-engicam-edimm2.2.dtsi | 7 +++++ 2 files changed, 46 insertions(+) create mode 100644 arch/arm/dts/px30-engicam-common.dtsi create mode 100644 arch/arm/dts/px30-engicam-edimm2.2.dtsi diff --git a/arch/arm/dts/px30-engicam-common.dtsi b/arch/arm/dts/px30-engicam-common.dtsi new file mode 100644 index 0000000000..bd5bde989e --- /dev/null +++ b/arch/arm/dts/px30-engicam-common.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/ { + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; /* +5V */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&gmac { + clock_in_out = "output"; + phy-supply = <&vcc_3v3>; /* +3V3_SOM */ + snps,reset-active-low; + snps,reset-delays-us = <0 50000 50000>; + snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&sdmmc { + cap-sd-highspeed; + card-detect-delay = <800>; + vmmc-supply = <&vcc_3v3>; /* +3V3_SOM */ + vqmmc-supply = <&vcc_3v3>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m1_xfer>; + status = "okay"; +}; diff --git a/arch/arm/dts/px30-engicam-edimm2.2.dtsi b/arch/arm/dts/px30-engicam-edimm2.2.dtsi new file mode 100644 index 0000000000..cb00988953 --- /dev/null +++ b/arch/arm/dts/px30-engicam-edimm2.2.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +#include "px30-engicam-common.dtsi" From 9946bfd4a093ad71f5072df9e20e86db41657e1c Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Wed, 28 Oct 2020 19:03:42 +0530 Subject: [PATCH 13/19] arm64: dts: rockchip: Add Engicam PX30.Core SOM PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. General features: - Rockchip PX30 - Up to 2GB DDR4 - eMMC 4 GB expandible - rest of PX30 features PX30.Core needs to mount on top of Engicam baseboards for creating complete platform boards. Possible baseboards are, - EDIMM2.2 - C.TOUCH 2.0 Add support for it. Signed-off-by: Jagan Teki Signed-off-by: Michael Trimarchi Reviewed-by: Kever Yang --- arch/arm/dts/px30-px30-core.dtsi | 232 +++++++++++++++++++++++++++++++ 1 file changed, 232 insertions(+) create mode 100644 arch/arm/dts/px30-px30-core.dtsi diff --git a/arch/arm/dts/px30-px30-core.dtsi b/arch/arm/dts/px30-px30-core.dtsi new file mode 100644 index 0000000000..16e6cf28a4 --- /dev/null +++ b/arch/arm/dts/px30-px30-core.dtsi @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutons + * Copyright (c) 2020 Amarula Solutons(India) + */ + +#include +#include + +/ { + compatible = "engicam,px30-px30-core", "rockchip,px30"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-name = "vcc_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_1v0: LDO_REG3 { + regulator-name = "vdd_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-name = "vcc3v0_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc5v0_host: SWITCH_REG2 { + regulator-name = "vcc5v0_host"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&io_domains { + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vcc_3v3>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int: pmic_int { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc_3v3>; + pmuio2-supply = <&vcc_3v3>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; From cf1b86a3ae319fb396ef9cca3788b43ab0fd3a1c Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 28 Oct 2020 19:03:43 +0530 Subject: [PATCH 14/19] rockchip: px30: Add EVB_PX30 Kconfig help TARGET_EVB_PX30 can be possible to use other px30 boards. Add the help text for existing EVB, so-that the new boards which are resuing this config option can mention their board help text. This would help to track which boards are using EVB_PX30 config. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/px30/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index f5373c6f9f..6cd65dfa97 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -2,6 +2,11 @@ if ROCKCHIP_PX30 config TARGET_EVB_PX30 bool "EVB_PX30" + help + This target config option used for below listed px30 boards. + + EVB_PX30: + * EVB_PX30 is an evaluation board for Rockchip PX30. config TARGET_ODROID_GO2 bool "ODROID_GO2" From ce87a88b4dec9fe7f0f1bbeaa4526ec5da14c333 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 28 Oct 2020 19:03:44 +0530 Subject: [PATCH 15/19] board: engicam: Attach i.MX6 common code The existing common code for Engicam boards uses i.MX6, so attach that into i.MX6 Engicam boards so-that adding new SoC variants of Engicam boards become meaningful. Add support for it. Cc: Stefano Babic Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- board/engicam/common/Kconfig | 8 ++++++++ board/engicam/common/Makefile | 7 +++++-- board/engicam/imx6q/Kconfig | 2 ++ board/engicam/imx6ul/Kconfig | 2 ++ 4 files changed, 17 insertions(+), 2 deletions(-) create mode 100644 board/engicam/common/Kconfig diff --git a/board/engicam/common/Kconfig b/board/engicam/common/Kconfig new file mode 100644 index 0000000000..38328fd5ea --- /dev/null +++ b/board/engicam/common/Kconfig @@ -0,0 +1,8 @@ +config IMX6_ENGICAM_COMMON + bool "Engicam i.MX6 Common code" + depends on SPL && MX6 + default y if TARGET_MX6Q_ENGICAM || TARGET_MX6UL_ENGICAM + help + Common SPL and U-Boot proper code for Engicam i.MX6 targets. + + Enable it in board Kconfig if it uses i.MX6 variant Engicam boards. diff --git a/board/engicam/common/Makefile b/board/engicam/common/Makefile index b392bf6cb1..15f0eaa1ec 100644 --- a/board/engicam/common/Makefile +++ b/board/engicam/common/Makefile @@ -1,5 +1,8 @@ # SPDX-License-Identifier: GPL-2.0+ # Copyright (C) 2016 Amarula Solutions B.V. -obj-y := board.o -obj-$(CONFIG_SPL_BUILD) += spl.o +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_IMX6_ENGICAM_COMMON) += spl.o +else +obj-$(CONFIG_IMX6_ENGICAM_COMMON) += board.o +endif diff --git a/board/engicam/imx6q/Kconfig b/board/engicam/imx6q/Kconfig index 48eb60c09a..fab8da0e73 100644 --- a/board/engicam/imx6q/Kconfig +++ b/board/engicam/imx6q/Kconfig @@ -9,4 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx6-engicam" +source "board/engicam/common/Kconfig" + endif diff --git a/board/engicam/imx6ul/Kconfig b/board/engicam/imx6ul/Kconfig index e91dd15970..58f25d0623 100644 --- a/board/engicam/imx6ul/Kconfig +++ b/board/engicam/imx6ul/Kconfig @@ -9,4 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx6-engicam" +source "board/engicam/common/Kconfig" + endif From 39c8b2c72a53329bf691f60b8a774a6939d27706 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 28 Oct 2020 19:03:45 +0530 Subject: [PATCH 16/19] rockchip: Add Engicam PX30.Core EDIMM2.2 Starter Kit PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board from Engicam. PX30.Core needs to mount on top of this Evaluation board for creating complete PX30.Core EDIMM2.2 Starter Kit. Add support for it. Signed-off-by: Jagan Teki Signed-off-by: Suniel Mahesh Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 1 + arch/arm/dts/px30-px30-core-edimm2.2.dts | 21 +++++ arch/arm/mach-rockchip/px30/Kconfig | 10 ++ board/engicam/px30_core/Kconfig | 16 ++++ board/engicam/px30_core/MAINTAINERS | 7 ++ board/engicam/px30_core/Makefile | 7 ++ board/engicam/px30_core/px30_core.c | 4 + configs/px30-core-edimm2.2-px30_defconfig | 108 ++++++++++++++++++++++ include/configs/px30_core.h | 15 +++ 9 files changed, 189 insertions(+) create mode 100644 arch/arm/dts/px30-px30-core-edimm2.2.dts create mode 100644 board/engicam/px30_core/Kconfig create mode 100644 board/engicam/px30_core/MAINTAINERS create mode 100644 board/engicam/px30_core/Makefile create mode 100644 board/engicam/px30_core/px30_core.c create mode 100644 configs/px30-core-edimm2.2-px30_defconfig create mode 100644 include/configs/px30_core.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 72b6fe1a3e..aa5dba94cb 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -72,6 +72,7 @@ dtb-$(CONFIG_MACH_S700) += \ dtb-$(CONFIG_ROCKCHIP_PX30) += \ px30-evb.dtb \ px30-firefly.dtb \ + px30-px30-core-edimm2.2.dtb \ rk3326-odroid-go2.dtb dtb-$(CONFIG_ROCKCHIP_RK3036) += \ diff --git a/arch/arm/dts/px30-px30-core-edimm2.2.dts b/arch/arm/dts/px30-px30-core-edimm2.2.dts new file mode 100644 index 0000000000..c36280ce7f --- /dev/null +++ b/arch/arm/dts/px30-px30-core-edimm2.2.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/dts-v1/; +#include "px30.dtsi" +#include "px30-engicam-edimm2.2.dtsi" +#include "px30-px30-core.dtsi" + +/ { + model = "Engicam PX30.Core EDIMM2.2 Starter Kit"; + compatible = "engicam,px30-core-edimm2.2", "engicam,px30-px30-core", + "rockchip,px30"; + + chosen { + stdout-path = "serial2:115200n8"; + }; +}; diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 6cd65dfa97..5d014f6561 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -11,6 +11,15 @@ config TARGET_EVB_PX30 config TARGET_ODROID_GO2 bool "ODROID_GO2" +config TARGET_PX30_CORE + bool "Engicam PX30.Core" + help + PX30.Core EDIMM2.2: + * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. + * EDIMM2.2 is a Form Factor Capacitive Evaluation Board from Engicam. + * PX30.Core needs to mount on top of EDIMM2.2 for creating complete + PX30.Core EDIMM2.2 Starter Kit. + config ROCKCHIP_BOOT_MODE_REG default 0xff010200 @@ -44,6 +53,7 @@ config DEBUG_UART_CHANNEL For using the UART for early debugging the route to use needs to be declared (0 or 1). +source "board/engicam/px30_core/Kconfig" source "board/hardkernel/odroid_go2/Kconfig" source "board/rockchip/evb_px30/Kconfig" diff --git a/board/engicam/px30_core/Kconfig b/board/engicam/px30_core/Kconfig new file mode 100644 index 0000000000..a03be78369 --- /dev/null +++ b/board/engicam/px30_core/Kconfig @@ -0,0 +1,16 @@ +if TARGET_PX30_CORE + +config SYS_BOARD + default "px30_core" + +config SYS_VENDOR + default "engicam" + +config SYS_CONFIG_NAME + default "px30_core" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select RAM_PX30_DDR4 + +endif diff --git a/board/engicam/px30_core/MAINTAINERS b/board/engicam/px30_core/MAINTAINERS new file mode 100644 index 0000000000..f98a84450a --- /dev/null +++ b/board/engicam/px30_core/MAINTAINERS @@ -0,0 +1,7 @@ +PX30-Core-EDIMM2.2 +M: Jagan Teki +M: Suniel Mahesh +S: Maintained +F: board/engicam/px30_core +F: include/configs/px30_core.h +F: configs/px30-core-edimm2.2-px30_defconfig diff --git a/board/engicam/px30_core/Makefile b/board/engicam/px30_core/Makefile new file mode 100644 index 0000000000..321fdb0173 --- /dev/null +++ b/board/engicam/px30_core/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2020 Amarula Solutions(India) +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += px30_core.o diff --git a/board/engicam/px30_core/px30_core.c b/board/engicam/px30_core/px30_core.c new file mode 100644 index 0000000000..3adc2f11de --- /dev/null +++ b/board/engicam/px30_core/px30_core.c @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2020 Amarula Solutions(India) + */ diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig new file mode 100644 index 0000000000..50a9a150c8 --- /dev/null +++ b/configs/px30-core-edimm2.2-px30_defconfig @@ -0,0 +1,108 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_TEXT_BASE=0x00000000 +CONFIG_ROCKCHIP_PX30=y +CONFIG_TARGET_PX30_CORE=y +CONFIG_DEBUG_UART_CHANNEL=1 +CONFIG_TPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_DEBUG_UART_BASE=0xFF160000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-edimm2.2" +CONFIG_DEBUG_UART=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_CONSOLE_MUX is not set +CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-edimm2.2.dtb" +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +# CONFIG_TPL_BANNER_PRINT is not set +CONFIG_SPL_CRC32_SUPPORT=y +CONFIG_SPL_ATF=y +# CONFIG_TPL_FRAMEWORK is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_GPT=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_BUF_SIZE=0x04000000 +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_OTP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_ROCKCHIP_SDRAM_COMMON=y +CONFIG_DM_RESET=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +# CONFIG_SPECIFY_CONSOLE_INDEX is not set +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SOUND=y +CONFIG_SYSRESET=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_LCD=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_LZO=y +CONFIG_ERRNO_STR=y diff --git a/include/configs/px30_core.h b/include/configs/px30_core.h new file mode 100644 index 0000000000..01b4995598 --- /dev/null +++ b/include/configs/px30_core.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2020 Amarula Solutions(India) + */ + +#ifndef __PX30_CORE_H +#define __PX30_CORE_H + +#include + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#endif /* __PX30_CORE_H */ From d432975cec39b856fe910371c78f4f25b6fa8b33 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 28 Oct 2020 19:03:46 +0530 Subject: [PATCH 17/19] arm64: dts: rockchip: px30: Add Engicam C.TOUCH 2.0 Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose carrier board with capacitive touch interface. Genaral features: - TFT 10.1" industrial, 1280x800 LVDS display - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN - LVDS panel connector SOM's like PX30.Core needs to mount on top of this Carrier board for creating complete PX30.Core C.TOUCH 2.0 board. Add support for it. Signed-off-by: Jagan Teki Signed-off-by: Michael Trimarchi Reviewed-by: Kever Yang --- arch/arm/dts/px30-engicam-ctouch2.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 arch/arm/dts/px30-engicam-ctouch2.dtsi diff --git a/arch/arm/dts/px30-engicam-ctouch2.dtsi b/arch/arm/dts/px30-engicam-ctouch2.dtsi new file mode 100644 index 0000000000..58425b1e55 --- /dev/null +++ b/arch/arm/dts/px30-engicam-ctouch2.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions + * Copyright (c) 2020 Amarula Solutions(India) + */ + +#include "px30-engicam-common.dtsi" From 51656ae1d130975d8acfa47308b5b9edee15924f Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 28 Oct 2020 19:03:47 +0530 Subject: [PATCH 18/19] rockchip: Add Engicam PX30.Core C.TOUCH 2.0 PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. C.TOUCH 2.0 is a general purpose carrier board with capacitive touch interface support. PX30.Core needs to mount on top of this Carrier board for creating complete PX30.Core C.TOUCH 2.0 board. Add support for it. Signed-off-by: Jagan Teki Signed-off-by: Suniel Mahesh Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 1 + arch/arm/dts/px30-px30-core-ctouch2.dts | 22 +++++ arch/arm/mach-rockchip/px30/Kconfig | 7 ++ board/engicam/px30_core/MAINTAINERS | 6 ++ configs/px30-core-ctouch2-px30_defconfig | 108 +++++++++++++++++++++++ 5 files changed, 144 insertions(+) create mode 100644 arch/arm/dts/px30-px30-core-ctouch2.dts create mode 100644 configs/px30-core-ctouch2-px30_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index aa5dba94cb..dafe9485e0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -72,6 +72,7 @@ dtb-$(CONFIG_MACH_S700) += \ dtb-$(CONFIG_ROCKCHIP_PX30) += \ px30-evb.dtb \ px30-firefly.dtb \ + px30-px30-core-ctouch2.dtb \ px30-px30-core-edimm2.2.dtb \ rk3326-odroid-go2.dtb diff --git a/arch/arm/dts/px30-px30-core-ctouch2.dts b/arch/arm/dts/px30-px30-core-ctouch2.dts new file mode 100644 index 0000000000..2da0128188 --- /dev/null +++ b/arch/arm/dts/px30-px30-core-ctouch2.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/dts-v1/; +#include "px30.dtsi" +#include "px30-engicam-ctouch2.dtsi" +#include "px30-px30-core.dtsi" + +/ { + model = "Engicam PX30.Core C.TOUCH 2.0"; + compatible = "engicam,px30-core-ctouch2", "engicam,px30-px30-core", + "rockchip,px30"; + + chosen { + stdout-path = "serial2:115200n8"; + }; +}; diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 5d014f6561..16090f5b08 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -20,6 +20,13 @@ config TARGET_PX30_CORE * PX30.Core needs to mount on top of EDIMM2.2 for creating complete PX30.Core EDIMM2.2 Starter Kit. + PX30.Core CTOUCH2: + * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. + * CTOUCH2.0 is a general purpose Carrier board with capacitive + touch interface support. + * PX30.Core needs to mount on top of CTOUCH2.0 for creating complete + PX30.Core C.TOUCH Carrier board. + config ROCKCHIP_BOOT_MODE_REG default 0xff010200 diff --git a/board/engicam/px30_core/MAINTAINERS b/board/engicam/px30_core/MAINTAINERS index f98a84450a..b87ca22207 100644 --- a/board/engicam/px30_core/MAINTAINERS +++ b/board/engicam/px30_core/MAINTAINERS @@ -1,3 +1,9 @@ +PX30-Core-CTOUCH2.0 +M: Jagan Teki +M: Suniel Mahesh +S: Maintained +F: configs/px30-core-ctouch2-px30_defconfig + PX30-Core-EDIMM2.2 M: Jagan Teki M: Suniel Mahesh diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig new file mode 100644 index 0000000000..d64f05d8c0 --- /dev/null +++ b/configs/px30-core-ctouch2-px30_defconfig @@ -0,0 +1,108 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_TEXT_BASE=0x00000000 +CONFIG_ROCKCHIP_PX30=y +CONFIG_TARGET_PX30_CORE=y +CONFIG_DEBUG_UART_CHANNEL=1 +CONFIG_TPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_DEBUG_UART_BASE=0xFF160000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-ctouch2" +CONFIG_DEBUG_UART=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_CONSOLE_MUX is not set +CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-ctouch2.dtb" +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +# CONFIG_TPL_BANNER_PRINT is not set +CONFIG_SPL_CRC32_SUPPORT=y +CONFIG_SPL_ATF=y +# CONFIG_TPL_FRAMEWORK is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_GPT=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_BUF_SIZE=0x04000000 +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_OTP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_ROCKCHIP_SDRAM_COMMON=y +CONFIG_DM_RESET=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +# CONFIG_SPECIFY_CONSOLE_INDEX is not set +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SOUND=y +CONFIG_SYSRESET=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_LCD=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_LZO=y +CONFIG_ERRNO_STR=y From 43ed7a098d62e700ac024ab913f3be17a6974bb2 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 28 Oct 2020 19:03:48 +0530 Subject: [PATCH 19/19] doc: rockchip: Document Rockchip miniloader flashing This would be useful and recommended boot flow for new boards which has doesn't have the DDR support yet in mainline. Sometimes it is very useful for debugging mainline DDR support. Documen it for px30 boot flow. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- doc/board/rockchip/rockchip.rst | 40 ++++++++++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 8c92de0c92..955e6858f2 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -123,6 +123,9 @@ To build rk3399 boards:: Flashing -------- +1. Package the image with U-Boot TPL/SPL +----------------------------------------- + SD Card ^^^^^^^ @@ -187,6 +190,39 @@ Copy SPI boot images into SD card and boot from SD:: sf erase 0x60000 +$filesize sf write $kernel_addr_r 0x60000 ${filesize} +2. Package the image with Rockchip miniloader +--------------------------------------------- + +Image package with Rockchip miniloader requires robin [1]. + +Create idbloader.img + +.. code-block:: none + + cd u-boot + ./tools/mkimage -n px30 -T rksd -d rkbin/bin/rk33/px30_ddr_333MHz_v1.15.bin idbloader.img + cat rkbin/bin/rk33/px30_miniloader_v1.22.bin >> idbloader.img + sudo dd if=idbloader.img of=/dev/sda seek=64 + +Create trust.img + +.. code-block:: none + + cd rkbin + ./tools/trust_merger RKTRUST/PX30TRUST.ini + sudo dd if=trust.img of=/dev/sda seek=24576 + +Create uboot.img + +.. code-block:: none + + rbink/tools/loaderimage --pack --uboot u-boot-dtb.bin uboot.img 0x200000 + sudo dd if=uboot.img of=/dev/sda seek=16384 + +Note: +1. 0x200000 is load address and it's an optional in some platforms. +2. rkbin binaries are kept on updating, so would recommend to use the latest versions. + TODO ---- @@ -195,5 +231,7 @@ TODO - Document SPI flash boot - Add missing SoC's with it boards list +[1] https://github.com/rockchip-linux/rkbin + .. Jagan Teki -.. Tuesday 02 June 2020 12:18:57 AM IST +.. Wednesday 28 October 2020 06:47:26 PM IST