mirror of
https://github.com/Fishwaldo/u-boot.git
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arm: dts: k3: Sync dts from Linux
Sync the k3-am654 specific dts files from Linux next with tag 20181019. This changes are in queue for Linux v4.20-rc1 Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla
Tom Rini
parent
9dba883a45
commit
2d0eba3a45
5 changed files with 171 additions and 92 deletions
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@ -8,13 +8,13 @@
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&cbass_main {
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gic500: interrupt-controller@1800000 {
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compatible = "arm,gic-v3";
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#address-cells = <1>;
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#size-cells = <1>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x01800000 0x10000>, /* GICD */
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<0x01880000 0x90000>; /* GICR */
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reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
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<0x00 0x01880000 0x00 0x90000>; /* GICR */
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/*
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* vcpumntirq:
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* virtual CPU interface maintenance interrupt
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@ -23,9 +23,50 @@
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gic_its: gic-its@18200000 {
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compatible = "arm,gic-v3-its";
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reg = <0x01820000 0x10000>;
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reg = <0x00 0x01820000 0x00 0x10000>;
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msi-controller;
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#msi-cells = <1>;
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};
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};
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secure_proxy_main: mailbox@32c00000 {
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compatible = "ti,am654-secure-proxy";
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#mbox-cells = <1>;
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reg-names = "target_data", "rt", "scfg";
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reg = <0x00 0x32c00000 0x00 0x100000>,
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<0x00 0x32400000 0x00 0x100000>,
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<0x00 0x32800000 0x00 0x100000>;
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interrupt-names = "rx_011";
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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};
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main_uart0: serial@2800000 {
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compatible = "ti,am654-uart";
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reg = <0x00 0x02800000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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};
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main_uart1: serial@2810000 {
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compatible = "ti,am654-uart";
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reg = <0x00 0x02810000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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};
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main_uart2: serial@2820000 {
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compatible = "ti,am654-uart";
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reg = <0x00 0x02820000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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};
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};
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18
arch/arm/dts/k3-am65-mcu.dtsi
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18
arch/arm/dts/k3-am65-mcu.dtsi
Normal file
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@ -0,0 +1,18 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for AM6 SoC Family MCU Domain peripherals
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*
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
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*/
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&cbass_mcu {
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mcu_uart0: serial@40a00000 {
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compatible = "ti,am654-uart";
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reg = <0x00 0x40a00000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <96000000>;
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current-speed = <115200>;
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};
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};
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46
arch/arm/dts/k3-am65-wakeup.dtsi
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46
arch/arm/dts/k3-am65-wakeup.dtsi
Normal file
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@ -0,0 +1,46 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for AM6 SoC Family Wakeup Domain peripherals
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*
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
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*/
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&cbass_wakeup {
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dmsc: dmsc {
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compatible = "ti,k2g-sci";
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ti,host-id = <12>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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mbox-names = "rx", "tx";
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mboxes= <&secure_proxy_main 11>,
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<&secure_proxy_main 13>;
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k3_pds: power-controller {
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compatible = "ti,sci-pm-domain";
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#power-domain-cells = <1>;
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};
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k3_clks: clocks {
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compatible = "ti,k2g-sci-clk";
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#clock-cells = <2>;
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};
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k3_reset: reset-controller {
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compatible = "ti,sci-reset";
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#reset-cells = <2>;
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};
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};
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wkup_uart0: serial@42300000 {
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compatible = "ti,am654-uart";
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reg = <0x42300000 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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};
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};
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@ -16,6 +16,14 @@
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &wkup_uart0;
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serial1 = &mcu_uart0;
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serial2 = &main_uart0;
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serial3 = &main_uart1;
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serial4 = &main_uart2;
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};
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chosen { };
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firmware {
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@ -46,38 +54,38 @@
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cbass_main: interconnect@100000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00100000 0x00 0x00100000 0x00020000>, /* ctrl mmr */
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<0x00600000 0x00 0x00600000 0x00001100>, /* GPIO */
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<0x00900000 0x00 0x00900000 0x00012000>, /* serdes */
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<0x01000000 0x00 0x01000000 0x0af02400>, /* Most peripherals */
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<0x30800000 0x00 0x30800000 0x0bc00000>, /* MAIN NAVSS */
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
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<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
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<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
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<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
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<0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
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/* MCUSS Range */
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<0x28380000 0x00 0x28380000 0x03880000>,
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<0x40200000 0x00 0x40200000 0x00900100>,
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<0x42040000 0x00 0x42040000 0x03ac2400>,
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<0x45100000 0x00 0x45100000 0x00c24000>,
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<0x46000000 0x00 0x46000000 0x00200000>,
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<0x47000000 0x00 0x47000000 0x00068400>;
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<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
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<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
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<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
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<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
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<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
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<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>;
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cbass_mcu: interconnect@28380000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x28380000 0x28380000 0x03880000>, /* MCU NAVSS*/
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<0x40200000 0x40200000 0x00900100>, /* First peripheral window */
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<0x42040000 0x42040000 0x03ac2400>, /* WKUP */
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<0x45100000 0x45100000 0x00c24000>, /* MMRs, remaining NAVSS */
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<0x46000000 0x46000000 0x00200000>, /* CPSW */
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<0x47000000 0x47000000 0x00068400>; /* OSPI space 1 */
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
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<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
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<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
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<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
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<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
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<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; /* OSPI space 1 */
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cbass_wakeup: interconnect@42040000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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/* WKUP Basic peripherals */
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ranges = <0x42040000 0x42040000 0x03ac2400>;
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ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;
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};
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};
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};
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@ -85,3 +93,5 @@
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/* Now include the peripherals for each bus segments */
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#include "k3-am65-main.dtsi"
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#include "k3-am65-mcu.dtsi"
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#include "k3-am65-wakeup.dtsi"
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@ -17,56 +17,10 @@
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&cbass_main{
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u-boot,dm-spl;
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secure_proxy: secure_proxy@32c00000 {
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compatible = "ti,am654-secure-proxy";
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#mbox-cells = <1>;
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reg-names = "target_data", "rt", "scfg";
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reg = <0x32c00000 0x100000>,
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<0x32400000 0x100000>,
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<0x32800000 0x100000>;
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interrupt-names = "rx_011";
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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};
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dmsc: dmsc {
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compatible = "ti,k2g-sci";
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ti,host-id = <12>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/*
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* In case of rare platforms that does not use am6 as
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* system master, use /delete-property/
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*/
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ti,system-reboot-controller;
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mbox-names = "rx", "tx";
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mboxes= <&secure_proxy 11>,
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<&secure_proxy 13>;
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k3_pds: power-controller {
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compatible = "ti,sci-pm-domain";
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#power-domain-cells = <1>;
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};
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k3_clks: clocks {
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compatible = "ti,k2g-sci-clk";
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#clock-cells = <2>;
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};
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k3_reset: reset-controller {
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compatible = "ti,sci-reset";
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#reset-cells = <2>;
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};
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k3_sysreset: sysreset-controller {
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compatible = "ti,sci-sysreset";
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};
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};
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main_pmx0: pinmux@11c000 {
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compatible = "pinctrl-single";
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reg = <0x11c000 0x2e4>;
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reg = <0x0 0x11c000 0x0 0x2e4>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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@ -74,28 +28,16 @@
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main_pmx1: pinmux@11c2e8 {
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compatible = "pinctrl-single";
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reg = <0x11c2e8 0x24>;
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reg = <0x0 0x11c2e8 0x0 0x24>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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main_uart0: serial@2800000 {
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compatible = "ti,am654-uart", "ti,omap4-uart", "ns16550a";
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reg = <0x02800000 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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status = "disabled";
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u-boot,dm-pre-reloc;
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};
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sdhci0: sdhci@04F80000 {
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compatible = "arasan,sdhci-5.1";
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reg = <0x4F80000 0x1000>,
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<0x4F90000 0x400>;
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reg = <0x0 0x4F80000 0x0 0x1000>,
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<0x0 0x4F90000 0x0 0x400>;
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clocks = <&k3_clks 47 1>;
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power-domains = <&k3_pds 47>;
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max-frequency = <25000000>;
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@ -103,8 +45,8 @@
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sdhci1: sdhci@04FA0000 {
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compatible = "arasan,sdhci-5.1";
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reg = <0x4FA0000 0x1000>,
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<0x4FB0000 0x400>;
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reg = <0x0 0x4FA0000 0x0 0x1000>,
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<0x0 0x4FB0000 0x0 0x400>;
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clocks = <&k3_clks 48 1>;
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power-domains = <&k3_pds 48>;
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max-frequency = <25000000>;
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@ -112,12 +54,31 @@
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};
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&secure_proxy {
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&cbass_mcu {
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u-boot,dm-spl;
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wkup_pmx0: pinmux@4301c000 {
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compatible = "pinctrl-single";
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reg = <0x0 0x4301c000 0x0 0x118>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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};
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&cbass_wakeup {
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u-boot,dm-spl;
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};
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&secure_proxy_main {
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u-boot,dm-spl;
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};
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&dmsc {
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u-boot,dm-spl;
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k3_sysreset: sysreset-controller {
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compatible = "ti,sci-sysreset";
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u-boot,dm-spl;
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};
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};
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&k3_pds {
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@ -141,6 +102,7 @@
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AM65X_IOPAD(0x01ec, PIN_INPUT | MUX_MODE0) /* (AG11) UART0_CTSn */
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AM65X_IOPAD(0x01f0, PIN_OUTPUT | MUX_MODE0) /* (AD11) UART0_RTSn */
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>;
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u-boot,dm-spl;
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};
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main_mmc0_pins_default: main_mmc0_pins_default {
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@ -157,6 +119,7 @@
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AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP | MUX_MODE0) /* (D25) MMC0_DAT7 */
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AM65X_IOPAD(0x01b0, PIN_INPUT | MUX_MODE0) /* (C25) MMC0_DS */
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>;
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u-boot,dm-spl;
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};
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main_mmc1_pins_default: main_mmc1_pins_default {
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@ -170,6 +133,7 @@
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AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP | MUX_MODE0) /* (B24) MMC1_SDCD */
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AM65X_IOPAD(0x02e0, PIN_INPUT | MUX_MODE0) /* (C24) MMC1_SDWP */
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>;
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u-boot,dm-spl;
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};
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};
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