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serial: pl01x: fix pl011 baud rate configuration

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UART_IBRD, UART_FBRD, and UART_LCR_H form a single 30-bit wide register which
is updated on a single write strobe generated by a UART_LCR_H write. So, to
internally update the content of UART_IBRD or UART_FBRD, a write to UART_LCR_H
must always be performed at the end.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Vikas Manocha 2014-11-21 10:34:20 -08:00 • committed by Tom Rini
parent a7deea691c
commit 2df810717e
1 changed files with 8 additions and 0 deletions
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8
drivers/serial/serial_pl01x.c
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@ -122,6 +122,7 @@ static int pl01x_generic_serial_init(struct pl01x_regs *regs,
static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type, static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
int clock, int baudrate) int clock, int baudrate)
{ {
unsigned int lcr;
switch (type) { switch (type) {
case TYPE_PL010: { case TYPE_PL010: {
unsigned int divisor; unsigned int divisor;
@ -175,6 +176,13 @@ static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
writel(divider, &regs->pl011_ibrd); writel(divider, &regs->pl011_ibrd);
writel(fraction, &regs->pl011_fbrd); writel(fraction, &regs->pl011_fbrd);
/*
* Internal update of baud rate register require line
* control register write
*/
lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
writel(lcr, &regs->pl011_lcrh);
/* Finally, enable the UART */ /* Finally, enable the UART */
writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr); UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr);