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armv8: ls2080a: Implement workaround for core errata 829520, 833471

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829520: Code bounded by indirect conditional branch might corrupt
instruction stream.
Workaround: Set CPUACTLR_EL1[4] = 1'b1 to disable the Indirect
Predictor.

833471: VMSR FPSCR functional failure or deadlock.
Workaround: Set CPUACTLR[38] to 1, which forces FPSCR write flush.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Ashish kumar 2016-01-27 18:09:32 +05:30 • committed by York Sun
parent 73a5de4c6e
commit 2ea3a448cc
2 changed files with 23 additions and 0 deletions
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19
arch/arm/cpu/armv8/start.S
View file

@ -168,6 +168,25 @@ apply_a57_core_errata:
msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
#endif #endif
#ifdef CONFIG_ARM_ERRATA_833471
mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
/* FPSCR write flush.
* Note that in some cases where a flush is unnecessary this
could impact performance. */
orr x0, x0, #1 << 38
msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
#endif
#ifdef CONFIG_ARM_ERRATA_829520
mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
/* Disable Indirect Predictor bit will prevent this erratum
from occurring
* Note that in some cases where a flush is unnecessary this
could impact performance. */
orr x0, x0, #1 << 4
msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
#endif
#ifdef CONFIG_ARM_ERRATA_833069 #ifdef CONFIG_ARM_ERRATA_833069
mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
/* Disable Enable Invalidates of BTB bit */ /* Disable Enable Invalidates of BTB bit */

4
arch/arm/include/asm/arch-fsl-layerscape/config.h
View file

@ -121,6 +121,10 @@
#define CONFIG_SYS_FSL_ERRATUM_A009663 #define CONFIG_SYS_FSL_ERRATUM_A009663
#define CONFIG_SYS_FSL_ERRATUM_A009942 #define CONFIG_SYS_FSL_ERRATUM_A009942
/* ARM A57 CORE ERRATA */
#define CONFIG_ARM_ERRATA_829520
#define CONFIG_ARM_ERRATA_833471
#elif defined(CONFIG_LS1043A) #elif defined(CONFIG_LS1043A)
#define CONFIG_MAX_CPUS 4 #define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_SYS_CACHELINE_SIZE 64