mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-21 06:31:31 +00:00
powerpc: mpc85xx: Use symbolic names for cache control bits
We should use the symbolic names for the cache control bits. Signed-off-by: Mark Marshall <Mark.Marshall@omicron.at> Reviewed-by: Thomas Graziadei <thomas.graziadei@omicronenergy.com> Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
parent
dbcb2c0e2b
commit
2ec70961e7
1 changed files with 4 additions and 4 deletions
|
@ -1373,8 +1373,8 @@ icache_enable:
|
|||
mtlr r8
|
||||
isync
|
||||
mfspr r4,L1CSR1
|
||||
ori r4,r4,0x0001
|
||||
oris r4,r4,0x0001
|
||||
ori r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@l
|
||||
oris r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@h
|
||||
mtspr L1CSR1,r4
|
||||
isync
|
||||
blr
|
||||
|
@ -1402,8 +1402,8 @@ dcache_enable:
|
|||
mtlr r8
|
||||
isync
|
||||
mfspr r0,L1CSR0
|
||||
ori r0,r0,0x0001
|
||||
oris r0,r0,0x0001
|
||||
ori r0,r0,(L1CSR0_CPE | L1CSR0_DCE)@l
|
||||
oris r0,r0,(L1CSR0_CPE | L1CSR0_DCE)@h
|
||||
msync
|
||||
isync
|
||||
mtspr L1CSR0,r0
|
||||
|
|
Loading…
Add table
Reference in a new issue