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clk: meson: fix clk81 divider calculation
clk81 divider is 0 based (meaning that 0 value in the register means divide by 1). Fix clk81 rate calculation for this. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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1 changed files with 2 additions and 1 deletions
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@ -600,7 +600,8 @@ static unsigned long meson_clk81_get_rate(struct clk *clk)
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reg = readl(priv->addr + HHI_MPEG_CLK_CNTL);
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reg = reg & ((1 << 7) - 1);
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return parent_rate / reg;
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/* clk81 divider is zero based */
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return parent_rate / (reg + 1);
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}
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static long mpll_rate_from_params(unsigned long parent_rate,
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