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ARM: I2C: I2C Multi byte address support
Existing OMAP I2C driver does not support address length greater than one. Hence this patch is to add support for 2 byte address read/write. Signed-off-by: Philip, Avinash <avinashphilip@ti.com> Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com> Signed-off-by: Patil, Rachna <rachna@ti.com>
This commit is contained in:
Patil, Rachna
Heiko Schocher
parent
137703b811
commit
2faa76196a
2 changed files with 301 additions and 178 deletions
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@ -29,10 +29,11 @@
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DECLARE_GLOBAL_DATA_PTR;
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#define I2C_TIMEOUT 1000
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#define I2C_STAT_TIMEO (1 << 31)
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#define I2C_TIMEOUT 10
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static void wait_for_bb(void);
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static u16 wait_for_pin(void);
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static u32 wait_for_bb(void);
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static u32 wait_for_status_mask(u16 mask);
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static void flush_fifo(void);
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/*
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@ -50,7 +51,6 @@ void i2c_init(int speed, int slaveadd)
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int psc, fsscll, fssclh;
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int hsscll = 0, hssclh = 0;
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u32 scll, sclh;
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int timeout = I2C_TIMEOUT;
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/* Only handle standard, fast and high speeds */
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if ((speed != OMAP_I2C_STANDARD) &&
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@ -112,24 +112,14 @@ void i2c_init(int speed, int slaveadd)
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sclh = (unsigned int)fssclh;
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}
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if (gd->flags & GD_FLG_RELOC)
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bus_initialized[current_bus] = 1;
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if (readw(&i2c_base->con) & I2C_CON_EN) {
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writew(0, &i2c_base->con);
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udelay(50000);
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}
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writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
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udelay(1000);
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writew(I2C_CON_EN, &i2c_base->con);
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while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
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if (timeout <= 0) {
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puts("ERROR: Timeout in soft-reset\n");
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return;
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}
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udelay(1000);
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}
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writew(0, &i2c_base->con);
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writew(psc, &i2c_base->psc);
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writew(scll, &i2c_base->scll);
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writew(sclh, &i2c_base->sclh);
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@ -145,81 +135,6 @@ void i2c_init(int speed, int slaveadd)
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flush_fifo();
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writew(0xFFFF, &i2c_base->stat);
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writew(0, &i2c_base->cnt);
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if (gd->flags & GD_FLG_RELOC)
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bus_initialized[current_bus] = 1;
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}
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static int i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value)
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{
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int i2c_error = 0;
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u16 status;
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/* wait until bus not busy */
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wait_for_bb();
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/* one byte only */
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writew(1, &i2c_base->cnt);
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/* set slave address */
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writew(devaddr, &i2c_base->sa);
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/* no stop bit needed here */
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writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
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I2C_CON_TRX, &i2c_base->con);
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/* send register offset */
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while (1) {
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status = wait_for_pin();
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if (status == 0 || status & I2C_STAT_NACK) {
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i2c_error = 1;
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goto read_exit;
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}
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if (status & I2C_STAT_XRDY) {
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/* Important: have to use byte access */
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writeb(regoffset, &i2c_base->data);
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writew(I2C_STAT_XRDY, &i2c_base->stat);
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}
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if (status & I2C_STAT_ARDY) {
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writew(I2C_STAT_ARDY, &i2c_base->stat);
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break;
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}
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}
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/* set slave address */
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writew(devaddr, &i2c_base->sa);
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/* read one byte from slave */
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writew(1, &i2c_base->cnt);
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/* need stop bit here */
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writew(I2C_CON_EN | I2C_CON_MST |
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I2C_CON_STT | I2C_CON_STP,
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&i2c_base->con);
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/* receive data */
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while (1) {
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status = wait_for_pin();
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if (status == 0 || status & I2C_STAT_NACK) {
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i2c_error = 1;
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goto read_exit;
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}
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if (status & I2C_STAT_RRDY) {
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#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
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defined(CONFIG_OMAP44XX)
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*value = readb(&i2c_base->data);
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#else
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*value = readw(&i2c_base->data);
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#endif
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writew(I2C_STAT_RRDY, &i2c_base->stat);
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}
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if (status & I2C_STAT_ARDY) {
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writew(I2C_STAT_ARDY, &i2c_base->stat);
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break;
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}
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}
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read_exit:
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flush_fifo();
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writew(0xFFFF, &i2c_base->stat);
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writew(0, &i2c_base->cnt);
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return i2c_error;
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}
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static void flush_fifo(void)
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@ -246,32 +161,42 @@ static void flush_fifo(void)
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int i2c_probe(uchar chip)
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{
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u16 status;
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u32 status;
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int res = 1; /* default = fail */
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if (chip == readw(&i2c_base->oa))
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return res;
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/* wait until bus not busy */
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wait_for_bb();
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status = wait_for_bb();
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/* exit on BUS busy */
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if (status & I2C_STAT_TIMEO)
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return res;
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/* try to write one byte */
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writew(1, &i2c_base->cnt);
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/* set slave address */
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writew(chip, &i2c_base->sa);
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/* stop bit needed here */
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writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
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I2C_CON_STP, &i2c_base->con);
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status = wait_for_pin();
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/* check for ACK (!NAK) */
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if (!(status & I2C_STAT_NACK))
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res = 0;
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/* abort transfer (force idle state) */
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writew(0, &i2c_base->con);
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writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT
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| I2C_CON_STP, &i2c_base->con);
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/* enough delay for the NACK bit set */
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udelay(9000);
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if (!(readw(&i2c_base->stat) & I2C_STAT_NACK)) {
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res = 0; /* success case */
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flush_fifo();
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writew(0xFFFF, &i2c_base->stat);
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} else {
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/* failure, clear sources*/
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writew(0xFFFF, &i2c_base->stat);
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/* finish up xfer */
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writew(readw(&i2c_base->con) | I2C_CON_STP, &i2c_base->con);
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status = wait_for_bb();
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/* exit on BUS busy */
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if (status & I2C_STAT_TIMEO)
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return res;
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}
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flush_fifo();
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/* don't allow any more data in... we don't want it. */
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writew(0, &i2c_base->cnt);
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@ -281,111 +206,309 @@ int i2c_probe(uchar chip)
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int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
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{
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int i;
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int i2c_error = 0, i;
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u32 status;
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if (alen > 1) {
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printf("I2C read: addr len %d not supported\n", alen);
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if ((alen > 2) || (alen < 0))
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return 1;
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}
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if (addr + len > 256) {
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puts("I2C read: address out of range\n");
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return 1;
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}
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for (i = 0; i < len; i++) {
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if (i2c_read_byte(chip, addr + i, &buffer[i])) {
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puts("I2C read: I/O error\n");
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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if (alen < 2) {
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if (addr + len > 256)
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return 1;
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} else if (addr + len > 0xFFFF) {
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return 1;
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}
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/* wait until bus not busy */
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status = wait_for_bb();
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/* exit on BUS busy */
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if (status & I2C_STAT_TIMEO)
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return 1;
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writew((alen & 0xFF), &i2c_base->cnt);
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/* set slave address */
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writew(chip, &i2c_base->sa);
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/* Clear the Tx & Rx FIFOs */
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writew((readw(&i2c_base->buf) | I2C_RXFIFO_CLEAR |
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I2C_TXFIFO_CLEAR), &i2c_base->buf);
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/* no stop bit needed here */
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writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX |
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I2C_CON_STT, &i2c_base->con);
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/* wait for Transmit ready condition */
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status = wait_for_status_mask(I2C_STAT_XRDY | I2C_STAT_NACK);
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if (status & (I2C_STAT_NACK | I2C_STAT_TIMEO))
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i2c_error = 1;
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if (!i2c_error) {
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if (status & I2C_STAT_XRDY) {
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switch (alen) {
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case 2:
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/* Send address MSByte */
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#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
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writew(((addr >> 8) & 0xFF), &i2c_base->data);
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/* Clearing XRDY event */
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writew((status & I2C_STAT_XRDY),
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&i2c_base->stat);
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/* wait for Transmit ready condition */
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status = wait_for_status_mask(I2C_STAT_XRDY |
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I2C_STAT_NACK);
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if (status & (I2C_STAT_NACK |
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I2C_STAT_TIMEO)) {
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i2c_error = 1;
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break;
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}
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#endif
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case 1:
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#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
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/* Send address LSByte */
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writew((addr & 0xFF), &i2c_base->data);
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#else
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/* Send address Short word */
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writew((addr & 0xFFFF), &i2c_base->data);
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#endif
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/* Clearing XRDY event */
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writew((status & I2C_STAT_XRDY),
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&i2c_base->stat);
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/*wait for Transmit ready condition */
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status = wait_for_status_mask(I2C_STAT_ARDY |
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I2C_STAT_NACK);
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if (status & (I2C_STAT_NACK |
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I2C_STAT_TIMEO)) {
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i2c_error = 1;
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break;
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}
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}
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} else
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i2c_error = 1;
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}
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/* Wait for ARDY to set */
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status = wait_for_status_mask(I2C_STAT_ARDY | I2C_STAT_NACK
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| I2C_STAT_AL);
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if (!i2c_error) {
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/* set slave address */
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writew(chip, &i2c_base->sa);
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writew((len & 0xFF), &i2c_base->cnt);
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/* Clear the Tx & Rx FIFOs */
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writew((readw(&i2c_base->buf) | I2C_RXFIFO_CLEAR |
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I2C_TXFIFO_CLEAR), &i2c_base->buf);
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/* need stop bit here */
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writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP,
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&i2c_base->con);
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for (i = 0; i < len; i++) {
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/* wait for Receive condition */
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status = wait_for_status_mask(I2C_STAT_RRDY |
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I2C_STAT_NACK);
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if (status & (I2C_STAT_NACK | I2C_STAT_TIMEO)) {
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i2c_error = 1;
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break;
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}
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if (status & I2C_STAT_RRDY) {
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#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
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buffer[i] = readb(&i2c_base->data);
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#else
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*((u16 *)&buffer[i]) =
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readw(&i2c_base->data) & 0xFFFF;
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i++;
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#endif
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writew((status & I2C_STAT_RRDY),
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&i2c_base->stat);
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udelay(1000);
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} else {
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i2c_error = 1;
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}
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}
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}
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/* Wait for ARDY to set */
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status = wait_for_status_mask(I2C_STAT_ARDY | I2C_STAT_NACK
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| I2C_STAT_AL);
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if (i2c_error) {
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writew(0, &i2c_base->con);
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return 1;
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}
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writew(I2C_CON_EN, &i2c_base->con);
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while (readw(&i2c_base->stat)
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|| (readw(&i2c_base->con) & I2C_CON_MST)) {
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udelay(10000);
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writew(0xFFFF, &i2c_base->stat);
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}
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writew(I2C_CON_EN, &i2c_base->con);
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flush_fifo();
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writew(0xFFFF, &i2c_base->stat);
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writew(0, &i2c_base->cnt);
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return 0;
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}
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int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
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{
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int i;
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u16 status;
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int i2c_error = 0;
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if (alen > 1) {
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printf("I2C write: addr len %d not supported\n", alen);
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int i, i2c_error = 0;
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u32 status;
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u16 writelen;
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if (alen > 2)
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return 1;
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}
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if (addr + len > 256) {
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printf("I2C write: address 0x%x + 0x%x out of range\n",
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addr, len);
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if (alen < 2) {
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if (addr + len > 256)
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return 1;
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} else if (addr + len > 0xFFFF) {
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return 1;
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}
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/* wait until bus not busy */
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wait_for_bb();
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status = wait_for_bb();
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/* start address phase - will write regoffset + len bytes data */
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/* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */
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writew(alen + len, &i2c_base->cnt);
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/* exiting on BUS busy */
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if (status & I2C_STAT_TIMEO)
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return 1;
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writelen = (len & 0xFFFF) + alen;
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/* two bytes */
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writew((writelen & 0xFFFF), &i2c_base->cnt);
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/* Clear the Tx & Rx FIFOs */
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writew((readw(&i2c_base->buf) | I2C_RXFIFO_CLEAR |
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I2C_TXFIFO_CLEAR), &i2c_base->buf);
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/* set slave address */
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writew(chip, &i2c_base->sa);
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/* stop bit needed here */
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writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
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I2C_CON_STP, &i2c_base->con);
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/* Send address byte */
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status = wait_for_pin();
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/* wait for Transmit ready condition */
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status = wait_for_status_mask(I2C_STAT_XRDY | I2C_STAT_NACK);
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if (status == 0 || status & I2C_STAT_NACK) {
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if (status & (I2C_STAT_NACK | I2C_STAT_TIMEO))
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i2c_error = 1;
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printf("error waiting for i2c address ACK (status=0x%x)\n",
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status);
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goto write_exit;
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}
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if (status & I2C_STAT_XRDY) {
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writeb(addr & 0xFF, &i2c_base->data);
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writew(I2C_STAT_XRDY, &i2c_base->stat);
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} else {
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i2c_error = 1;
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printf("i2c bus not ready for transmit (status=0x%x)\n",
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status);
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goto write_exit;
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}
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/* address phase is over, now write data */
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for (i = 0; i < len; i++) {
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status = wait_for_pin();
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if (status == 0 || status & I2C_STAT_NACK) {
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i2c_error = 1;
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printf("i2c error waiting for data ACK (status=0x%x)\n",
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status);
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goto write_exit;
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}
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if (!i2c_error) {
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if (status & I2C_STAT_XRDY) {
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writeb(buffer[i], &i2c_base->data);
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writew(I2C_STAT_XRDY, &i2c_base->stat);
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} else {
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switch (alen) {
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#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
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||||
case 2:
|
||||
/* send out MSB byte */
|
||||
writeb(((addr >> 8) & 0xFF), &i2c_base->data);
|
||||
#else
|
||||
writeb((addr & 0xFFFF), &i2c_base->data);
|
||||
break;
|
||||
#endif
|
||||
/* Clearing XRDY event */
|
||||
writew((status & I2C_STAT_XRDY),
|
||||
&i2c_base->stat);
|
||||
/*waiting for Transmit ready * condition */
|
||||
status = wait_for_status_mask(I2C_STAT_XRDY |
|
||||
I2C_STAT_NACK);
|
||||
|
||||
if (status & (I2C_STAT_NACK | I2C_STAT_TIMEO)) {
|
||||
i2c_error = 1;
|
||||
break;
|
||||
}
|
||||
case 1:
|
||||
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
|
||||
/* send out MSB byte */
|
||||
writeb((addr & 0xFF), &i2c_base->data);
|
||||
#else
|
||||
writew(((buffer[0] << 8) | (addr & 0xFF)),
|
||||
&i2c_base->data);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Clearing XRDY event */
|
||||
writew((status & I2C_STAT_XRDY), &i2c_base->stat);
|
||||
}
|
||||
|
||||
/* waiting for Transmit ready condition */
|
||||
status = wait_for_status_mask(I2C_STAT_XRDY | I2C_STAT_NACK);
|
||||
|
||||
if (status & (I2C_STAT_NACK | I2C_STAT_TIMEO))
|
||||
i2c_error = 1;
|
||||
printf("i2c bus not ready for Tx (i=%d)\n", i);
|
||||
goto write_exit;
|
||||
|
||||
if (!i2c_error) {
|
||||
for (i = ((alen > 1) ? 0 : 1); i < len; i++) {
|
||||
if (status & I2C_STAT_XRDY) {
|
||||
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
|
||||
writeb((buffer[i] & 0xFF),
|
||||
&i2c_base->data);
|
||||
#else
|
||||
writew((((buffer[i] << 8) |
|
||||
buffer[i + 1]) & 0xFFFF),
|
||||
&i2c_base->data);
|
||||
i++;
|
||||
#endif
|
||||
} else
|
||||
i2c_error = 1;
|
||||
/* Clearing XRDY event */
|
||||
writew((status & I2C_STAT_XRDY),
|
||||
&i2c_base->stat);
|
||||
/* waiting for XRDY condition */
|
||||
status = wait_for_status_mask(
|
||||
I2C_STAT_XRDY |
|
||||
I2C_STAT_ARDY |
|
||||
I2C_STAT_NACK);
|
||||
if (status & (I2C_STAT_NACK |
|
||||
I2C_STAT_TIMEO)) {
|
||||
i2c_error = 1;
|
||||
break;
|
||||
}
|
||||
if (status & I2C_STAT_ARDY)
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
status = wait_for_status_mask(I2C_STAT_ARDY | I2C_STAT_NACK |
|
||||
I2C_STAT_AL);
|
||||
|
||||
if (status & (I2C_STAT_NACK | I2C_STAT_TIMEO))
|
||||
i2c_error = 1;
|
||||
|
||||
if (i2c_error) {
|
||||
writew(0, &i2c_base->con);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (!i2c_error) {
|
||||
int eout = 200;
|
||||
|
||||
writew(I2C_CON_EN, &i2c_base->con);
|
||||
while ((status = readw(&i2c_base->stat)) ||
|
||||
(readw(&i2c_base->con) & I2C_CON_MST)) {
|
||||
udelay(1000);
|
||||
/* have to read to clear intrrupt */
|
||||
writew(0xFFFF, &i2c_base->stat);
|
||||
if (--eout == 0)
|
||||
/* better leave with error than hang */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
write_exit:
|
||||
flush_fifo();
|
||||
writew(0xFFFF, &i2c_base->stat);
|
||||
return i2c_error;
|
||||
writew(0, &i2c_base->cnt);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void wait_for_bb(void)
|
||||
static u32 wait_for_bb(void)
|
||||
{
|
||||
int timeout = I2C_TIMEOUT;
|
||||
u16 stat;
|
||||
u32 stat;
|
||||
|
||||
writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
|
||||
while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
|
||||
writew(stat, &i2c_base->stat);
|
||||
udelay(1000);
|
||||
|
|
@ -394,30 +517,28 @@ static void wait_for_bb(void)
|
|||
if (timeout <= 0) {
|
||||
printf("timed out in wait_for_bb: I2C_STAT=%x\n",
|
||||
readw(&i2c_base->stat));
|
||||
stat |= I2C_STAT_TIMEO;
|
||||
}
|
||||
writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
|
||||
return stat;
|
||||
}
|
||||
|
||||
static u16 wait_for_pin(void)
|
||||
static u32 wait_for_status_mask(u16 mask)
|
||||
{
|
||||
u16 status;
|
||||
u32 status;
|
||||
int timeout = I2C_TIMEOUT;
|
||||
|
||||
do {
|
||||
udelay(1000);
|
||||
status = readw(&i2c_base->stat);
|
||||
} while (!(status &
|
||||
(I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
|
||||
I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
|
||||
I2C_STAT_AL)) && timeout--);
|
||||
} while (!(status & mask) && timeout--);
|
||||
|
||||
if (timeout <= 0) {
|
||||
printf("timed out in wait_for_pin: I2C_STAT=%x\n",
|
||||
printf("timed out in wait_for_status_mask: I2C_STAT=%x\n",
|
||||
readw(&i2c_base->stat));
|
||||
writew(0xFFFF, &i2c_base->stat);
|
||||
status = 0;
|
||||
status |= I2C_STAT_TIMEO;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -60,7 +60,9 @@
|
|||
/* I2C Buffer Configuration Register (I2C_BUF): */
|
||||
|
||||
#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */
|
||||
#define I2C_RXFIFO_CLEAR (1 << 14) /* RX FIFO Clear */
|
||||
#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */
|
||||
#define I2C_TXFIFO_CLEAR (1 << 6) /* TX FIFO clear */
|
||||
|
||||
/* I2C Configuration Register (I2C_CON): */
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue