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Xilinx changes for v2022.01-rc3

Browse source 
sdhci:
 - Fix emmc mini case with missing firmware interface
 
 zynqmp:
 - Restore JTAG interface if required
 - Allow overriding board name
 - Add support for DLC21
 - Fix one fallthrought statement description
 - Use config macro instead of name duplication
 - Save multiboot to variable
 
 firmware:
 - Handle ipi_req errors better
 - Use local buffer in case user doesn't need it instead of NULL/0 location
 
 spi:
 - gqsi: Fix write issue at low frequencies
 
 net:
 - gem: Disable broadcasts
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Merge tag 'xilinx-for-v2022.01-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.01-rc3

sdhci:
- Fix emmc mini case with missing firmware interface

zynqmp:
- Restore JTAG interface if required
- Allow overriding board name
- Add support for DLC21
- Fix one fallthrought statement description
- Use config macro instead of name duplication
- Save multiboot to variable

firmware:
- Handle ipi_req errors better
- Use local buffer in case user doesn't need it instead of NULL/0 location

spi:
- gqsi: Fix write issue at low frequencies

net:
- gem: Disable broadcasts
This commit is contained in:
Tom Rini 2021-11-16 09:51:04 -05:00
commit 2ffa0e87df
12 changed files with 1243 additions and 22 deletions
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1
arch/arm/dts/Makefile
View file

@ -319,6 +319,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
avnet-ultra96-rev1.dtb \
avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb \
zynqmp-a2197-revA.dtb \
zynqmp-dlc21-revA.dtb \
zynqmp-e-a2197-00-revA.dtb \
zynqmp-g-a2197-00-revA.dtb \
zynqmp-m-a2197-01-revA.dtb \

221
arch/arm/dts/zynqmp-dlc21-revA.dts Normal file
View file

@ -0,0 +1,221 @@
// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Xilinx ZynqMP DLC21 revA
*
* (C) Copyright 2019 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
#include <include/dt-bindings/gpio/gpio.h>
/ {
model = "Smartlynq+ DLC21 RevA";
compatible = "xlnx,zynqmp-dlc21-revA", "xlnx,zynqmp-dlc21",
"xlnx,zynqmp";
aliases {
ethernet0 = &gem0;
gpio0 = &gpio;
i2c0 = &i2c0;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
rtc0 = &rtc;
serial0 = &uart0;
serial2 = &dcc;
usb0 = &usb0;
usb1 = &usb1;
spi0 = &spi0;
nvmem0 = &eeprom;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0 0 0 0x80000000>, <0x8 0 0x3 0x80000000>;
};
si5332_1: si5332_1 { /* clk0_sgmii - u142 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
si5332_2: si5332_2 { /* clk1_usb - u142 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
};
&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
status = "okay";
non-removable;
disable-wp;
bus-width = <8>;
xlnx,mio_bank = <0>;
};
&sdhci1 { /* sd1 MIO45-51 cd in place */
status = "okay";
no-1-8-v;
disable-wp;
xlnx,mio_bank = <1>;
};
&psgtr {
status = "okay";
/* sgmii, usb3 */
clocks = <&si5332_1>, <&si5332_2>;
clock-names = "ref0", "ref1";
};
&uart0 { /* uart0 MIO38-39 */
status = "okay";
u-boot,dm-pre-reloc;
};
&gem0 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "sgmii"; /* DTG generates this properly 1512 */
is-internal-pcspma;
/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
phy0: ethernet-phy@0 {
reg = <0>;
};
};
&gpio {
status = "okay";
gpio-line-names = "", "", "", "", "", /* 0 - 4 */
"", "", "", "", "", /* 5 - 9 */
"", "", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
"EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
"EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
"", "DISP_SCL", "DISP_DC_B", "DISP_RES_B", "DISP_CS_B", /* 25 - 29 */
"", "DISP_SDI", "SYSTEM_RST_R_B", "", "I2C0_SCL", /* 30 - 34 */
"I2C0_SDA", "", "", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
"", "", "ETH_RESET_B", "", "", /* 40 - 44 */
"SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
"SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
"USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
"USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
"USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
"USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
"USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
"", "", /* 78 - 79 */
"", "", "", "", "", /* 80 - 84 */
"", "", "", "", "", /* 85 -89 */
"", "", "", "", "", /* 90 - 94 */
"", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
"VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */
"", "", "", "", "", /* 105 - 109 */
"SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */
"SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */
"", "", "", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */
"SYSCTLR_UTIL_2V5_EN", "", "", "", "", /* 125 - 129 */
"", "", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "", /* 130 - 134 */
"", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */
"", "", "SYSCTLR_ETH_RESET_B", "", "", /* 140 - 144 */
"", "", "", "", "", /* 145 - 149 */
"", "", "", "", "", /* 150 - 154 */
"", "", "", "", "", /* 155 - 159 */
"", "", "", "", "", /* 160 - 164 */
"", "", "", "", "", /* 165 - 169 */
"", "", "", ""; /* 170 - 174 */
};
&i2c0 { /* MIO34/35 */
status = "okay";
clock-frequency = <400000>;
jtag_vref: mcp4725@62 {
compatible = "microchip,mcp4725";
reg = <0x62>;
vref-millivolt = <3300>;
};
eeprom: eeprom@50 { /* u46 */
compatible = "atmel,24c32";
reg = <0x50>;
};
/* u138 - TUSB320IRWBR - for USB-C */
};
&usb0 {
status = "okay";
xlnx,usb-polarity = <0>;
xlnx,usb-reset-mode = <0>;
};
&dwc3_0 {
status = "okay";
dr_mode = "peripheral";
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
maximum-speed = "super-speed";
phy-names = "usb3-phy";
phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
};
&usb1 {
status = "disabled"; /* Any unknown issue with USB-C */
xlnx,usb-polarity = <0>;
xlnx,usb-reset-mode = <0>;
};
&dwc3_1 {
/delete-property/ phy-names ;
/delete-property/ phys ;
dr_mode = "host";
maximum-speed = "high-speed";
snps,dis_u2_susphy_quirk ;
snps,dis_u3_susphy_quirk ;
status = "okay";
};
&xilinx_ams {
status = "okay";
};
&ams_ps {
status = "okay";
};
&ams_pl {
status = "okay";
};
&spi0 {
status = "okay";
is-decoded-cs = <0>;
num-cs = <1>;
u-boot,dm-pre-reloc;
displayspi@0 {
compatible = "syncoam,seps525";
u-boot,dm-pre-reloc;
reg = <0>;
status = "okay";
spi-max-frequency = <10000000>;
spi-cpol;
spi-cpha;
rotate = <0>;
fps = <50>;
buswidth = <8>;
txbuflen = <64000>;
reset-gpios = <&gpio 0x1c GPIO_ACTIVE_LOW>;
dc-gpios = <&gpio 0x1b GPIO_ACTIVE_HIGH>;
debug = <0>;
};
};

2
arch/arm/dts/zynqmp-p-a2197-00-revA.dts
View file

@ -46,7 +46,7 @@
si5332_1: si5332_1 { /* clk0_sgmii - u142 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <33333333>; /* FIXME */
clock-frequency = <125000000>;
};
si5332_2: si5332_2 { /* clk1_usb - u142 */

9
arch/arm/mach-zynqmp/Kconfig
View file

@ -25,6 +25,7 @@ config SPL_SPI
default y if ZYNQ_QSPI
config SYS_BOARD
string "Board name"
default "zynqmp"
config SYS_VENDOR
@ -149,6 +150,14 @@ config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
Overwrite bootmode selected via boot mode pins to tell SPL what should
be the next boot device.
config SPL_ZYNQMP_RESTORE_JTAG
bool "Restore JTAG"
depends on SPL
help
Booting SPL in secure mode causes the CSU to disable the JTAG interface
even if no eFuses were burnt. This option restores the interface if
possible.
config ZYNQ_SDHCI_MAX_FREQ
default 200000000

31
arch/arm/mach-zynqmp/include/mach/hardware.h
View file

@ -39,20 +39,26 @@
#define RESET_REASON_INTERNAL BIT(1)
#define RESET_REASON_EXTERNAL BIT(0)
#define CRLAPB_DBG_LPD_CTRL_SETUP_CLK 0x01002002
#define CRLAPB_RST_LPD_DBG_RESET 0
struct crlapb_regs {
u32 reserved0[36];
u32 cpu_r5_ctrl; /* 0x90 */
u32 reserved1[37];
u32 reserved1[7];
u32 dbg_lpd_ctrl; /* 0xB0 */
u32 reserved2[29];
u32 timestamp_ref_ctrl; /* 0x128 */
u32 reserved2[53];
u32 reserved3[53];
u32 boot_mode; /* 0x200 */
u32 reserved3_0[7];
u32 reserved4_0[7];
u32 reset_reason; /* 0x220 */
u32 reserved3_1[6];
u32 reserved4_1[6];
u32 rst_lpd_top; /* 0x23C */
u32 reserved4[4];
u32 rst_lpd_dbg; /* 0x240 */
u32 reserved5[3];
u32 boot_pin_ctrl; /* 0x250 */
u32 reserved5[21];
u32 reserved6[21];
};
#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
@ -141,12 +147,23 @@ struct apu_regs {
#define ZYNQMP_SILICON_VER_MASK 0xF
#define ZYNQMP_SILICON_VER_SHIFT 0
#define CSU_JTAG_SEC_GATE_DISABLE GENMASK(7, 0)
#define CSU_JTAG_DAP_ENABLE_DEBUG GENMASK(7, 0)
#define CSU_JTAG_CHAIN_WR_SETUP GENMASK(1, 0)
#define CSU_PCAP_PROG_RELEASE_PL BIT(0)
struct csu_regs {
u32 reserved0[4];
u32 multi_boot;
u32 reserved1[11];
u32 reserved1[7];
u32 jtag_chain_status_wr;
u32 jtag_chain_status;
u32 jtag_sec;
u32 jtag_dap_cfg;
u32 idcode;
u32 version;
u32 reserved2[3055];
u32 pcap_prog;
};
#define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR)

922
board/xilinx/zynqmp/zynqmp-dlc21-revA/psu_init_gpl.c Normal file
View file

@ -0,0 +1,922 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (c) Copyright 2015 Xilinx, Inc. All rights reserved.
*/
#include <asm/arch/psu_init_gpl.h>
#include <xil_io.h>
static unsigned long psu_pll_init_data(void)
{
psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014000U);
psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
mask_poll(0xFF5E0040, 0x00000002U);
psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U);
psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
mask_poll(0xFF5E0040, 0x00000001U);
psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
mask_poll(0xFD1A0044, 0x00000001U);
psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
mask_poll(0xFD1A0044, 0x00000002U);
psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014000U);
psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
mask_poll(0xFD1A0044, 0x00000004U);
psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000200U);
psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
return 1;
}
static unsigned long psu_clock_init_data(void)
{
psu_mask_write(0xFF5E0050, 0x063F3F07U, 0x06013C00U);
psu_mask_write(0xFF180360, 0x00000003U, 0x00000001U);
psu_mask_write(0xFF180308, 0x00000006U, 0x00000006U);
psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
psu_mask_write(0xFF5E0064, 0x023F3F07U, 0x02010600U);
psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010800U);
psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U);
psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
psu_mask_write(0xFF5E007C, 0x013F3F07U, 0x01010702U);
psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000400U);
psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000200U);
psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000200U);
psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010502U);
psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010802U);
psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010402U);
psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01030A00U);
psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000104U);
psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U);
psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000203U);
psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000202U);
psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
return 1;
}
static unsigned long psu_ddr_init_data(void)
{
psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x43041010U);
psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
psu_mask_write(0xFD070030, 0x0000007FU, 0x00000008U);
psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00818126U);
psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300501U);
psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000700U);
psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x110C2412U);
psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041CU);
psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D0BU);
psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1607010EU);
psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000909U);
psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
psu_mask_write(0xFD070200, 0x0000001FU, 0x00000018U);
psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010101U);
psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x0F010101U);
psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U);
psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F07U);
psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000700U);
psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
psu_mask_write(0xFD070244, 0x00003333U, 0x00000201U);
psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
psu_mask_write(0xFD070300, 0x00000011U, 0x00000001U);
psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
psu_mask_write(0xFD070400, 0x00000111U, 0x00000101U);
psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U);
psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U);
psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E0U);
psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F08U);
psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28170008U);
psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x024B2B07U);
psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00370F08U);
psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000501U);
psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000700U);
psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x810091C7U);
psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00030236U);
psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12344000U);
psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000005U);
psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x000879DBU);
psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B00CU);
psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B00CU);
psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x80803660U);
psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x55556000U);
psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0xAAAAAAAAU);
psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x0029A4A4U);
psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0C00B000U);
psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x80803660U);
psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x55556000U);
psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0xAAAAAAAAU);
psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x0029A4A4U);
psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0C00B000U);
psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x80803660U);
psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x55556000U);
psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0xAAAAAAAAU);
psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x0029A4A4U);
psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0C00B000U);
psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x80803660U);
psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x55556000U);
psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0xAAAAAAAAU);
psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x0029A4A4U);
psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0C00B000U);
psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x15019FFEU);
psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x21100000U);
psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01266300U);
psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70400000U);
psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x15019FFEU);
psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x21100000U);
psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01266300U);
psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70400000U);
psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
return 1;
}
static unsigned long psu_ddr_qos_init_data(void)
{
psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
return 1;
}
static unsigned long psu_mio_init_data(void)
{
psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000008U);
psu_mask_write(0xFF180068, 0x000000FEU, 0x00000080U);
psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF180074, 0x000000FEU, 0x00000080U);
psu_mask_write(0xFF180078, 0x000000FEU, 0x00000080U);
psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000080U);
psu_mask_write(0xFF180080, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF180084, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF180088, 0x000000FEU, 0x00000040U);
psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000040U);
psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF180098, 0x000000FEU, 0x000000C0U);
psu_mask_write(0xFF18009C, 0x000000FEU, 0x000000C0U);
psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF180100, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF180104, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF180108, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF180110, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF180114, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF180118, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF180120, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF180124, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF180128, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF180130, 0x000000FEU, 0x00000060U);
psu_mask_write(0xFF180134, 0x000000FEU, 0x00000060U);
psu_mask_write(0xFF180204, 0xFCFFE000U, 0x00000000U);
psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02040U);
psu_mask_write(0xFF18020C, 0x00003FFFU, 0x0000000BU);
psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x033FFFFFU);
psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x01FF9FFFU);
psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x03F76FFFU);
psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x02FBFFBFU);
psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x03FF4FF4U);
psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
return 1;
}
static unsigned long psu_peripherals_pre_init_data(void)
{
psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
return 1;
}
static unsigned long psu_peripherals_init_data(void)
{
psu_mask_write(0xFD1A0100, 0x0000807CU, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U);
psu_mask_write(0xFF5E023C, 0x00000C00U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U);
psu_mask_write(0xFF180320, 0x33843384U, 0x00801284U);
psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000200U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000008U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x01FC9F08U);
psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
mask_delay(1);
psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
mask_delay(5);
psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
return 1;
}
static unsigned long psu_serdes_init_data(void)
{
psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000FU);
psu_mask_write(0xFD410004, 0x0000001FU, 0x00000008U);
psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
psu_mask_write(0xFD402864, 0x00000080U, 0x00000080U);
psu_mask_write(0xFD406094, 0x00000010U, 0x00000010U);
psu_mask_write(0xFD406368, 0x000000FFU, 0x00000038U);
psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
psu_mask_write(0xFD406370, 0x000000FFU, 0x000000F4U);
psu_mask_write(0xFD406374, 0x000000FFU, 0x00000031U);
psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
psu_mask_write(0xFD40106C, 0x0000000FU, 0x0000000FU);
psu_mask_write(0xFD4000F4, 0x0000000BU, 0x0000000BU);
psu_mask_write(0xFD40506C, 0x00000003U, 0x00000003U);
psu_mask_write(0xFD4040F4, 0x00000003U, 0x00000003U);
psu_mask_write(0xFD4050CC, 0x00000020U, 0x00000020U);
psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
psu_mask_write(0xFD4018F8, 0x000000FFU, 0x0000007DU);
psu_mask_write(0xFD4018FC, 0x000000FFU, 0x0000007DU);
psu_mask_write(0xFD401990, 0x000000FFU, 0x00000000U);
psu_mask_write(0xFD401924, 0x000000FFU, 0x00000082U);
psu_mask_write(0xFD401928, 0x000000FFU, 0x00000000U);
psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
psu_mask_write(0xFD401914, 0x000000FFU, 0x000000FFU);
psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
psu_mask_write(0xFD401940, 0x000000FFU, 0x000000FFU);
psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
psu_mask_write(0xFD40589C, 0x00000080U, 0x00000080U);
psu_mask_write(0xFD4058F8, 0x000000FFU, 0x0000001AU);
psu_mask_write(0xFD4058FC, 0x000000FFU, 0x0000001AU);
psu_mask_write(0xFD405990, 0x000000FFU, 0x00000010U);
psu_mask_write(0xFD405924, 0x000000FFU, 0x000000FEU);
psu_mask_write(0xFD405928, 0x000000FFU, 0x00000000U);
psu_mask_write(0xFD405900, 0x000000FFU, 0x0000001AU);
psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000000U);
psu_mask_write(0xFD405980, 0x000000FFU, 0x000000FFU);
psu_mask_write(0xFD405914, 0x000000FFU, 0x000000F7U);
psu_mask_write(0xFD405918, 0x00000001U, 0x00000001U);
psu_mask_write(0xFD405940, 0x000000FFU, 0x000000F7U);
psu_mask_write(0xFD405944, 0x00000001U, 0x00000001U);
psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
psu_mask_write(0xFD410010, 0x00000077U, 0x00000035U);
psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U);
psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U);
return 1;
}
static unsigned long psu_resetout_init_data(void)
{
psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
psu_mask_write(0xFF5E023C, 0x00000800U, 0x00000000U);
psu_mask_write(0xFF9E0080, 0x00000001U, 0x00000001U);
psu_mask_write(0xFF9E007C, 0x00000001U, 0x00000001U);
psu_mask_write(0xFF5E023C, 0x00000280U, 0x00000000U);
psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U);
psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
psu_mask_write(0xFE30C200, 0x00023FFFU, 0x00022457U);
psu_mask_write(0xFE30C630, 0x003FFF00U, 0x00000000U);
psu_mask_write(0xFE30C12C, 0x00004000U, 0x00004000U);
psu_mask_write(0xFE30C11C, 0x00000400U, 0x00000400U);
psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
mask_poll(0xFD4023E4, 0x00000010U);
mask_poll(0xFD4063E4, 0x00000010U);
return 1;
}
static unsigned long psu_resetin_init_data(void)
{
psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000A80U);
psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000001U);
return 1;
}
static unsigned long psu_afi_config(void)
{
psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
psu_mask_write(0xFD615000, 0x00000F00U, 0x00000A00U);
psu_mask_write(0xFF419000, 0x00000300U, 0x00000000U);
psu_mask_write(0xFD360000, 0x00000003U, 0x00000000U);
psu_mask_write(0xFD360014, 0x00000003U, 0x00000000U);
return 1;
}
static unsigned long psu_ddr_phybringup_data(void)
{
unsigned int regval = 0;
unsigned int pll_retry = 10;
unsigned int pll_locked = 0;
int cur_r006_trefprd;
while ((pll_retry > 0) && (!pll_locked)) {
Xil_Out32(0xFD080004, 0x00040010);
Xil_Out32(0xFD080004, 0x00040011);
while ((Xil_In32(0xFD080030) & 0x1) != 1)
;
pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
>> 31;
pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
>> 16;
pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
>> 16;
pll_retry--;
}
Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
if (!pll_locked)
return 0;
Xil_Out32(0xFD080004U, 0x00040063U);
while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
;
prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
;
Xil_Out32(0xFD0701B0U, 0x00000001U);
Xil_Out32(0xFD070320U, 0x00000001U);
while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
;
prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
Xil_Out32(0xFD080004, 0x0004FE01);
regval = Xil_In32(0xFD080030);
while (regval != 0x80000FFF)
regval = Xil_In32(0xFD080030);
regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
if (regval != 0)
return 0;
Xil_Out32(0xFD080200U, 0x110091C7U);
cur_r006_trefprd = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_r006_trefprd);
prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
Xil_Out32(0xFD080004, 0x00060001);
regval = Xil_In32(0xFD080030);
while ((regval & 0x80004001) != 0x80004001)
regval = Xil_In32(0xFD080030);
prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
Xil_Out32(0xFD080200U, 0x810091C7U);
prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_r006_trefprd);
Xil_Out32(0xFD080004, 0x0000C001);
regval = Xil_In32(0xFD080030);
while ((regval & 0x80000C01) != 0x80000C01)
regval = Xil_In32(0xFD080030);
Xil_Out32(0xFD070180U, 0x01000040U);
Xil_Out32(0xFD070060U, 0x00000000U);
prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
return 1;
}
static int serdes_enb_coarse_saturation(void)
{
Xil_Out32(0xFD402094, 0x00000010);
Xil_Out32(0xFD406094, 0x00000010);
Xil_Out32(0xFD40A094, 0x00000010);
Xil_Out32(0xFD40E094, 0x00000010);
return 1;
}
static int serdes_fixcal_code(void)
{
int maskstatus = 1;
unsigned int rdata = 0;
unsigned int match_pmos_code[23];
unsigned int match_nmos_code[23];
unsigned int match_ical_code[7];
unsigned int match_rcal_code[7];
unsigned int p_code = 0, n_code = 0, i_code = 0, r_code = 0;
unsigned int repeat_count = 0;
unsigned int L3_TM_CALIB_DIG20 = 0;
unsigned int L3_TM_CALIB_DIG19 = 0;
unsigned int L3_TM_CALIB_DIG18 = 0;
unsigned int L3_TM_CALIB_DIG16 = 0;
unsigned int L3_TM_CALIB_DIG15 = 0;
unsigned int L3_TM_CALIB_DIG14 = 0;
int count = 0, i = 0;
rdata = Xil_In32(0xFD40289C);
rdata = rdata & ~0x03;
rdata = rdata | 0x1;
Xil_Out32(0xFD40289C, rdata);
do {
if (count == 1100000)
break;
rdata = Xil_In32(0xFD402B1C);
count++;
} while ((rdata & 0x0000000E) != 0x0000000E);
for (i = 0; i < 23; i++) {
match_pmos_code[i] = 0;
match_nmos_code[i] = 0;
}
for (i = 0; i < 7; i++) {
match_ical_code[i] = 0;
match_rcal_code[i] = 0;
}
do {
Xil_Out32(0xFD410010, 0x00000000);
Xil_Out32(0xFD410014, 0x00000000);
Xil_Out32(0xFD410010, 0x00000001);
Xil_Out32(0xFD410014, 0x00000000);
maskstatus = mask_poll(0xFD40EF14, 0x2);
if (maskstatus == 0) {
xil_printf("#SERDES initialization timed out\n\r");
return maskstatus;
}
p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
;
i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
;
if (p_code >= 0x26 && p_code <= 0x3C)
match_pmos_code[p_code - 0x26] += 1;
if (n_code >= 0x26 && n_code <= 0x3C)
match_nmos_code[n_code - 0x26] += 1;
if (i_code >= 0xC && i_code <= 0x12)
match_ical_code[i_code - 0xc] += 1;
if (r_code >= 0x6 && r_code <= 0xC)
match_rcal_code[r_code - 0x6] += 1;
} while (repeat_count++ < 10);
for (i = 0; i < 23; i++) {
if (match_pmos_code[i] >= match_pmos_code[0]) {
match_pmos_code[0] = match_pmos_code[i];
p_code = 0x26 + i;
}
if (match_nmos_code[i] >= match_nmos_code[0]) {
match_nmos_code[0] = match_nmos_code[i];
n_code = 0x26 + i;
}
}
for (i = 0; i < 7; i++) {
if (match_ical_code[i] >= match_ical_code[0]) {
match_ical_code[0] = match_ical_code[i];
i_code = 0xC + i;
}
if (match_rcal_code[i] >= match_rcal_code[0]) {
match_rcal_code[0] = match_rcal_code[i];
r_code = 0x6 + i;
}
}
L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
| 0x20 | 0x4 | ((n_code >> 3) & 0x3);
L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
| 0x40 | 0x8 | ((i_code >> 1) & 0x7);
L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
return maskstatus;
}
static int init_serdes(void)
{
int status = 1;
status &= psu_resetin_init_data();
status &= serdes_fixcal_code();
status &= serdes_enb_coarse_saturation();
status &= psu_serdes_init_data();
status &= psu_resetout_init_data();
return status;
}
static void init_peripheral(void)
{
psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
}
int psu_init(void)
{
int status = 1;
status &= psu_mio_init_data();
status &= psu_peripherals_pre_init_data();
status &= psu_pll_init_data();
status &= psu_clock_init_data();
status &= psu_ddr_init_data();
status &= psu_ddr_phybringup_data();
status &= psu_peripherals_init_data();
status &= init_serdes();
init_peripheral();
status &= psu_afi_config();
psu_ddr_qos_init_data();
if (status == 0)
return 1;
return 0;
}

48
board/xilinx/zynqmp/zynqmp.c
View file

@ -358,6 +358,21 @@ static int multi_boot(void)
return multiboot;
}
#if defined(CONFIG_SPL_BUILD)
static void restore_jtag(void)
{
if (current_el() != 3)
return;
writel(CSU_JTAG_SEC_GATE_DISABLE, &csu_base->jtag_sec);
writel(CSU_JTAG_DAP_ENABLE_DEBUG, &csu_base->jtag_dap_cfg);
writel(CSU_JTAG_CHAIN_WR_SETUP, &csu_base->jtag_chain_status_wr);
writel(CRLAPB_DBG_LPD_CTRL_SETUP_CLK, &crlapb_base->dbg_lpd_ctrl);
writel(CRLAPB_RST_LPD_DBG_RESET, &crlapb_base->rst_lpd_dbg);
writel(CSU_PCAP_PROG_RELEASE_PL, &csu_base->pcap_prog);
}
#endif
#define PS_SYSMON_ANALOG_BUS_VAL 0x3210
#define PS_SYSMON_ANALOG_BUS_REG 0xFFA50914
@ -377,6 +392,10 @@ int board_init(void)
zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
zynqmp_pm_cfg_obj_size);
printf("Silicon version:\t%d\n", zynqmp_get_silicon_version());
/* the CSU disables the JTAG interface when secure boot is enabled */
if (CONFIG_IS_ENABLED(ZYNQMP_RESTORE_JTAG))
restore_jtag();
#else
if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
xilinx_read_eeprom();
@ -477,7 +496,7 @@ ulong board_get_usable_ram_top(ulong total_size)
lmb_init(&lmb);
lmb_add(&lmb, gd->ram_base, gd->ram_size);
boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob);
size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE),
size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE);
reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE);
if (!reg)
@ -621,7 +640,7 @@ int board_late_init(void)
const char *mode;
char *new_targets;
char *env_targets;
int ret;
int ret, multiboot;
#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
usb_ether_init();
@ -639,6 +658,10 @@ int board_late_init(void)
if (ret)
return ret;
multiboot = multi_boot();
if (multiboot >= 0)
env_set_hex("multiboot", multiboot);
bootmode = zynqmp_get_bootmode();
puts("Bootmode: ");
@ -691,7 +714,7 @@ int board_late_init(void)
break;
case SD1_LSHFT_MODE:
puts("LVL_SHFT_");
/* fall through */
fallthrough;
case SD_MODE1:
puts("SD_MODE1\n");
if (uclass_get_device_by_name(UCLASS_MMC,
@ -845,6 +868,10 @@ void set_dfu_alt_info(char *interface, char *devstr)
memset(buf, 0, sizeof(buf));
multiboot = multi_boot();
if (multiboot < 0)
multiboot = 0;
multiboot = env_get_hex("multiboot", multiboot);
debug("Multiboot: %d\n", multiboot);
switch (zynqmp_get_bootmode()) {
@ -856,20 +883,23 @@ void set_dfu_alt_info(char *interface, char *devstr)
if (!multiboot)
snprintf(buf, DFU_ALT_BUF_LEN,
"mmc %d:1=boot.bin fat %d 1;"
"u-boot.itb fat %d 1",
bootseq, bootseq, bootseq);
"%s fat %d 1",
bootseq, bootseq,
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, bootseq);
else
snprintf(buf, DFU_ALT_BUF_LEN,
"mmc %d:1=boot%04d.bin fat %d 1;"
"u-boot.itb fat %d 1",
bootseq, multiboot, bootseq, bootseq);
"%s fat %d 1",
bootseq, multiboot, bootseq,
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, bootseq);
break;
case QSPI_MODE_24BIT:
case QSPI_MODE_32BIT:
snprintf(buf, DFU_ALT_BUF_LEN,
"sf 0:0=boot.bin raw %x 0x1500000;"
"u-boot.itb raw 0x%x 0x500000",
multiboot * SZ_32K, CONFIG_SYS_SPI_U_BOOT_OFFS);
"%s raw 0x%x 0x500000",
multiboot * SZ_32K, CONFIG_SPL_FS_LOAD_PAYLOAD_NAME,
CONFIG_SYS_SPI_U_BOOT_OFFS);
break;
default:
return;

2
configs/xilinx_zynqmp_virt_defconfig
View file

@ -81,7 +81,7 @@ CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
CONFIG_CMD_UBI=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1 zynqmp-sm-k26-revA zynqmp-smk-k26-revA"
CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1 zynqmp-sm-k26-revA zynqmp-smk-k26-revA zynqmp-dlc21-revA"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent interrupts iommus power-domains"
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_FAT=y

10
drivers/firmware/firmware-zynqmp.c
View file

@ -29,6 +29,10 @@ static int ipi_req(const u32 *req, size_t req_len, u32 *res, size_t res_maxlen)
{
struct zynqmp_ipi_msg msg;
int ret;
u32 buffer[PAYLOAD_ARG_CNT];
if (!res)
res = buffer;
if (req_len > PMUFW_PAYLOAD_ARG_CNT ||
res_maxlen > PMUFW_PAYLOAD_ARG_CNT)
@ -164,6 +168,7 @@ int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
* firmware API is limited by the SMC call size
*/
u32 regs[] = {api_id, arg0, arg1, arg2, arg3};
int ret;
if (api_id == PM_FPGA_LOAD) {
/* Swap addr_hi/low because of incompatibility */
@ -173,7 +178,10 @@ int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
regs[2] = temp;
}
ipi_req(regs, PAYLOAD_ARG_CNT, ret_payload, PAYLOAD_ARG_CNT);
ret = ipi_req(regs, PAYLOAD_ARG_CNT, ret_payload,
PAYLOAD_ARG_CNT);
if (ret)
return ret;
#else
return -EPERM;
#endif

6
drivers/mmc/zynq_sdhci.c
View file

@ -69,6 +69,12 @@ __weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value)
return 0;
}
__weak int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
u32 arg3, u32 *ret_payload)
{
return 0;
}
#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
/* Default settings for ZynqMP Clock Phases */
static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0,

2
drivers/net/zynq_gem.c
View file

@ -60,6 +60,7 @@
#define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */
#define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */
#define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
#define ZYNQ_GEM_NWCFG_NO_BRDC BIT(5) /* No broadcast */
#define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */
#define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
@ -77,6 +78,7 @@
#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
ZYNQ_GEM_NWCFG_FDEN | \
ZYNQ_GEM_NWCFG_NO_BRDC | \
ZYNQ_GEM_NWCFG_FSREM | \
ZYNQ_GEM_NWCFG_MDCCLKDIV)

11
drivers/spi/zynqmp_gqspi.c
View file

@ -37,6 +37,7 @@
*/
#define GQSPI_IXR_TXNFULL_MASK 0x00000004 /* QSPI TX FIFO Overflow */
#define GQSPI_IXR_TXFULL_MASK 0x00000008 /* QSPI TX FIFO is full */
#define GQSPI_IXR_TXFIFOEMPTY_MASK 0x00000100 /* QSPI TX FIFO is Empty */
#define GQSPI_IXR_RXNEMTY_MASK 0x00000010 /* QSPI RX FIFO Not Empty */
#define GQSPI_IXR_GFEMTY_MASK 0x00000080 /* QSPI Generic FIFO Empty */
#define GQSPI_IXR_GFNFULL_MASK 0x00000200 /* QSPI GENFIFO not full */
@ -279,9 +280,6 @@ static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
/* Dummy generic FIFO entry */
zynqmp_qspi_fill_gen_fifo(priv, 0);
zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
}
@ -470,6 +468,13 @@ static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size)
}
}
ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_TXFIFOEMPTY_MASK, 1,
GQSPI_TIMEOUT, 1);
if (ret) {
printf("%s: Timeout\n", __func__);
return ret;
}
priv->tx_buf += len;
return 0;
}