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arm: Remove IXP425 boards pdnb3 and scpu
Remove Prodrive pdnb3 board (including the scpu variant) support from mainline. As its unmaintained and not needed any more for quite some time. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Martijn de Gouw <martijn.de.gouw@prodrive.nl> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
This commit is contained in:
Stefan Roese
Albert ARIBAUD
parent
262f08d6ea
commit
304db0b38c
7 changed files with 3 additions and 775 deletions
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@ -1,28 +0,0 @@
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := flash.o pdnb3.o nand.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -1,73 +0,0 @@
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/*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/ixp425.h>
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#if !defined(CONFIG_FLASH_CFI_DRIVER)
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/*
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* include common flash code (for esd boards)
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*/
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#include "../common/flash.c"
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/*
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* Prototypes
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*/
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static ulong flash_get_size (vu_long * addr, flash_info_t * info);
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static inline ulong ld(ulong x)
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{
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ulong k = 0;
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while (x >>= 1)
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++k;
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return k;
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}
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unsigned long flash_init(void)
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{
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unsigned long size;
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int i;
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/* Init: no FLASHes known */
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for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; i++)
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flash_info[i].flash_id = FLASH_UNKNOWN;
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size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
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if (flash_info[0].flash_id == FLASH_UNKNOWN)
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
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size, size<<20);
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/* Reconfigure CS0 to actual FLASH size */
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*IXP425_EXP_CS0 = (*IXP425_EXP_CS0 & ~0x00003C00) | ((ld(size) - 9) << 10);
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/* Monitor protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
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&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
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/* Environment protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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CONFIG_ENV_ADDR,
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CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
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&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
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/* Redundant environment protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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CONFIG_ENV_ADDR_REDUND,
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CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
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&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
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flash_info[0].size = size;
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return size;
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}
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#endif /* CONFIG_FLASH_CFI_DRIVER */
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@ -1,129 +0,0 @@
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/*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#if defined(CONFIG_CMD_NAND)
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#include <nand.h>
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struct pdnb3_ndfc_regs {
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uchar cmd;
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uchar wait;
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uchar addr;
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uchar term;
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uchar data;
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};
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static u8 hwctl;
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static struct pdnb3_ndfc_regs *pdnb3_ndfc;
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#define readb(addr) *(volatile u_char *)(addr)
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#define readl(addr) *(volatile u_long *)(addr)
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#define writeb(d,addr) *(volatile u_char *)(addr) = (d)
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/*
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* The PDNB3 has a NAND Flash Controller (NDFC) that handles all accesses to
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* the NAND devices. The NDFC has command, address and data registers that
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* when accessed will set up the NAND flash pins appropriately. We'll use the
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* hwcontrol function to save the configuration in a global variable.
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* We can then use this information in the read and write functions to
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* determine which NDFC register to access.
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*
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* There is one NAND devices on the board, a Hynix HY27US08561A (32 MByte).
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*/
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static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *this = mtd->priv;
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if (ctrl & NAND_CTRL_CHANGE) {
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if ( ctrl & NAND_CLE )
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hwctl |= 0x1;
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else
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hwctl &= ~0x1;
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if ( ctrl & NAND_ALE )
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hwctl |= 0x2;
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else
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hwctl &= ~0x2;
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if ( (ctrl & NAND_NCE) != NAND_NCE)
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writeb(0x00, &(pdnb3_ndfc->term));
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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}
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static u_char pdnb3_nand_read_byte(struct mtd_info *mtd)
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{
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return readb(&(pdnb3_ndfc->data));
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}
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static void pdnb3_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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for (i = 0; i < len; i++) {
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if (hwctl & 0x1)
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writeb(buf[i], &(pdnb3_ndfc->cmd));
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else if (hwctl & 0x2)
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writeb(buf[i], &(pdnb3_ndfc->addr));
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else
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writeb(buf[i], &(pdnb3_ndfc->data));
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}
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}
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static void pdnb3_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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int i;
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for (i = 0; i < len; i++)
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buf[i] = readb(&(pdnb3_ndfc->data));
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}
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static int pdnb3_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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for (i = 0; i < len; i++)
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if (buf[i] != readb(&(pdnb3_ndfc->data)))
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return i;
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return 0;
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}
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static int pdnb3_nand_dev_ready(struct mtd_info *mtd)
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{
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/*
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* Blocking read to wait for NAND to be ready
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*/
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readb(&(pdnb3_ndfc->wait));
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/*
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* Return always true
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*/
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return 1;
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}
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int board_nand_init(struct nand_chip *nand)
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{
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pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CONFIG_SYS_NAND_BASE;
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nand->ecc.mode = NAND_ECC_SOFT;
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/* Set address of NAND IO lines (Using Linear Data Access Region) */
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nand->IO_ADDR_R = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
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nand->IO_ADDR_W = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
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/* Reference hardware control function */
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nand->cmd_ctrl = pdnb3_nand_hwcontrol;
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nand->read_byte = pdnb3_nand_read_byte;
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nand->write_buf = pdnb3_nand_write_buf;
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nand->read_buf = pdnb3_nand_read_buf;
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nand->verify_buf = pdnb3_nand_verify_buf;
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nand->dev_ready = pdnb3_nand_dev_ready;
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return 0;
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}
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#endif
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@ -1,220 +0,0 @@
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/*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <malloc.h>
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#include <asm/arch/ixp425.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* predefine these here for FPGA programming (before including fpga.c) */
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#define SET_FPGA(data) *IXP425_GPIO_GPOUTR = (data)
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#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_DONE)
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#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_INIT)
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#define OLD_VAL old_val
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static unsigned long old_val = 0;
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/*
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* include common fpga code (for prodrive boards)
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*/
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#include "../common/fpga.c"
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/*
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* Miscelaneous platform dependent initialisations
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*/
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0x00000100;
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GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_FPGA_RESET);
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GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SYS_RUNNING);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SYS_RUNNING);
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/*
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* Setup GPIO's for FPGA programming
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*/
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PRG);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DATA);
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GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_INIT);
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GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DONE);
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/*
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* Setup GPIO's for interrupts
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*/
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GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
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GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
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GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
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GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
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GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTORE_INT);
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GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTORE_INT);
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GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTART_INT);
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GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTART_INT);
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/*
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* Setup GPIO's for 33MHz clock output
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*/
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*IXP425_GPIO_GPCLKR = 0x01FF0000;
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK_33M);
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/*
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* Setup other chip select's
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*/
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*IXP425_EXP_CS1 = CONFIG_SYS_EXP_CS1;
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return 0;
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}
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/*
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* Check Board Identity
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*/
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int checkboard(void)
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{
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char buf[64];
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int i = getenv_f("serial#", buf, sizeof(buf));
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puts("Board: PDNB3");
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if (i > 0) {
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puts(", serial# ");
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puts(buf);
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}
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putc('\n');
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return (0);
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}
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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return (0);
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}
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int do_fpga_boot(unsigned char *fpgadata)
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{
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unsigned char *dst;
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int status;
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int index;
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int i;
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ulong len = CONFIG_SYS_MALLOC_LEN;
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/*
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* Setup GPIO's for FPGA programming
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*/
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
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/*
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* Save value so no readback is required upon programming
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*/
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old_val = *IXP425_GPIO_GPOUTR;
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/*
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* First try to decompress fpga image (gzip compressed?)
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*/
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dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
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if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
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printf("Error: Image has to be gzipp'ed!\n");
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return -1;
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}
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status = fpga_boot(dst, len);
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if (status != 0) {
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printf("\nFPGA: Booting failed ");
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switch (status) {
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case ERROR_FPGA_PRG_INIT_LOW:
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printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_INIT_HIGH:
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printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_DONE:
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printf("(Timeout: DONE not high after programming FPGA)\n ");
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break;
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}
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/* display infos on fpgaimage */
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index = 15;
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for (i=0; i<4; i++) {
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len = dst[index];
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printf("FPGA: %s\n", &(dst[index+1]));
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index += len+3;
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}
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putc ('\n');
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/* delayed reboot */
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for (i=5; i>0; i--) {
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printf("Rebooting in %2d seconds \r",i);
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for (index=0;index<1000;index++)
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udelay(1000);
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}
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putc('\n');
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do_reset(NULL, 0, 0, NULL);
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}
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puts("FPGA: ");
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/* display infos on fpgaimage */
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index = 15;
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for (i=0; i<4; i++) {
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len = dst[index];
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printf("%s ", &(dst[index+1]));
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index += len+3;
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}
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putc('\n');
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free(dst);
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/*
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* Reset FPGA
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*/
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_FPGA_RESET);
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udelay(10);
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GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
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return (0);
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}
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int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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ulong addr;
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if (argc < 2)
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return cmd_usage(cmdtp);
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addr = simple_strtoul(argv[1], NULL, 16);
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return do_fpga_boot((unsigned char *)addr);
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}
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U_BOOT_CMD(
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fpga, 2, 0, do_fpga,
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"boot FPGA",
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"address size\n - boot FPGA with gzipped image at <address>"
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);
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#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
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extern struct pci_controller hose;
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extern void pci_ixp_init(struct pci_controller * hose);
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void pci_init_board(void)
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{
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extern void pci_ixp_init (struct pci_controller *hose);
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pci_ixp_init(&hose);
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}
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#endif
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@ -366,8 +366,6 @@ Active arm ixp - - actux1
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Active arm ixp - - actux1 actux1_4_32 actux1:FLASH2X2,RAM_32MB Michael Schwingen <michael@schwingen.org>
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Active arm ixp - - actux1 actux1_8_16 actux1:FLASH1X8 Michael Schwingen <michael@schwingen.org>
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Active arm ixp - - actux1 actux1_8_32 actux1:FLASH1X8,RAM_32MB Michael Schwingen <michael@schwingen.org>
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Active arm ixp - prodrive pdnb3 pdnb3 - Stefan Roese <sr@denx.de>
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Active arm ixp - prodrive pdnb3 scpu pdnb3:SCPU Stefan Roese <sr@denx.de>
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Active arm pxa - - - balloon3 - Marek Vasut <marek.vasut@gmail.com>
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Active arm pxa - - - h2200 - Lukasz Dalek <luk0104@gmail.com>
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Active arm pxa - - - palmld - Marek Vasut <marek.vasut@gmail.com>
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@ -11,7 +11,9 @@ easily if here is something they might want to dig for...
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Board Arch CPU Commit Removed Last known maintainer/contact
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=================================================================================================
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omap1510inn arm arm925t - - Kshitij Gupta <kshitij@ti.com>
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pdnb3 arm ixp - 2013-09-24 Stefan Roese <sr@denx.de>
|
||||
scpu arm ixp - 2013-09-24 Stefan Roese <sr@denx.de>
|
||||
omap1510inn arm arm925t 0610a16 2013-09-23 Kshitij Gupta <kshitij@ti.com>
|
||||
CANBT powerpc 405CR fb8f4fd 2013-08-07 Matthias Fuchs <matthias.fuchs@esd.eu>
|
||||
Alaska8220 powerpc mpc8220 d6ed322 2013-05-11
|
||||
Yukon8220 powerpc mpc8220 d6ed322 2013-05-11
|
||||
|
|
|
|||
|
|
@ -1,322 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2006-2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* Configuation settings for the PDNB3 board.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#define CONFIG_IXP425 1 /* This is an IXP425 CPU */
|
||||
#define CONFIG_PDNB3 1 /* on an PDNB3 board */
|
||||
|
||||
#define CONFIG_MACH_TYPE 1002
|
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
|
||||
#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
#define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */
|
||||
#define CONFIG_PHY_ADDR 16 /* NPE0 PHY address */
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_PHY1_ADDR 18 /* NPE1 PHY address */
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
|
||||
|
||||
/*
|
||||
* Misc configuration options
|
||||
*/
|
||||
#define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */
|
||||
#define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
#define CONFIG_INITRD_TAG 1
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (1 << 20)
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_IXP_SERIAL
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_PING
|
||||
|
||||
#if !defined(CONFIG_SCPU)
|
||||
#define CONFIG_CMD_NAND
|
||||
#endif
|
||||
|
||||
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */
|
||||
|
||||
#define CONFIG_IXP425_TIMER_CLK 66666666
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
/***************************************************************
|
||||
* Platform/Board specific defines start here.
|
||||
***************************************************************/
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Default configuration (environment varibles...)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"hostname=pdnb3\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate} " \
|
||||
"mtdparts=${mtdparts}\0" \
|
||||
"flash_nfs=run nfsargs addip addtty;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip addtty;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
|
||||
"bootm\0" \
|
||||
"rootpath=/opt/buildroot\0" \
|
||||
"bootfile=/tftpboot/netbox/uImage\0" \
|
||||
"kernel_addr=50080000\0" \
|
||||
"ramdisk_addr=50200000\0" \
|
||||
"load=tftp 100000 /tftpboot/netbox/u-boot.bin\0" \
|
||||
"update=protect off 50000000 5007dfff;era 50000000 5007dfff;" \
|
||||
"cp.b 100000 50000000 ${filesize};" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"upd=run load update\0" \
|
||||
"ipaddr=10.0.0.233\0" \
|
||||
"serverip=10.0.0.152\0" \
|
||||
"netmask=255.255.0.0\0" \
|
||||
"ethaddr=c6:6f:13:36:f3:81\0" \
|
||||
"eth1addr=c6:6f:13:36:f3:82\0" \
|
||||
"mtdparts=IXP4XX-Flash.0:504k@0(uboot),4k@504k(env)," \
|
||||
"4k@508k(renv)\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run net_nfs"
|
||||
|
||||
/*
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
|
||||
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x50000000
|
||||
#define CONFIG_SYS_FLASH_BASE 0x50000000
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#if defined(CONFIG_SCPU)
|
||||
#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 512 kB for Monitor */
|
||||
#else
|
||||
#define CONFIG_SYS_MONITOR_LEN (504 << 10) /* Reserve 512 kB for Monitor */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Expansion bus settings
|
||||
*/
|
||||
#if defined(CONFIG_SCPU)
|
||||
#define CONFIG_SYS_EXP_CS0 0x94d23C42 /* 8bit, max size */
|
||||
#else
|
||||
#define CONFIG_SYS_EXP_CS0 0x94913C43 /* 8bit, max size */
|
||||
#endif
|
||||
#define CONFIG_SYS_EXP_CS1 0x85000043 /* 8bit, 512bytes */
|
||||
|
||||
/*
|
||||
* SDRAM settings
|
||||
*/
|
||||
#define CONFIG_SYS_SDR_CONFIG 0x18
|
||||
#define CONFIG_SYS_SDR_MODE_CONFIG 0x1
|
||||
#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
|
||||
|
||||
/*
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#if defined(CONFIG_SCPU)
|
||||
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
|
||||
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
|
||||
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
|
||||
#endif
|
||||
|
||||
#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
|
||||
#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
|
||||
#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
|
||||
/*
|
||||
* The following defines are added for buggy IOP480 byte interface.
|
||||
* All other boards should use the standard values (CPCI405 etc.)
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
|
||||
#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
|
||||
#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
|
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||
#if defined(CONFIG_SCPU)
|
||||
/* no redundant environment on SCPU */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
|
||||
#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
|
||||
#else
|
||||
#define CONFIG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */
|
||||
#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SCPU)
|
||||
/*
|
||||
* NAND-FLASH stuff
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base Address */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* GPIO settings
|
||||
*/
|
||||
|
||||
/* FPGA program pin configuration */
|
||||
#define CONFIG_SYS_GPIO_PRG 12 /* FPGA program pin (cpu output)*/
|
||||
#define CONFIG_SYS_GPIO_CLK 10 /* FPGA clk pin (cpu output) */
|
||||
#define CONFIG_SYS_GPIO_DATA 14 /* FPGA data pin (cpu output) */
|
||||
#define CONFIG_SYS_GPIO_INIT 13 /* FPGA init pin (cpu input) */
|
||||
#define CONFIG_SYS_GPIO_DONE 11 /* FPGA done pin (cpu input) */
|
||||
|
||||
/* other GPIO's */
|
||||
#define CONFIG_SYS_GPIO_RESTORE_INT 0
|
||||
#define CONFIG_SYS_GPIO_RESTART_INT 1
|
||||
#define CONFIG_SYS_GPIO_SYS_RUNNING 2
|
||||
#define CONFIG_SYS_GPIO_PCI_INTA 3
|
||||
#define CONFIG_SYS_GPIO_PCI_INTB 4
|
||||
#define CONFIG_SYS_GPIO_I2C_SCL 6
|
||||
#define CONFIG_SYS_GPIO_I2C_SDA 7
|
||||
#define CONFIG_SYS_GPIO_FPGA_RESET 9
|
||||
#define CONFIG_SYS_GPIO_CLK_33M 15
|
||||
|
||||
/*
|
||||
* I2C stuff
|
||||
*/
|
||||
|
||||
/* enable I2C and select the hardware/software driver */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
|
||||
#define CONFIG_SYS_I2C_SOFT_SPEED 83000 /* 83 kHz is supposed to work */
|
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
|
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration
|
||||
*/
|
||||
#define PB_SCL (1 << CONFIG_SYS_GPIO_I2C_SCL)
|
||||
#define PB_SDA (1 << CONFIG_SYS_GPIO_I2C_SDA)
|
||||
|
||||
#define I2C_INIT GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SCL)
|
||||
#define I2C_ACTIVE GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SDA)
|
||||
#define I2C_TRISTATE GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_I2C_SDA)
|
||||
#define I2C_READ ((*IXP425_GPIO_GPINR & PB_SDA) != 0)
|
||||
#define I2C_SDA(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SDA); \
|
||||
else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SDA)
|
||||
#define I2C_SCL(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SCL); \
|
||||
else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SCL)
|
||||
#define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */
|
||||
|
||||
/*
|
||||
* I2C RTC
|
||||
*/
|
||||
#if 0 /* test-only */
|
||||
#define CONFIG_RTC_DS1340 1
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
||||
#else
|
||||
/* M41T11 Serial Access Timekeeper(R) SRAM */
|
||||
#define CONFIG_RTC_M41T11 1
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
||||
#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with the linux driver */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Spartan3 FPGA configuration support
|
||||
*/
|
||||
#define CONFIG_SYS_FPGA_MAX_SIZE 700*1024 /* 700kByte for XC3S500E */
|
||||
|
||||
#define CONFIG_SYS_FPGA_PRG (1 << CONFIG_SYS_GPIO_PRG) /* FPGA program pin (cpu output)*/
|
||||
#define CONFIG_SYS_FPGA_CLK (1 << CONFIG_SYS_GPIO_CLK) /* FPGA clk pin (cpu output) */
|
||||
#define CONFIG_SYS_FPGA_DATA (1 << CONFIG_SYS_GPIO_DATA) /* FPGA data pin (cpu output) */
|
||||
#define CONFIG_SYS_FPGA_INIT (1 << CONFIG_SYS_GPIO_INIT) /* FPGA init pin (cpu input) */
|
||||
#define CONFIG_SYS_FPGA_DONE (1 << CONFIG_SYS_GPIO_DONE) /* FPGA done pin (cpu input) */
|
||||
|
||||
/*
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
|
||||
/* additions for new relocation code, must be added to all boards */
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Add table
Reference in a new issue