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ram: rk3328: only do data traning for cs0
No need to do twice data training for rk3328 ddr sdram, we re-use the setting for both channel. And adjust the sdram_init properly for correct init flow. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: YouMin Chen <cym@rock-chips.com>
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parent
338b86c9b3
commit
31531f6fdb
1 changed files with 3 additions and 7 deletions
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@ -377,16 +377,12 @@ static int sdram_init(struct dram_info *dram,
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printf("data training error\n");
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return -1;
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}
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if (data_training(dram, 1, sdram_params->base.dramtype) != 0) {
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printf("data training error\n");
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return -1;
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}
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if (sdram_params->base.dramtype == DDR4)
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pctl_write_vrefdq(dram->pctl, 0x3, 5670,
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sdram_params->base.dramtype);
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if (pre_init == 0) {
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if (pre_init != 0) {
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rx_deskew_switch_adjust(dram);
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tx_deskew_switch_adjust(dram);
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}
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@ -482,7 +478,7 @@ static int sdram_init_detect(struct dram_info *dram,
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memcpy(&sdram_ch, &sdram_params->ch,
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sizeof(struct rk3328_sdram_channel));
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sdram_init(dram, sdram_params, 1);
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sdram_init(dram, sdram_params, 0);
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dram_detect_cap(dram, sdram_params, 0);
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/* modify bw, cs related timing */
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@ -495,7 +491,7 @@ static int sdram_init_detect(struct dram_info *dram,
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sdram_ch.noc_timings.ddrtiming.b.bwratio = 1;
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/* reinit sdram by real dram cap */
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sdram_init(dram, sdram_params, 0);
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sdram_init(dram, sdram_params, 1);
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/* redetect cs1 row */
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sdram_detect_cs1_row(cap_info, sdram_params->base.dramtype);
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