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rockchip: pinctrl: rk3399: add support for the SPI5 controller

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This commit adds support for the pin-configuration of the SPI5
controller of the RK3399 through the following changes:
 * grf_rk3399.h: adds definition for configuring the SPI5 pins
   		 in the GPIO2C group
 * periph.h: defines PERIPH_ID_SPI3 through PERIPH_ID_SPI5
 * pinctrl_rk3399.c: adds the reverse-mapping from the IRQ# to
   		     PERIPH_ID_SPI5; dispatches PERIPH_ID_SPI3
		     through SPI5 to the appropriate pin-config
		     function; implements the pin-configuration
		     for PERIPH_ID_SPI5 using the GPIO2C group

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Philipp Tomsich 2017-04-20 22:05:53 +02:00 • committed by Simon Glass
parent 9fc354e246
commit 315e6a38f9
3 changed files with 32 additions and 0 deletions
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12
arch/arm/include/asm/arch-rockchip/grf_rk3399.h
View file

@ -344,6 +344,18 @@ enum {
GRF_GPIO2C1_SEL_SHIFT = 2,
GRF_GPIO2C1_SEL_MASK = 3 << GRF_GPIO2C1_SEL_SHIFT,
GRF_UART0BT_SOUT = 1,
GRF_GPIO2C4_SEL_SHIFT = 8,
GRF_GPIO2C4_SEL_MASK = 3 << GRF_GPIO2C4_SEL_SHIFT,
GRF_SPI5EXPPLUS_RXD = 2,
GRF_GPIO2C5_SEL_SHIFT = 10,
GRF_GPIO2C5_SEL_MASK = 3 << GRF_GPIO2C5_SEL_SHIFT,
GRF_SPI5EXPPLUS_TXD = 2,
GRF_GPIO2C6_SEL_SHIFT = 12,
GRF_GPIO2C6_SEL_MASK = 3 << GRF_GPIO2C6_SEL_SHIFT,
GRF_SPI5EXPPLUS_CLK = 2,
GRF_GPIO2C7_SEL_SHIFT = 14,
GRF_GPIO2C7_SEL_MASK = 3 << GRF_GPIO2C7_SEL_SHIFT,
GRF_SPI5EXPPLUS_CSN0 = 2,
/* GRF_GPIO3A_IOMUX */
GRF_GPIO3A0_SEL_SHIFT = 0,

3
arch/arm/include/asm/arch-rockchip/periph.h
View file

@ -27,6 +27,9 @@ enum periph_id {
PERIPH_ID_SPI0,
PERIPH_ID_SPI1,
PERIPH_ID_SPI2,
PERIPH_ID_SPI3,
PERIPH_ID_SPI4,
PERIPH_ID_SPI5,
PERIPH_ID_UART0,
PERIPH_ID_UART1,
PERIPH_ID_UART2,

17
drivers/pinctrl/rockchip/pinctrl_rk3399.c
View file

@ -145,7 +145,19 @@ static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs *grf,
| GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT
| GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT);
break;
case PERIPH_ID_SPI5:
if (cs != 0)
goto err;
rk_clrsetreg(&grf->gpio2c_iomux,
GRF_GPIO2C4_SEL_MASK | GRF_GPIO2C5_SEL_MASK
| GRF_GPIO2C6_SEL_MASK | GRF_GPIO2C7_SEL_MASK,
GRF_SPI5EXPPLUS_RXD << GRF_GPIO2C4_SEL_SHIFT
| GRF_SPI5EXPPLUS_TXD << GRF_GPIO2C5_SEL_SHIFT
| GRF_SPI5EXPPLUS_CLK << GRF_GPIO2C6_SEL_SHIFT
| GRF_SPI5EXPPLUS_CSN0 << GRF_GPIO2C7_SEL_SHIFT);
break;
default:
printf("%s: spi_id %d is not supported.\n", __func__, spi_id);
goto err;
}
@ -259,6 +271,9 @@ static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags)
case PERIPH_ID_SPI0:
case PERIPH_ID_SPI1:
case PERIPH_ID_SPI2:
case PERIPH_ID_SPI3:
case PERIPH_ID_SPI4:
case PERIPH_ID_SPI5:
pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags);
break;
case PERIPH_ID_UART0:
@ -307,6 +322,8 @@ static int rk3399_pinctrl_get_periph_id(struct udevice *dev,
return PERIPH_ID_SPI1;
case 52:
return PERIPH_ID_SPI2;
case 132:
return PERIPH_ID_SPI5;
case 57:
return PERIPH_ID_I2C0;
case 59: /* Note strange order */