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https://github.com/Fishwaldo/u-boot.git
synced 2025-03-15 19:51:37 +00:00
arm: socfpga: Enable Intel N5X device build
Add defconfig for N5X to support legacy, ATF and VAB boot flow. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
This commit is contained in:
parent
ed9050f87e
commit
31b51cb1d2
5 changed files with 257 additions and 6 deletions
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@ -8,7 +8,7 @@ config NR_DRAM_BANKS
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config SOCFPGA_SECURE_VAB_AUTH
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bool "Enable boot image authentication with Secure Device Manager"
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depends on TARGET_SOCFPGA_AGILEX
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depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X
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select FIT_IMAGE_POST_PROCESS
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select SHA384
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select SHA512_ALGO
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@ -91,6 +91,22 @@ config TARGET_SOCFPGA_GEN5
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imply SPL_SYS_MALLOC_SIMPLE
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imply SPL_USE_TINY_PRINTF
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config TARGET_SOCFPGA_N5X
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bool
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select ARMV8_MULTIENTRY
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select ARMV8_SET_SMPEN
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select BINMAN if SPL_ATF
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select CLK
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select FPGA_INTEL_SDM_MAILBOX
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select NCORE_CACHE
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select SPL_ALTERA_SDRAM
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select SPL_CLK if SPL
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select TARGET_SOCFPGA_SOC64
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config TARGET_SOCFPGA_N5X_SOCDK
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bool "Intel eASIC SoCDK (N5X)"
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select TARGET_SOCFPGA_N5X
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config TARGET_SOCFPGA_SOC64
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bool
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@ -185,6 +201,7 @@ config SYS_BOARD
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default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
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default "is1" if TARGET_SOCFPGA_IS1
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default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
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default "n5x-socdk" if TARGET_SOCFPGA_N5X_SOCDK
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default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
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default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
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default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
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@ -194,6 +211,7 @@ config SYS_BOARD
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config SYS_VENDOR
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default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
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default "intel" if TARGET_SOCFPGA_N5X_SOCDK
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default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
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default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
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default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
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@ -223,6 +241,7 @@ config SYS_CONFIG_NAME
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default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
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default "socfpga_is1" if TARGET_SOCFPGA_IS1
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default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
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default "socfpga_n5x_socdk" if TARGET_SOCFPGA_N5X_SOCDK
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default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
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default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
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default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
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@ -4,7 +4,7 @@
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
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# Copyright (C) 2017-2020 Intel Corporation <www.intel.com>
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# Copyright (C) 2017-2021 Intel Corporation <www.intel.com>
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obj-y += board.o
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obj-y += clock_manager.o
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@ -56,6 +56,21 @@ obj-y += wrap_handoff_soc64.o
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obj-y += wrap_pll_config_soc64.o
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endif
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ifdef CONFIG_TARGET_SOCFPGA_N5X
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obj-y += clock_manager_n5x.o
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obj-y += lowlevel_init_soc64.o
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obj-y += mailbox_s10.o
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obj-y += misc_soc64.o
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obj-y += mmu-arm64_s10.o
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obj-y += reset_manager_s10.o
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obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
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obj-y += system_manager_soc64.o
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obj-y += timer_s10.o
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obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o
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obj-y += wrap_handoff_soc64.o
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obj-y += wrap_pll_config_soc64.o
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endif
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ifdef CONFIG_SPL_BUILD
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ifdef CONFIG_TARGET_SOCFPGA_GEN5
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obj-y += spl_gen5.o
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@ -64,18 +79,21 @@ obj-y += wrap_iocsr_config.o
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obj-y += wrap_pinmux_config.o
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obj-y += wrap_sdram_config.o
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endif
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ifdef CONFIG_TARGET_SOCFPGA_SOC64
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obj-y += firewall.o
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obj-y += spl_soc64.o
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endif
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ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
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obj-y += spl_a10.o
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endif
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ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
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obj-y += firewall.o
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obj-y += spl_s10.o
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obj-y += spl_soc64.o
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endif
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ifdef CONFIG_TARGET_SOCFPGA_AGILEX
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obj-y += firewall.o
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obj-y += spl_agilex.o
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obj-y += spl_soc64.o
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endif
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ifdef CONFIG_TARGET_SOCFPGA_N5X
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obj-y += spl_n5x.o
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endif
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else
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obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
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74
configs/socfpga_n5x_atf_defconfig
Normal file
74
configs/socfpga_n5x_atf_defconfig
Normal file
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@ -0,0 +1,74 @@
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CONFIG_ARM=y
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CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
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CONFIG_ARCH_SOCFPGA=y
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CONFIG_SYS_TEXT_BASE=0x200000
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_NR_DRAM_BANKS=2
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CONFIG_ENV_SIZE=0x1000
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CONFIG_ENV_OFFSET=0x200
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CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
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CONFIG_DM_GPIO=y
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CONFIG_DEFAULT_DEVICE_TREE="socfpga_n5x_socdk"
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CONFIG_SPL_TEXT_BASE=0xFFE00000
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CONFIG_TARGET_SOCFPGA_N5X_SOCDK=y
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CONFIG_IDENT_STRING="socfpga_n5x"
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CONFIG_SPL_FS_FAT=y
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CONFIG_FIT=y
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CONFIG_SPL_FIT_SIGNATURE=y
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CONFIG_SPL_LOAD_FIT=y
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CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
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# CONFIG_USE_SPL_FIT_GENERATOR is not set
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CONFIG_BOOTDELAY=5
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="earlycon panic=-1 earlyprintk=ttyS0,115200"
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CONFIG_USE_BOOTCOMMAND=y
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CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
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CONFIG_SPL_CRC32=y
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CONFIG_SPL_CACHE=y
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CONFIG_SPL_SPI_LOAD=y
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CONFIG_SPL_ATF=y
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CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
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CONFIG_HUSH_PARSER=y
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CONFIG_SYS_PROMPT="SOCFPGA_N5X # "
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CONFIG_CMD_MEMTEST=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_CMD_WDT=y
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_SPL_ALTERA_SDRAM=y
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CONFIG_DWAPB_GPIO=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_DW=y
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CONFIG_MMC_DW=y
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CONFIG_MTD=y
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CONFIG_SF_DEFAULT_MODE=0x2003
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ90X1=y
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CONFIG_DM_ETH=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_MII=y
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CONFIG_DM_RESET=y
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CONFIG_SPI=y
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CONFIG_CADENCE_QSPI=y
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CONFIG_DESIGNWARE_SPI=y
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CONFIG_USB=y
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CONFIG_USB_DWC2=y
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CONFIG_USB_STORAGE=y
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CONFIG_DESIGNWARE_WATCHDOG=y
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CONFIG_WDT=y
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# CONFIG_SPL_USE_TINY_PRINTF is not set
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CONFIG_PANIC_HANG=y
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65
configs/socfpga_n5x_defconfig
Normal file
65
configs/socfpga_n5x_defconfig
Normal file
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@ -0,0 +1,65 @@
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CONFIG_ARM=y
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CONFIG_ARCH_SOCFPGA=y
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CONFIG_SYS_TEXT_BASE=0x1000
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_NR_DRAM_BANKS=2
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CONFIG_ENV_SIZE=0x1000
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CONFIG_ENV_OFFSET=0x200
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CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000
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CONFIG_DM_GPIO=y
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CONFIG_DEFAULT_DEVICE_TREE="socfpga_n5x_socdk"
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CONFIG_SPL_TEXT_BASE=0xFFE00000
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CONFIG_TARGET_SOCFPGA_N5X_SOCDK=y
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CONFIG_IDENT_STRING="socfpga_n5x"
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CONFIG_SPL_FS_FAT=y
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# CONFIG_PSCI_RESET is not set
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CONFIG_BOOTDELAY=5
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="earlycon panic=-1 earlyprintk=ttyS0,115200"
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CONFIG_USE_BOOTCOMMAND=y
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CONFIG_BOOTCOMMAND="run fatscript; run mmcload; run linux_qspi_enable; run mmcboot"
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CONFIG_SPL_CACHE=y
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CONFIG_SPL_SPI_LOAD=y
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CONFIG_HUSH_PARSER=y
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CONFIG_SYS_PROMPT="SOCFPGA_N5X # "
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CONFIG_CMD_MEMTEST=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_CMD_WDT=y
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_SPL_ALTERA_SDRAM=y
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CONFIG_DWAPB_GPIO=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_DW=y
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CONFIG_MMC_DW=y
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CONFIG_SF_DEFAULT_MODE=0x2003
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ90X1=y
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CONFIG_DM_ETH=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_MII=y
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CONFIG_DM_RESET=y
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CONFIG_SPI=y
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CONFIG_CADENCE_QSPI=y
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CONFIG_DESIGNWARE_SPI=y
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CONFIG_USB=y
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CONFIG_USB_DWC2=y
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CONFIG_USB_STORAGE=y
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CONFIG_DESIGNWARE_WATCHDOG=y
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CONFIG_WDT=y
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# CONFIG_SPL_USE_TINY_PRINTF is not set
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CONFIG_PANIC_HANG=y
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75
configs/socfpga_n5x_vab_defconfig
Normal file
75
configs/socfpga_n5x_vab_defconfig
Normal file
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CONFIG_ARM=y
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CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
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CONFIG_ARCH_SOCFPGA=y
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CONFIG_SYS_TEXT_BASE=0x200000
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_NR_DRAM_BANKS=2
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CONFIG_ENV_SIZE=0x1000
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CONFIG_ENV_OFFSET=0x200
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CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
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CONFIG_DM_GPIO=y
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CONFIG_DEFAULT_DEVICE_TREE="socfpga_n5x_socdk"
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CONFIG_SPL_TEXT_BASE=0xFFE00000
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CONFIG_SOCFPGA_SECURE_VAB_AUTH=y
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CONFIG_TARGET_SOCFPGA_N5X_SOCDK=y
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CONFIG_IDENT_STRING="socfpga_n5x"
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CONFIG_SPL_FS_FAT=y
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CONFIG_FIT=y
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CONFIG_SPL_FIT_SIGNATURE=y
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CONFIG_SPL_LOAD_FIT=y
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CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
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# CONFIG_USE_SPL_FIT_GENERATOR is not set
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CONFIG_BOOTDELAY=5
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="earlycon panic=-1 earlyprintk=ttyS0,115200"
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CONFIG_USE_BOOTCOMMAND=y
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CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
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CONFIG_SPL_CRC32=y
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CONFIG_SPL_CACHE=y
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CONFIG_SPL_SPI_LOAD=y
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CONFIG_SPL_ATF=y
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CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
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CONFIG_HUSH_PARSER=y
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CONFIG_SYS_PROMPT="SOCFPGA_N5X # "
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CONFIG_CMD_MEMTEST=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_CMD_WDT=y
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_SPL_ALTERA_SDRAM=y
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CONFIG_DWAPB_GPIO=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_DW=y
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CONFIG_MMC_DW=y
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CONFIG_MTD=y
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CONFIG_SF_DEFAULT_MODE=0x2003
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ90X1=y
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CONFIG_DM_ETH=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_MII=y
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CONFIG_DM_RESET=y
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CONFIG_SPI=y
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CONFIG_CADENCE_QSPI=y
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CONFIG_DESIGNWARE_SPI=y
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CONFIG_USB=y
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CONFIG_USB_DWC2=y
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CONFIG_USB_STORAGE=y
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CONFIG_DESIGNWARE_WATCHDOG=y
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CONFIG_WDT=y
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# CONFIG_SPL_USE_TINY_PRINTF is not set
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CONFIG_PANIC_HANG=y
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