mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-29 10:31:30 +00:00
Merge branch 'master' of /home/wd/git/u-boot/custodians
This commit is contained in:
Wolfgang Denk
commit
33aa4eac66
7 changed files with 882 additions and 2 deletions
|
|
@ -365,6 +365,7 @@ Heiko Schocher <hs@denx.de>
|
||||||
jupiter MPC5200
|
jupiter MPC5200
|
||||||
mgcoge MPC8247
|
mgcoge MPC8247
|
||||||
mgsuvd MPC852
|
mgsuvd MPC852
|
||||||
|
mucmc52 MPC5200
|
||||||
muas3001 MPC8270
|
muas3001 MPC8270
|
||||||
municse MPC5200
|
municse MPC5200
|
||||||
sc3 PPC405GP
|
sc3 PPC405GP
|
||||||
|
|
|
||||||
3
Makefile
3
Makefile
|
|
@ -626,6 +626,9 @@ mecp5200_config: unconfig
|
||||||
motionpro_config: unconfig
|
motionpro_config: unconfig
|
||||||
@$(MKCONFIG) motionpro ppc mpc5xxx motionpro
|
@$(MKCONFIG) motionpro ppc mpc5xxx motionpro
|
||||||
|
|
||||||
|
mucmc52_config: unconfig
|
||||||
|
@$(MKCONFIG) mucmc52 ppc mpc5xxx mucmc52
|
||||||
|
|
||||||
munices_config: unconfig
|
munices_config: unconfig
|
||||||
@$(MKCONFIG) munices ppc mpc5xxx munices
|
@$(MKCONFIG) munices ppc mpc5xxx munices
|
||||||
|
|
||||||
|
|
|
||||||
53
board/mucmc52/Makefile
Normal file
53
board/mucmc52/Makefile
Normal file
|
|
@ -0,0 +1,53 @@
|
||||||
|
#
|
||||||
|
# (C) Copyright 2008
|
||||||
|
# Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||||
|
#
|
||||||
|
# (C) Copyright 2003-2006
|
||||||
|
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
#
|
||||||
|
# See file CREDITS for list of people who contributed to this
|
||||||
|
# project.
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or
|
||||||
|
# modify it under the terms of the GNU General Public License as
|
||||||
|
# published by the Free Software Foundation; either version 2 of
|
||||||
|
# the License, or (at your option) any later version.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program; if not, write to the Free Software
|
||||||
|
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
# MA 02111-1307 USA
|
||||||
|
#
|
||||||
|
|
||||||
|
include $(TOPDIR)/config.mk
|
||||||
|
|
||||||
|
LIB = $(obj)lib$(BOARD).a
|
||||||
|
|
||||||
|
COBJS := $(BOARD).o
|
||||||
|
|
||||||
|
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||||
|
OBJS := $(addprefix $(obj),$(COBJS))
|
||||||
|
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||||
|
|
||||||
|
$(LIB): $(obj).depend $(OBJS)
|
||||||
|
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||||
|
|
||||||
|
clean:
|
||||||
|
rm -f $(SOBJS) $(OBJS)
|
||||||
|
|
||||||
|
distclean: clean
|
||||||
|
rm -f $(LIB) core *.bak .depend
|
||||||
|
|
||||||
|
#########################################################################
|
||||||
|
|
||||||
|
# defines $(obj).depend target
|
||||||
|
include $(SRCTREE)/rules.mk
|
||||||
|
|
||||||
|
sinclude $(obj).depend
|
||||||
|
|
||||||
|
#########################################################################
|
||||||
45
board/mucmc52/config.mk
Normal file
45
board/mucmc52/config.mk
Normal file
|
|
@ -0,0 +1,45 @@
|
||||||
|
#
|
||||||
|
# (C) Copyright 2008
|
||||||
|
# Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||||
|
#
|
||||||
|
# (C) Copyright 2004
|
||||||
|
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
#
|
||||||
|
# See file CREDITS for list of people who contributed to this
|
||||||
|
# project.
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or
|
||||||
|
# modify it under the terms of the GNU General Public License as
|
||||||
|
# published by the Free Software Foundation; either version 2 of
|
||||||
|
# the License, or (at your option) any later version.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program; if not, write to the Free Software
|
||||||
|
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
# MA 02111-1307 USA
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# MUCMC52 board:
|
||||||
|
#
|
||||||
|
# Valid values for TEXT_BASE are:
|
||||||
|
#
|
||||||
|
# 0xFFE00000 boot high
|
||||||
|
#
|
||||||
|
# 0x00100000 boot from RAM (for testing only)
|
||||||
|
#
|
||||||
|
|
||||||
|
ifndef TEXT_BASE
|
||||||
|
## Standard: boot high
|
||||||
|
TEXT_BASE = 0xFFF00000
|
||||||
|
## For testing: boot from RAM
|
||||||
|
#TEXT_BASE = 0x00100000
|
||||||
|
endif
|
||||||
|
|
||||||
|
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
|
||||||
|
LDSCRIPT := $(SRCTREE)/cpu/mpc5xxx/u-boot.lds
|
||||||
400
board/mucmc52/mucmc52.c
Normal file
400
board/mucmc52/mucmc52.c
Normal file
|
|
@ -0,0 +1,400 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2003-2004
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* (C) Copyright 2004
|
||||||
|
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
|
||||||
|
*
|
||||||
|
* (C) Copyright 2004
|
||||||
|
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
|
||||||
|
*
|
||||||
|
* (C) Copyright 2008
|
||||||
|
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <mpc5xxx.h>
|
||||||
|
#include <pci.h>
|
||||||
|
#include <malloc.h>
|
||||||
|
#include <asm/processor.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
|
||||||
|
#ifndef CFG_RAMBOOT
|
||||||
|
static void sdram_start (int hi_addr)
|
||||||
|
{
|
||||||
|
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
|
||||||
|
|
||||||
|
/* unlock mode register */
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
|
||||||
|
(SDRAM_CONTROL | 0x80000000 | hi_addr_bit));
|
||||||
|
__asm__ volatile ("sync");
|
||||||
|
|
||||||
|
/* precharge all banks */
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
|
||||||
|
(SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
|
||||||
|
__asm__ volatile ("sync");
|
||||||
|
|
||||||
|
#if SDRAM_DDR
|
||||||
|
/* set mode register: extended mode */
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_MODE, (SDRAM_EMODE));
|
||||||
|
__asm__ volatile ("sync");
|
||||||
|
|
||||||
|
/* set mode register: reset DLL */
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_MODE,
|
||||||
|
(SDRAM_MODE | 0x04000000));
|
||||||
|
__asm__ volatile ("sync");
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* precharge all banks */
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
|
||||||
|
(SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
|
||||||
|
__asm__ volatile ("sync");
|
||||||
|
|
||||||
|
/* auto refresh */
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
|
||||||
|
(SDRAM_CONTROL | 0x80000004 | hi_addr_bit));
|
||||||
|
__asm__ volatile ("sync");
|
||||||
|
|
||||||
|
/* set mode register */
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_MODE, (SDRAM_MODE));
|
||||||
|
__asm__ volatile ("sync");
|
||||||
|
|
||||||
|
/* normal operation */
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
|
||||||
|
(SDRAM_CONTROL | hi_addr_bit));
|
||||||
|
__asm__ volatile ("sync");
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ATTENTION: Although partially referenced initdram does NOT make real use
|
||||||
|
* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
|
||||||
|
* is something else than 0x00000000.
|
||||||
|
*/
|
||||||
|
|
||||||
|
phys_size_t initdram (int board_type)
|
||||||
|
{
|
||||||
|
ulong dramsize = 0;
|
||||||
|
ulong dramsize2 = 0;
|
||||||
|
uint svr, pvr;
|
||||||
|
|
||||||
|
#ifndef CFG_RAMBOOT
|
||||||
|
ulong test1, test2;
|
||||||
|
|
||||||
|
/* setup SDRAM chip selects */
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG, 0x0000001c); /* 512MB at 0x0 */
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, 0x80000000);/* disabled */
|
||||||
|
__asm__ volatile ("sync");
|
||||||
|
|
||||||
|
/* setup config registers */
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
|
||||||
|
__asm__ volatile ("sync");
|
||||||
|
|
||||||
|
#if SDRAM_DDR
|
||||||
|
/* set tap delay */
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
|
||||||
|
__asm__ volatile ("sync");
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* find RAM size using SDRAM CS0 only */
|
||||||
|
sdram_start (0);
|
||||||
|
test1 = get_ram_size ((long *)CFG_SDRAM_BASE, 0x20000000);
|
||||||
|
sdram_start(1);
|
||||||
|
test2 = get_ram_size ((long *)CFG_SDRAM_BASE, 0x20000000);
|
||||||
|
if (test1 > test2) {
|
||||||
|
sdram_start (0);
|
||||||
|
dramsize = test1;
|
||||||
|
} else {
|
||||||
|
dramsize = test2;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* memory smaller than 1MB is impossible */
|
||||||
|
if (dramsize < (1 << 20)) {
|
||||||
|
dramsize = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* set SDRAM CS0 size according to the amount of RAM found */
|
||||||
|
if (dramsize > 0) {
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG,
|
||||||
|
(0x13 + __builtin_ffs(dramsize >> 20) - 1));
|
||||||
|
} else {
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
|
||||||
|
}
|
||||||
|
|
||||||
|
/* let SDRAM CS1 start right after CS0 */
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, (dramsize + 0x0000001c));/*512MB*/
|
||||||
|
|
||||||
|
/* find RAM size using SDRAM CS1 only */
|
||||||
|
if (!dramsize)
|
||||||
|
sdram_start (0);
|
||||||
|
test2 = test1 = get_ram_size ((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
|
||||||
|
if (!dramsize) {
|
||||||
|
sdram_start (1);
|
||||||
|
test2 = get_ram_size ((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
|
||||||
|
}
|
||||||
|
if (test1 > test2) {
|
||||||
|
sdram_start (0);
|
||||||
|
dramsize2 = test1;
|
||||||
|
} else {
|
||||||
|
dramsize2 = test2;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* memory smaller than 1MB is impossible */
|
||||||
|
if (dramsize2 < (1 << 20)) {
|
||||||
|
dramsize2 = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* set SDRAM CS1 size according to the amount of RAM found */
|
||||||
|
if (dramsize2 > 0) {
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG,
|
||||||
|
(dramsize | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
|
||||||
|
} else {
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
|
||||||
|
}
|
||||||
|
|
||||||
|
#else /* CFG_RAMBOOT */
|
||||||
|
|
||||||
|
/* retrieve size of memory connected to SDRAM CS0 */
|
||||||
|
dramsize = in_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
|
||||||
|
if (dramsize >= 0x13) {
|
||||||
|
dramsize = (1 << (dramsize - 0x13)) << 20;
|
||||||
|
} else {
|
||||||
|
dramsize = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* retrieve size of memory connected to SDRAM CS1 */
|
||||||
|
dramsize2 = in_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
|
||||||
|
if (dramsize2 >= 0x13) {
|
||||||
|
dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
|
||||||
|
} else {
|
||||||
|
dramsize2 = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* CFG_RAMBOOT */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* On MPC5200B we need to set the special configuration delay in the
|
||||||
|
* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
|
||||||
|
* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
|
||||||
|
*
|
||||||
|
* "The SDelay should be written to a value of 0x00000004. It is
|
||||||
|
* required to account for changes caused by normal wafer processing
|
||||||
|
* parameters."
|
||||||
|
*/
|
||||||
|
svr = get_svr();
|
||||||
|
pvr = get_pvr();
|
||||||
|
if ((SVR_MJREV(svr) >= 2) &&
|
||||||
|
(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
|
||||||
|
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_SDELAY, 0x04);
|
||||||
|
__asm__ volatile ("sync");
|
||||||
|
}
|
||||||
|
|
||||||
|
return dramsize + dramsize2;
|
||||||
|
}
|
||||||
|
|
||||||
|
int checkboard (void)
|
||||||
|
{
|
||||||
|
puts ("Board: MUC.MC-52 HW WDT ");
|
||||||
|
#if defined(CONFIG_HW_WATCHDOG)
|
||||||
|
puts ("enabled\n");
|
||||||
|
#else
|
||||||
|
puts ("disabled\n");
|
||||||
|
#endif
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_PREBOOT
|
||||||
|
|
||||||
|
static uchar kbd_magic_prefix[] = "key_magic";
|
||||||
|
static uchar kbd_command_prefix[] = "key_cmd";
|
||||||
|
|
||||||
|
#define S1_ROT 0xf0
|
||||||
|
#define S2_Q 0x40
|
||||||
|
#define S2_M 0x20
|
||||||
|
|
||||||
|
struct kbd_data_t {
|
||||||
|
char s1;
|
||||||
|
char s2;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
|
||||||
|
{
|
||||||
|
kbd_data->s1 = in_8 ((volatile uchar*)CFG_STATUS1_BASE);
|
||||||
|
kbd_data->s2 = in_8 ((volatile uchar*)CFG_STATUS2_BASE);
|
||||||
|
|
||||||
|
return kbd_data;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
|
||||||
|
{
|
||||||
|
char s1 = str[0];
|
||||||
|
char s2;
|
||||||
|
|
||||||
|
if (s1 >= '0' && s1 <= '9')
|
||||||
|
s1 -= '0';
|
||||||
|
else if (s1 >= 'a' && s1 <= 'f')
|
||||||
|
s1 = s1 - 'a' + 10;
|
||||||
|
else if (s1 >= 'A' && s1 <= 'F')
|
||||||
|
s1 = s1 - 'A' + 10;
|
||||||
|
else
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
if (((S1_ROT & kbd_data->s1) >> 4) != s1)
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
s2 = (S2_Q | S2_M) & kbd_data->s2;
|
||||||
|
|
||||||
|
switch (str[1]) {
|
||||||
|
case 'q':
|
||||||
|
case 'Q':
|
||||||
|
if (s2 == S2_Q)
|
||||||
|
return -1;
|
||||||
|
break;
|
||||||
|
case 'm':
|
||||||
|
case 'M':
|
||||||
|
if (s2 == S2_M)
|
||||||
|
return -1;
|
||||||
|
break;
|
||||||
|
case '\0':
|
||||||
|
if (s2 == (S2_Q | S2_M))
|
||||||
|
return 0;
|
||||||
|
default:
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (str[2])
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static char *key_match (const struct kbd_data_t *kbd_data)
|
||||||
|
{
|
||||||
|
char magic[sizeof (kbd_magic_prefix) + 1];
|
||||||
|
char *suffix;
|
||||||
|
char *kbd_magic_keys;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The following string defines the characters that can be appended
|
||||||
|
* to "key_magic" to form the names of environment variables that
|
||||||
|
* hold "magic" key codes, i. e. such key codes that can cause
|
||||||
|
* pre-boot actions. If the string is empty (""), then only
|
||||||
|
* "key_magic" is checked (old behaviour); the string "125" causes
|
||||||
|
* checks for "key_magic1", "key_magic2" and "key_magic5", etc.
|
||||||
|
*/
|
||||||
|
if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
|
||||||
|
kbd_magic_keys = "";
|
||||||
|
|
||||||
|
/* loop over all magic keys;
|
||||||
|
* use '\0' suffix in case of empty string
|
||||||
|
*/
|
||||||
|
for (suffix = kbd_magic_keys; *suffix ||
|
||||||
|
suffix == kbd_magic_keys; ++suffix) {
|
||||||
|
sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
|
||||||
|
|
||||||
|
if (compare_magic(kbd_data, getenv(magic)) == 0) {
|
||||||
|
char cmd_name[sizeof (kbd_command_prefix) + 1];
|
||||||
|
char *cmd;
|
||||||
|
|
||||||
|
sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
|
||||||
|
cmd = getenv (cmd_name);
|
||||||
|
|
||||||
|
return (cmd);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return (NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* CONFIG_PREBOOT */
|
||||||
|
|
||||||
|
int misc_init_r (void)
|
||||||
|
{
|
||||||
|
#ifdef CONFIG_PREBOOT
|
||||||
|
struct kbd_data_t kbd_data;
|
||||||
|
/* Decode keys */
|
||||||
|
char *str = strdup (key_match (get_keys (&kbd_data)));
|
||||||
|
/* Set or delete definition */
|
||||||
|
setenv ("preboot", str);
|
||||||
|
free (str);
|
||||||
|
#endif /* CONFIG_PREBOOT */
|
||||||
|
|
||||||
|
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x38), ' ');
|
||||||
|
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x39), ' ');
|
||||||
|
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3A), ' ');
|
||||||
|
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3B), ' ');
|
||||||
|
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3C), ' ');
|
||||||
|
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3D), ' ');
|
||||||
|
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3E), ' ');
|
||||||
|
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3F), ' ');
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_early_init_r (void)
|
||||||
|
{
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_CFG, in_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_CFG) & ~0x1);
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_START, START_REG(CFG_FLASH_BASE));
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_CS0_START, START_REG(CFG_FLASH_BASE));
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_STOP,
|
||||||
|
STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE));
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_CS0_STOP,
|
||||||
|
STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE));
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int last_stage_init (void)
|
||||||
|
{
|
||||||
|
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x38), 'M');
|
||||||
|
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x39), 'U');
|
||||||
|
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3A), 'C');
|
||||||
|
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3B), '.');
|
||||||
|
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3C), 'M');
|
||||||
|
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3D), 'C');
|
||||||
|
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3E), '5');
|
||||||
|
out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3F), '2');
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined(CONFIG_HW_WATCHDOG)
|
||||||
|
#define GPT_OUT_0 0x00000027
|
||||||
|
#define GPT_OUT_1 0x00000037
|
||||||
|
void hw_watchdog_reset (void)
|
||||||
|
{
|
||||||
|
/* Trigger HW Watchdog with TIMER_0 */
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_GPT0_ENABLE, GPT_OUT_1);
|
||||||
|
out_be32 ((unsigned __iomem *)MPC5XXX_GPT0_ENABLE, GPT_OUT_0);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_PCI
|
||||||
|
static struct pci_controller hose;
|
||||||
|
|
||||||
|
extern void pci_mpc5xxx_init (struct pci_controller *);
|
||||||
|
|
||||||
|
void pci_init_board (void)
|
||||||
|
{
|
||||||
|
pci_mpc5xxx_init (&hose);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
@ -474,8 +474,9 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
|
||||||
miiphy_write(dev->name, phyAddr, 0x0, 0x8000);
|
miiphy_write(dev->name, phyAddr, 0x0, 0x8000);
|
||||||
udelay(1000);
|
udelay(1000);
|
||||||
|
|
||||||
#if defined(CONFIG_UC101)
|
#if defined(CONFIG_UC101) || defined(CONFIG_MUCMC52)
|
||||||
/* Set the LED configuration Register for the UC101 Board */
|
/* Set the LED configuration Register for the UC101
|
||||||
|
and MUCMC52 Board */
|
||||||
miiphy_write(dev->name, phyAddr, 0x14, 0x4122);
|
miiphy_write(dev->name, phyAddr, 0x14, 0x4122);
|
||||||
#endif
|
#endif
|
||||||
if (fec->xcv_type == MII10) {
|
if (fec->xcv_type == MII10) {
|
||||||
|
|
@ -897,6 +898,7 @@ int mpc5xxx_fec_initialize(bd_t * bis)
|
||||||
defined(CONFIG_JUPITER) || \
|
defined(CONFIG_JUPITER) || \
|
||||||
defined(CONFIG_MCC200) || \
|
defined(CONFIG_MCC200) || \
|
||||||
defined(CONFIG_MOTIONPRO) || \
|
defined(CONFIG_MOTIONPRO) || \
|
||||||
|
defined(CONFIG_MUCMC52) || \
|
||||||
defined(CONFIG_O2DNT) || \
|
defined(CONFIG_O2DNT) || \
|
||||||
defined(CONFIG_PM520) || \
|
defined(CONFIG_PM520) || \
|
||||||
defined(CONFIG_TOP5200) || \
|
defined(CONFIG_TOP5200) || \
|
||||||
|
|
|
||||||
376
include/configs/mucmc52.h
Normal file
376
include/configs/mucmc52.h
Normal file
|
|
@ -0,0 +1,376 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2008
|
||||||
|
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||||
|
*
|
||||||
|
* (C) Copyright 2003-2005
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CONFIG_H
|
||||||
|
#define __CONFIG_H
|
||||||
|
|
||||||
|
/*
|
||||||
|
* High Level Configuration Options
|
||||||
|
* (easy to change)
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
|
||||||
|
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
|
||||||
|
#define CONFIG_MUCMC52 1 /* MUCMC52 board */
|
||||||
|
|
||||||
|
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
|
||||||
|
|
||||||
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||||
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||||
|
|
||||||
|
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
|
||||||
|
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||||
|
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CONFIG_BOARD_EARLY_INIT_R
|
||||||
|
|
||||||
|
#define CONFIG_LAST_STAGE_INIT
|
||||||
|
|
||||||
|
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
|
||||||
|
/*
|
||||||
|
* Serial console configuration
|
||||||
|
*/
|
||||||
|
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
|
||||||
|
#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
|
||||||
|
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
|
||||||
|
|
||||||
|
/* Partitions */
|
||||||
|
#define CONFIG_DOS_PARTITION
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Command line configuration.
|
||||||
|
*/
|
||||||
|
#include <config_cmd_default.h>
|
||||||
|
|
||||||
|
#define CONFIG_CMD_DATE
|
||||||
|
#define CONFIG_CMD_DISPLAY
|
||||||
|
#define CONFIG_CMD_DHCP
|
||||||
|
#define CONFIG_CMD_EEPROM
|
||||||
|
#define CONFIG_CMD_FAT
|
||||||
|
#define CONFIG_CMD_I2C
|
||||||
|
#define CONFIG_CMD_DTT
|
||||||
|
#define CONFIG_CMD_IDE
|
||||||
|
#define CONFIG_CMD_MII
|
||||||
|
#define CONFIG_CMD_NFS
|
||||||
|
#define CONFIG_CMD_PCI
|
||||||
|
#define CONFIG_CMD_PING
|
||||||
|
#define CONFIG_CMD_SNTP
|
||||||
|
|
||||||
|
#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
|
||||||
|
|
||||||
|
#if (TEXT_BASE == 0xFFF00000) /* Boot low */
|
||||||
|
# define CFG_LOWBOOT 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Autobooting
|
||||||
|
*/
|
||||||
|
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||||
|
|
||||||
|
#define CONFIG_PREBOOT "echo;" \
|
||||||
|
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||||
|
"echo"
|
||||||
|
|
||||||
|
#undef CONFIG_BOOTARGS
|
||||||
|
|
||||||
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
|
"netdev=eth0\0" \
|
||||||
|
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||||
|
"nfsroot=${serverip}:${rootpath}\0" \
|
||||||
|
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||||
|
"addip=setenv bootargs ${bootargs} " \
|
||||||
|
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||||
|
":${hostname}:${netdev}:off panic=1\0" \
|
||||||
|
"flash_nfs=run nfsargs addip;" \
|
||||||
|
"bootm ${kernel_addr}\0" \
|
||||||
|
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
|
||||||
|
"rootpath=/opt/eldk/ppc_82xx\0" \
|
||||||
|
""
|
||||||
|
|
||||||
|
#define CONFIG_BOOTCOMMAND "run net_nfs"
|
||||||
|
|
||||||
|
#define CONFIG_MISC_INIT_R 1
|
||||||
|
|
||||||
|
/*
|
||||||
|
* IPB Bus clocking configuration.
|
||||||
|
*/
|
||||||
|
#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* I2C configuration
|
||||||
|
*/
|
||||||
|
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||||
|
#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
|
||||||
|
|
||||||
|
#define CFG_I2C_SPEED 100000 /* 100 kHz */
|
||||||
|
#define CFG_I2C_SLAVE 0x7F
|
||||||
|
|
||||||
|
/*
|
||||||
|
* EEPROM configuration
|
||||||
|
*/
|
||||||
|
#define CFG_I2C_EEPROM_ADDR 0x58
|
||||||
|
#define CFG_I2C_EEPROM_ADDR_LEN 1
|
||||||
|
#define CFG_EEPROM_PAGE_WRITE_BITS 4
|
||||||
|
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
|
||||||
|
/* for LM81 */
|
||||||
|
#define CFG_EEPROM_PAGE_WRITE_ENABLE
|
||||||
|
|
||||||
|
/*
|
||||||
|
* RTC configuration
|
||||||
|
*/
|
||||||
|
#define CONFIG_RTC_PCF8563
|
||||||
|
#define CFG_I2C_RTC_ADDR 0x51
|
||||||
|
|
||||||
|
/* I2C SYSMON (LM75) */
|
||||||
|
#define CONFIG_DTT_LM81 1 /* ON Semi's LM75 */
|
||||||
|
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
|
||||||
|
#define CFG_DTT_MAX_TEMP 70
|
||||||
|
#define CFG_DTT_LOW_TEMP -30
|
||||||
|
#define CFG_DTT_HYSTERESIS 3
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Flash configuration
|
||||||
|
*/
|
||||||
|
#define CFG_FLASH_BASE 0xFF800000
|
||||||
|
|
||||||
|
#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
|
||||||
|
#define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */
|
||||||
|
|
||||||
|
#define CFG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */
|
||||||
|
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
|
||||||
|
(= chip selects) */
|
||||||
|
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
|
||||||
|
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
|
||||||
|
|
||||||
|
#define CONFIG_FLASH_CFI_DRIVER
|
||||||
|
#define CFG_FLASH_CFI
|
||||||
|
#define CFG_FLASH_EMPTY_INFO
|
||||||
|
#define CFG_FLASH_CFI_AMD_RESET
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Environment settings
|
||||||
|
*/
|
||||||
|
#define CFG_ENV_IS_IN_FLASH 1
|
||||||
|
#define CFG_ENV_SIZE 0x4000
|
||||||
|
#define CFG_ENV_SECT_SIZE 0x20000
|
||||||
|
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
|
||||||
|
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Memory map
|
||||||
|
*/
|
||||||
|
#define CFG_MBAR 0xF0000000
|
||||||
|
#define CFG_SDRAM_BASE 0x00000000
|
||||||
|
#define CFG_DEFAULT_MBAR 0x80000000
|
||||||
|
#define CFG_DISPLAY_BASE 0x80600000
|
||||||
|
#define CFG_STATUS1_BASE 0x80600200
|
||||||
|
#define CFG_STATUS2_BASE 0x80600300
|
||||||
|
#define CFG_PMI_UNI_BASE 0x80800000
|
||||||
|
#define CFG_PMI_BROAD_BASE 0x80810000
|
||||||
|
|
||||||
|
/* Settings for XLB = 132 MHz */
|
||||||
|
#define SDRAM_DDR 1
|
||||||
|
#define SDRAM_MODE 0x018D0000
|
||||||
|
#define SDRAM_EMODE 0x40090000
|
||||||
|
#define SDRAM_CONTROL 0x714f0f00
|
||||||
|
#define SDRAM_CONFIG1 0x73722930
|
||||||
|
#define SDRAM_CONFIG2 0x47770000
|
||||||
|
#define SDRAM_TAPDELAY 0x10000000
|
||||||
|
|
||||||
|
/* Use ON-Chip SRAM until RAM will be available */
|
||||||
|
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
|
||||||
|
#ifdef CONFIG_POST
|
||||||
|
/* preserve space for the post_word at end of on-chip SRAM */
|
||||||
|
#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
|
||||||
|
#else
|
||||||
|
#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||||
|
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||||
|
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||||
|
|
||||||
|
#define CFG_MONITOR_BASE TEXT_BASE
|
||||||
|
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
|
||||||
|
# define CFG_RAMBOOT 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
|
||||||
|
#define CFG_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */
|
||||||
|
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Ethernet configuration
|
||||||
|
*/
|
||||||
|
#define CONFIG_MPC5xxx_FEC 1
|
||||||
|
#define CONFIG_PHY_ADDR 0x00
|
||||||
|
#define CONFIG_MII 1 /* MII PHY management */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GPIO configuration
|
||||||
|
*/
|
||||||
|
#define CFG_GPS_PORT_CONFIG 0x8D550644
|
||||||
|
|
||||||
|
/*use Hardware WDT */
|
||||||
|
#define CONFIG_HW_WATCHDOG
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Miscellaneous configurable options
|
||||||
|
*/
|
||||||
|
#define CFG_LONGHELP /* undef to save memory */
|
||||||
|
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||||
|
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||||
|
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||||
|
#else
|
||||||
|
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||||
|
#endif
|
||||||
|
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||||
|
#define CFG_MAXARGS 16 /* max number of command args */
|
||||||
|
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||||
|
|
||||||
|
/* Enable an alternate, more extensive memory test */
|
||||||
|
#define CFG_ALT_MEMTEST
|
||||||
|
|
||||||
|
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
|
||||||
|
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
|
||||||
|
|
||||||
|
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||||
|
|
||||||
|
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
|
||||||
|
* which is normally part of the default commands (CFV_CMD_DFL)
|
||||||
|
*/
|
||||||
|
#define CONFIG_LOOPW
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Various low-level settings
|
||||||
|
*/
|
||||||
|
#if defined(CONFIG_MPC5200)
|
||||||
|
#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
|
||||||
|
#define CFG_HID0_FINAL HID0_ICE
|
||||||
|
#else
|
||||||
|
#define CFG_HID0_INIT 0
|
||||||
|
#define CFG_HID0_FINAL 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CFG_BOOTCS_START CFG_FLASH_BASE
|
||||||
|
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
|
||||||
|
#define CFG_BOOTCS_CFG 0x0004FB00
|
||||||
|
#define CFG_CS0_START CFG_FLASH_BASE
|
||||||
|
#define CFG_CS0_SIZE CFG_FLASH_SIZE
|
||||||
|
|
||||||
|
/* 8Mbit SRAM @0x80100000 */
|
||||||
|
#define CFG_CS1_START 0x80100000
|
||||||
|
#define CFG_CS1_SIZE 0x00100000
|
||||||
|
#define CFG_CS1_CFG 0x00019B00
|
||||||
|
|
||||||
|
/* FRAM 32Kbyte @0x80700000 */
|
||||||
|
#define CFG_CS2_START 0x80700000
|
||||||
|
#define CFG_CS2_SIZE 0x00008000
|
||||||
|
#define CFG_CS2_CFG 0x00019800
|
||||||
|
|
||||||
|
/* Display H1, Status Inputs, EPLD @0x80600000 */
|
||||||
|
#define CFG_CS3_START 0x80600000
|
||||||
|
#define CFG_CS3_SIZE 0x00100000
|
||||||
|
#define CFG_CS3_CFG 0x00019800
|
||||||
|
|
||||||
|
/* PMI Unicast 32Kbyte @0x80800000 */
|
||||||
|
#define CFG_CS6_START CFG_PMI_UNI_BASE
|
||||||
|
#define CFG_CS6_SIZE 0x00008000
|
||||||
|
#define CFG_CS6_CFG 0xFFFFF930
|
||||||
|
|
||||||
|
/* PMI Broadcast 32Kbyte @0x80810000 */
|
||||||
|
#define CFG_CS7_START CFG_PMI_BROAD_BASE
|
||||||
|
#define CFG_CS7_SIZE 0x00008000
|
||||||
|
#define CFG_CS7_CFG 0xFF00F930
|
||||||
|
|
||||||
|
#define CFG_CS_BURST 0x00000000
|
||||||
|
#define CFG_CS_DEADCYCLE 0x33333333
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* IDE/ATA stuff Supports IDE harddisk
|
||||||
|
*-----------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
|
||||||
|
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
|
||||||
|
|
||||||
|
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
|
||||||
|
#undef CONFIG_IDE_LED /* LED for ide not supported */
|
||||||
|
|
||||||
|
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
|
||||||
|
#define CFG_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
|
||||||
|
|
||||||
|
#define CONFIG_IDE_PREINIT 1
|
||||||
|
|
||||||
|
#define CFG_ATA_IDE0_OFFSET 0x0000
|
||||||
|
|
||||||
|
#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
|
||||||
|
|
||||||
|
/* Offset for data I/O */
|
||||||
|
#define CFG_ATA_DATA_OFFSET (0x0060)
|
||||||
|
|
||||||
|
/* Offset for normal register accesses */
|
||||||
|
#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
|
||||||
|
|
||||||
|
/* Offset for alternate registers */
|
||||||
|
#define CFG_ATA_ALT_OFFSET (0x005C)
|
||||||
|
|
||||||
|
/* Interval between registers */
|
||||||
|
#define CFG_ATA_STRIDE 4
|
||||||
|
|
||||||
|
#define CONFIG_ATAPI 1
|
||||||
|
|
||||||
|
/*
|
||||||
|
* PCI Mapping:
|
||||||
|
* 0x40000000 - 0x4fffffff - PCI Memory
|
||||||
|
* 0x50000000 - 0x50ffffff - PCI IO Space
|
||||||
|
*/
|
||||||
|
#define CONFIG_PCI 1
|
||||||
|
#define CONFIG_PCI_PNP 1
|
||||||
|
#define CONFIG_PCI_SCAN_SHOW 1
|
||||||
|
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
|
||||||
|
|
||||||
|
#define CONFIG_PCI_MEM_BUS 0x40000000
|
||||||
|
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
|
||||||
|
#define CONFIG_PCI_MEM_SIZE 0x10000000
|
||||||
|
|
||||||
|
#define CONFIG_PCI_IO_BUS 0x50000000
|
||||||
|
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
|
||||||
|
#define CONFIG_PCI_IO_SIZE 0x01000000
|
||||||
|
|
||||||
|
#define CFG_ISA_IO CONFIG_PCI_IO_BUS
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------*/
|
||||||
|
/* Display addresses */
|
||||||
|
/*---------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
#define CFG_DISP_CHR_RAM (CFG_DISPLAY_BASE + 0x38)
|
||||||
|
#define CFG_DISP_CWORD (CFG_DISPLAY_BASE + 0x30)
|
||||||
|
|
||||||
|
#endif /* __CONFIG_H */
|
||||||
Loading…
Add table
Reference in a new issue