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Merge branch 'master' of git://git.denx.de/u-boot-samsung

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This commit is contained in:
Tom Rini 2015-04-06 06:57:15 -04:00
commit 3419af770d
16 changed files with 193 additions and 28 deletions
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69
arch/arm/cpu/armv7/exynos/clock.c
View file

@ -14,7 +14,6 @@
#define PLL_DIV_1024 1024
#define PLL_DIV_65535 65535
#define PLL_DIV_65536 65536
/* *
* This structure is to store the src bit, div bit and prediv bit
* positions of the peripheral clocks of the src and div registers
@ -423,8 +422,8 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
case PERIPH_ID_I2C6:
case PERIPH_ID_I2C7:
src = EXYNOS_SRC_MPLL;
div = readl(&clk->div_top0);
sub_div = readl(&clk->div_top1);
div = readl(&clk->div_top1);
sub_div = readl(&clk->div_top0);
break;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
@ -1028,6 +1027,40 @@ static unsigned long exynos5420_get_lcd_clk(void)
return pclk;
}
static unsigned long exynos5800_get_lcd_clk(void)
{
struct exynos5420_clock *clk =
(struct exynos5420_clock *)samsung_get_base_clock();
unsigned long sclk;
unsigned int sel;
unsigned int ratio;
/*
* CLK_SRC_DISP10
* CLKMUX_FIMD1 [6:4]
*/
sel = (readl(&clk->src_disp10) >> 4) & 0x7;
if (sel) {
/*
* Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into
* PLLs. The first element is a placeholder to bypass the
* default settig.
*/
const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL,
RPLL};
sclk = get_pll_clk(reg_map[sel]);
} else
sclk = CONFIG_SYS_CLK_FREQ;
/*
* CLK_DIV_DISP10
* FIMD1_RATIO [3:0]
*/
ratio = readl(&clk->div_disp10) & 0xf;
return sclk / (ratio + 1);
}
void exynos4_set_lcd_clk(void)
{
struct exynos4_clock *clk =
@ -1159,6 +1192,28 @@ void exynos5420_set_lcd_clk(void)
writel(cfg, &clk->div_disp10);
}
void exynos5800_set_lcd_clk(void)
{
struct exynos5420_clock *clk =
(struct exynos5420_clock *)samsung_get_base_clock();
unsigned int cfg;
/*
* Use RPLL for pixel clock
* CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4]
* ==================
* 111: SCLK_RPLL
*/
cfg = readl(&clk->src_disp10) | (0x7 << 4);
writel(cfg, &clk->src_disp10);
/*
* CLK_DIV_DISP10
* FIMD1_RATIO [3:0]
*/
clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0);
}
void exynos4_set_mipi_clk(void)
{
struct exynos4_clock *clk =
@ -1646,8 +1701,10 @@ unsigned long get_lcd_clk(void)
if (cpu_is_exynos4())
return exynos4_get_lcd_clk();
else {
if (proid_is_exynos5420() || proid_is_exynos5800())
if (proid_is_exynos5420())
return exynos5420_get_lcd_clk();
else if (proid_is_exynos5800())
return exynos5800_get_lcd_clk();
else
return exynos5_get_lcd_clk();
}
@ -1660,8 +1717,10 @@ void set_lcd_clk(void)
else {
if (proid_is_exynos5250())
exynos5_set_lcd_clk();
else if (proid_is_exynos5420() || proid_is_exynos5800())
else if (proid_is_exynos5420())
exynos5420_set_lcd_clk();
else
exynos5800_set_lcd_clk();
}
}

4
arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
View file

@ -179,10 +179,10 @@ struct mem_timings mem_timings[] = {
.spll_mdiv = 0xc8,
.spll_pdiv = 0x3,
.spll_sdiv = 0x2,
/* RPLL @70.5Mhz */
/* RPLL @141Mhz */
.rpll_mdiv = 0x5E,
.rpll_pdiv = 0x2,
.rpll_sdiv = 0x4,
.rpll_sdiv = 0x3,
.direct_cmd_msr = {
0x00020018, 0x00030000, 0x00010046, 0x00000d70,

2
arch/arm/dts/exynos5420-peach-pit.dts
View file

@ -67,6 +67,8 @@
edp-lvds-bridge@48 {
compatible = "parade,ps8625";
reg = <0x48>;
sleep-gpio = <&gpx3 5 GPIO_ACTIVE_HIGH>;
reset-gpio = <&gpy7 7 GPIO_ACTIVE_HIGH>;
};
};

1
arch/arm/dts/exynos54xx.dtsi
View file

@ -168,6 +168,7 @@
fimd@14400000 {
/* sysmmu is not used in U-Boot */
samsung,disable-sysmmu;
samsung,pwm-out-gpio = <&gpb2 0 GPIO_ACTIVE_HIGH>;
};
dp@145b0000 {

3
arch/arm/dts/exynos5800-peach-pi.dts
View file

@ -144,10 +144,13 @@
samsung,vl-vfpd = <10>;
samsung,vl-cmd-allow-len = <0xf>;
samsung,power-on-delay = <30000>;
samsung,winid = <3>;
samsung,interface-mode = <1>;
samsung,dp-enabled = <1>;
samsung,dual-lcd-enabled = <0>;
samsung,bl-en-gpio = <&gpx2 2 GPIO_ACTIVE_HIGH>;
};
};

3
arch/arm/include/asm/arch-exynos/clk.h
View file

@ -16,6 +16,9 @@
#define BPLL 5
#define RPLL 6
#define SPLL 7
#define CPLL 8
#define DPLL 9
#define IPLL 10
#define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8))
#define MASK_RATIO(x) (0xf << (x << 4))

15
board/samsung/smdk5420/smdk5420.c
View file

@ -58,16 +58,6 @@ void exynos_lcd_power_on(void)
mdelay(5);
/* TODO(ajaykumar.rs@samsung.com): Use device tree */
gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#");
gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */
mdelay(10);
gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#");
gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */
gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");
gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */
gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
if (has_edp_bridge())
if (parade_init(gd->fdt_blob))
printf("%s: ps8625_init() failed\n", __func__);
@ -75,11 +65,6 @@ void exynos_lcd_power_on(void)
void exynos_backlight_on(unsigned int onoff)
{
/* For PWM */
gpio_request(EXYNOS5420_GPIO_B20, "backlight_on");
gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(0x1));
gpio_set_value(EXYNOS5420_GPIO_B20, 1);
#ifdef CONFIG_POWER_TPS65090
tps65090_fet_enable(1);
#endif

2
doc/device-tree-bindings/video/exynos-fb.txt
View file

@ -61,6 +61,8 @@ Board(panel specific):
disabled with compatible string
"samsung,sysmmu-v3.3", with a "reg" property
holding the register address of FIMD sysmmu.
samsung,pwm-out-gpio: PWM output GPIO.
samsung,bl-en-gpio: backlight enable GPIO.
Example:
SOC specific part:

21
drivers/video/exynos_fb.c
View file

@ -19,6 +19,7 @@
#include <asm/arch/mipi_dsim.h>
#include <asm/arch/dp_info.h>
#include <asm/arch/system.h>
#include <asm/gpio.h>
#include <asm-generic/errno.h>
#include "exynos_fb.h"
@ -102,6 +103,10 @@ __weak int exynos_lcd_misc_init(vidinfo_t *vid)
static void lcd_panel_on(vidinfo_t *vid)
{
struct gpio_desc pwm_out_gpio;
struct gpio_desc bl_en_gpio;
unsigned int node;
udelay(vid->init_delay);
exynos_backlight_reset();
@ -121,6 +126,22 @@ static void lcd_panel_on(vidinfo_t *vid)
exynos_backlight_on(1);
#ifdef CONFIG_OF_CONTROL
node = fdtdec_next_compatible(gd->fdt_blob, 0,
COMPAT_SAMSUNG_EXYNOS_FIMD);
if (node <= 0) {
debug("FIMD: Can't get device node for FIMD\n");
return;
}
gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,pwm-out-gpio",
0, &pwm_out_gpio,
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,bl-en-gpio", 0,
&bl_en_gpio,
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
#endif
exynos_cfg_ldo();
exynos_enable_ldo(1);

11
drivers/video/parade.c
View file

@ -12,6 +12,7 @@
#include <common.h>
#include <i2c.h>
#include <fdtdec.h>
#include <asm/gpio.h>
/*
* Initialization of the chip is a process of writing certaing values into
@ -180,6 +181,8 @@ static int parade_write_regs(int base_addr, const struct reg_data *table)
int parade_init(const void *blob)
{
struct gpio_desc rst_gpio;
struct gpio_desc slp_gpio;
int bus, old_bus;
int parent;
int node;
@ -201,6 +204,14 @@ int parade_init(const void *blob)
return -1;
}
gpio_request_by_name_nodev(blob, node, "sleep-gpio", 0, &slp_gpio,
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
mdelay(10);
gpio_request_by_name_nodev(blob, node, "reset-gpio", 0, &rst_gpio,
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
bus = i2c_get_bus_num_fdt(parent);
old_bus = i2c_get_bus_num();

54
include/configs/exynos4-common.h
View file

@ -66,4 +66,58 @@
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_GADGET_MASS_STORAGE
/* Common environment variables */
#define CONFIG_EXTRA_ENV_ITB \
"loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \
"${kernelname}\0" \
"loadinitrd=load mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} " \
"${initrdname}\0" \
"loaddtb=load mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} " \
"${fdtfile}\0" \
"check_ramdisk=" \
"if run loadinitrd; then " \
"setenv initrd_addr ${initrdaddr};" \
"else " \
"setenv initrd_addr -;" \
"fi;\0" \
"check_dtb=" \
"if run loaddtb; then " \
"setenv fdt_addr ${fdtaddr};" \
"else " \
"setenv fdt_addr;" \
"fi;\0" \
"kernel_args=" \
"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart}" \
" ${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};\0" \
"boot_fit=" \
"setenv kerneladdr 0x42000000;" \
"setenv kernelname Image.itb;" \
"run loadkernel;" \
"run kernel_args;" \
"bootm ${kerneladdr}#${board_name}\0" \
"boot_uimg=" \
"setenv kerneladdr 0x40007FC0;" \
"setenv kernelname uImage;" \
"run check_dtb;" \
"run check_ramdisk;" \
"run loadkernel;" \
"run kernel_args;" \
"bootm ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \
"boot_zimg=" \
"setenv kerneladdr 0x40007FC0;" \
"setenv kernelname zImage;" \
"run check_dtb;" \
"run check_ramdisk;" \
"run loadkernel;" \
"run kernel_args;" \
"bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \
"autoboot=" \
"if test -e mmc ${mmcdev}:${mmcbootpart} Image.itb; then; " \
"run boot_fit;" \
"elif test -e mmc ${mmcdev}:${mmcbootpart} zImage; then; " \
"run boot_zimg;" \
"elif test -e mmc ${mmcdev}:${mmcbootpart} uImage; then; " \
"run boot_uimg;" \
"fi;\0"
#endif /* __CONFIG_EXYNOS4_COMMON_H */

4
include/configs/exynos5-common.h
View file

@ -16,14 +16,14 @@
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_EXYNOS_SPL
/* Allow tracing to be enabled */
#ifdef FTRACE
#define CONFIG_TRACE
#define CONFIG_CMD_TRACE
#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
#define CONFIG_TRACE_EARLY
#define CONFIG_TRACE_EARLY_ADDR 0x50000000
#endif
/* Enable ACE acceleration for SHA1 and SHA256 */
#define CONFIG_EXYNOS_ACE_SHA

8
include/configs/peach-pi.h
View file

@ -16,6 +16,14 @@
#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
#define CONFIG_SPI_BOOTING
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
"kernel_addr_r=0x22000000\0" \
"fdt_addr_r=0x23000000\0" \
"ramdisk_addr_r=0x23300000\0" \
"scriptaddr=0x30000000\0" \
"pxefile_addr_r=0x31000000\0"
#include <configs/exynos5420-common.h>
#include <configs/exynos5-dt-common.h>

8
include/configs/peach-pit.h
View file

@ -16,6 +16,14 @@
#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
#define CONFIG_SPI_BOOTING
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
"kernel_addr_r=0x22000000\0" \
"fdt_addr_r=0x23000000\0" \
"ramdisk_addr_r=0x23300000\0" \
"scriptaddr=0x30000000\0" \
"pxefile_addr_r=0x31000000\0"
#include <configs/exynos5420-common.h>
#include <configs/exynos5-dt-common.h>

8
include/configs/trats.h
View file

@ -51,8 +51,10 @@
#define MACH_TYPE_TRATS 3928
#define CONFIG_MACH_TYPE MACH_TYPE_TRATS
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE
#define CONFIG_BOOTARGS "Please use defined boot"
#define CONFIG_BOOTCOMMAND "run mmcboot"
#define CONFIG_BOOTCOMMAND "run autoboot"
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
@ -106,7 +108,8 @@
""PARTS_ROOT" part 0 5;" \
""PARTS_DATA" part 0 6;" \
""PARTS_UMS" part 0 7;" \
"params.bin raw 0x38 0x8\0"
"params.bin raw 0x38 0x8;" \
"/Image.itb ext4 0 2\0"
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootk=" \
@ -172,6 +175,7 @@
"setenv spl_imgsize;" \
"setenv spl_imgaddr;" \
"setenv spl_addr_tmp;\0" \
CONFIG_EXTRA_ENV_ITB \
"fdtaddr=40800000\0" \
/* Falcon mode definitions */

8
include/configs/trats2.h
View file

@ -44,8 +44,10 @@
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE
#define CONFIG_BOOTARGS "Please use defined boot"
#define CONFIG_BOOTCOMMAND "run mmcboot"
#define CONFIG_BOOTCOMMAND "run autoboot"
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
@ -96,7 +98,8 @@
""PARTS_ROOT" part 0 5;" \
""PARTS_DATA" part 0 6;" \
""PARTS_UMS" part 0 7;" \
"params.bin raw 0x38 0x8\0"
"params.bin raw 0x38 0x8;" \
"/Image.itb ext4 0 2\0"
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootk=" \
@ -153,6 +156,7 @@
"setenv spl_imgsize;" \
"setenv spl_imgaddr;" \
"setenv spl_addr_tmp;\0" \
CONFIG_EXTRA_ENV_ITB \
"fdtaddr=40800000\0" \
/* GPT */