Improvements and new features:

- improved SPI driver for better read throughput
 - refactors initialisation of debug UART init
 - restructures header file paths
 - adds pinctrl improvements
 
 Adds Kever as a co-custodian.
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Merge tag 'rockchip-for-2019.07' of git://git.denx.de/u-boot-rockchip

Improvements and new features:
- improved SPI driver for better read throughput
- refactors initialisation of debug UART init
- restructures header file paths
- adds pinctrl improvements

Adds Kever as a co-custodian.

MAINTAINERS

@@ -239,6 +239,7 @@ F:	arch/arm/mach-rmobile/
 ARM ROCKCHIP
 M:	Simon Glass <sjg@chromium.org>
 M:	Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+M:	Kever Yang <kever.yang@rock-chips.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-rockchip.git
 F:	arch/arm/include/asm/arch-rockchip/

arch/arm/Kconfig

@@ -1439,6 +1439,7 @@ config ARCH_ROCKCHIP
 	select SYS_THUMB_BUILD if !ARM64
 	imply ADC
 	imply CMD_DM
+	imply DEBUG_UART_BOARD_INIT
 	imply DISTRO_DEFAULTS
 	imply FAT_WRITE
 	imply SARADC_ROCKCHIP

arch/arm/cpu/armv8/start.S

@@ -26,7 +26,11 @@ _start:
  * order to boot, allow them to set that in their boot0.h file and then
  * use it here.
  */
+#ifdef CONFIG_ARCH_ROCKCHIP
+#include <asm/arch-rockchip/boot0.h>
+#else
 #include <asm/arch/boot0.h>
+#endif
 #else
 	b	reset
 #endif

arch/arm/dts/Makefile

@@ -74,6 +74,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rk3288-fennec.dtb \
 	rk3288-firefly.dtb \
 	rk3288-miqi.dtb \
+	rk3399-orangepi.dtb \
 	rk3288-phycore-rdk.dtb \
 	rk3288-popmetal.dtb \
 	rk3288-rock2-square.dtb \

arch/arm/dts/rk3399-evb.dts

@@ -155,7 +155,6 @@
 };
 
 &sdmmc {
-	u-boot,dm-pre-reloc;
 	bus-width = <4>;
 	status = "okay";
 };

arch/arm/dts/rk3399-firefly.dts

@@ -592,7 +592,6 @@
 };
 
 &sdmmc {
-	u-boot,dm-pre-reloc;
 	bus-width = <4>;
 	status = "okay";
 };

arch/arm/dts/rk3399-opp.dtsi

@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+/ {
+	cluster0_opp: opp-table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <408000000>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <40000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <800000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <850000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <1008000000>;
+			opp-microvolt = <925000>;
+		};
+		opp04 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1000000>;
+		};
+		opp05 {
+			opp-hz = /bits/ 64 <1416000000>;
+			opp-microvolt = <1125000>;
+		};
+	};
+
+	cluster1_opp: opp-table1 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <408000000>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <40000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <800000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <825000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <1008000000>;
+			opp-microvolt = <875000>;
+		};
+		opp04 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <950000>;
+		};
+		opp05 {
+			opp-hz = /bits/ 64 <1416000000>;
+			opp-microvolt = <1025000>;
+		};
+		opp06 {
+			opp-hz = /bits/ 64 <1608000000>;
+			opp-microvolt = <1100000>;
+		};
+		opp07 {
+			opp-hz = /bits/ 64 <1800000000>;
+			opp-microvolt = <1200000>;
+		};
+	};
+
+	gpu_opp_table: opp-table2 {
+		compatible = "operating-points-v2";
+
+		opp00 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <800000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <297000000>;
+			opp-microvolt = <800000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <825000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <875000>;
+		};
+		opp04 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <925000>;
+		};
+		opp05 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <1100000>;
+		};
+	};
+};
+
+&cpu_l0 {
+	operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_l1 {
+	operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_l2 {
+	operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_l3 {
+	operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_b0 {
+	operating-points-v2 = <&cluster1_opp>;
+};
+
+&cpu_b1 {
+	operating-points-v2 = <&cluster1_opp>;
+};
+
+&gpu {
+	operating-points-v2 = <&gpu_opp_table>;
+};

arch/arm/dts/rk3399-orangepi-u-boot.dtsi

@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-ddr3-1333.dtsi"

arch/arm/dts/rk3399-orangepi.dts

@@ -0,0 +1,771 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include "dt-bindings/pwm/pwm.h"
+#include "dt-bindings/input/input.h"
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+	model = "Orange Pi RK3399 Board";
+	compatible = "rockchip,rk3399-orangepi", "rockchip,rk3399";
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		button-up {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			press-threshold-microvolt = <100000>;
+		};
+
+		button-down {
+			label = "Volume Down";
+			linux,code = <KEY_VOLUMEDOWN>;
+			press-threshold-microvolt = <300000>;
+		};
+
+		back {
+			label = "Back";
+			linux,code = <KEY_BACK>;
+			press-threshold-microvolt = <985000>;
+		};
+
+		menu {
+			label = "Menu";
+			linux,code = <KEY_MENU>;
+			press-threshold-microvolt = <1314000>;
+		};
+	};
+
+	dc_12v: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	keys: gpio-keys {
+		compatible = "gpio-keys";
+		autorepeat;
+
+		power {
+			debounce-interval = <100>;
+			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+			label = "GPIO Power";
+			linux,code = <KEY_POWER>;
+			linux,input-type = <1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pwr_btn>;
+			wakeup-source;
+		};
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_reg_on_h>;
+		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+	};
+
+	/* switched by pmic_sleep */
+	vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_1v8>;
+	};
+
+	vcc3v0_sd: vcc3v0-sd {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc0_pwr_h>;
+		regulator-boot-on;
+		regulator-max-microvolt = <3000000>;
+		regulator-min-microvolt = <3000000>;
+		regulator-name = "vcc3v0_sd";
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+		regulator-name = "vcc5v0_host";
+		regulator-always-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vcc5v0_typec0: vcc5v0-typec0-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_typec0_en>;
+		regulator-name = "vcc5v0_typec0";
+		vin-supply = <&vcc_sys>;
+	};
+
+	vcc_sys: vcc-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vdd_log: vdd-log {
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		regulator-name = "vdd_log";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+		vin-supply = <&vcc_sys>;
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	clock_in_out = "input";
+	phy-supply = <&vcc3v3_s3>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 50000>;
+	tx_delay = <0x28>;
+	rx_delay = <0x11>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c3>;
+	status = "okay";
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <168>;
+	i2c-scl-falling-time-ns = <4>;
+	status = "okay";
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "rtc_clko_soc", "rtc_clko_wifi";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		vcc10-supply = <&vcc3v3_sys>;
+		vcc11-supply = <&vcc3v3_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_3v0>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_dvp: LDO_REG1 {
+				regulator-name = "vcc1v8_dvp";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v0_tp: LDO_REG2 {
+				regulator-name = "vcc3v0_tp";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc1v8_pmupll: LDO_REG3 {
+				regulator-name = "vcc1v8_pmupll";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <2500000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sdio: LDO_REG4 {
+				regulator-name = "vcc_sdio";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcca3v0_codec: LDO_REG5 {
+				regulator-name = "vcca3v0_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-name = "vcc_1v5";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <2500000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcca1v8_codec: LDO_REG7 {
+				regulator-name = "vcca1v8_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <2500000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-name = "vcc_3v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: SWITCH_REG1 {
+				regulator-name = "vcc3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-name = "vcc3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+
+	vdd_cpu_b: regulator@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc3v3_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: regulator@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc3v3_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c1 {
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+&i2c3 {
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+
+	ak09911@c {
+		compatible = "asahi-kasei,ak09911";
+		reg = <0x0c>;
+		vdd-supply = <&vcc3v3_s3>;
+	};
+
+	mpu6500@68 {
+		compatible = "invensense,mpu6500";
+		reg = <0x68>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PC6 IRQ_TYPE_EDGE_RISING>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&gsensor_int_l>;
+		vddio-supply = <&vcc3v3_s3>;
+	};
+
+	lsm6ds3@6a {
+		compatible = "st,lsm6ds3";
+		reg = <0x6a>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PD0 IRQ_TYPE_EDGE_RISING>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&gyr_int_l>;
+		vdd-supply = <&vcc3v3_s3>;
+		vddio-supply = <&vcc3v3_s3>;
+	};
+
+	cm32181@10 {
+		compatible = "capella,cm32181";
+		reg = <0x10>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <RK_PD0 IRQ_TYPE_EDGE_RISING>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&light_int_l>;
+		vdd-supply = <&vcc3v3_s3>;
+	};
+};
+
+&io_domains {
+	status = "okay";
+	bt656-supply = <&vcc_3v0>;
+	audio-supply = <&vcca1v8_codec>;
+	sdmmc-supply = <&vcc_sdio>;
+	gpio1830-supply = <&vcc_3v0>;
+};
+
+&pmu_io_domains {
+	status = "okay";
+	pmu1830-supply = <&vcc_3v0>;
+};
+
+&pinctrl {
+	buttons {
+		pwr_btn: pwr-btn {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins =
+				<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sd {
+		sdmmc0_pwr_h: sdmmc0-pwr-h {
+			rockchip,pins =
+				<RK_GPIO0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb2 {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins =
+				<4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_typec0_en: vcc5v0-typec0-en {
+			rockchip,pins =
+				<1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_reg_on_h: wifi-reg-on-h {
+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	wifi {
+		wifi_host_wake_l: wifi-host-wake-l {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	bluetooth {
+		bt_reg_on_h: bt-enable-h {
+			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_host_wake_l: bt-host-wake-l {
+			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_wake_l: bt-wake-l {
+			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	mpu6500 {
+		gsensor_int_l: gsensor-int-l {
+			rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	lsm6ds3 {
+		gyr_int_l: gyr-int-l {
+			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	cm32181 {
+		light_int_l: light-int-l {
+			rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca1v8_s3>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	non-removable;
+	status = "okay";
+};
+
+&sdio0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	clock-frequency = <50000000>;
+	disable-wp;
+	keep-power-in-suspend;
+	max-frequency = <50000000>;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+	sd-uhs-sdr104;
+	status = "okay";
+
+	brcmf: wifi@1 {
+		compatible = "brcm,bcm4329-fmac";
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
+		interrupt-names = "host-wake";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_host_wake_l>;
+	};
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+	clock-frequency = <150000000>;
+	disable-wp;
+	max-frequency = <150000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+	vmmc-supply = <&vcc3v0_sd>;
+	vqmmc-supply = <&vcc_sdio>;
+	status = "okay";
+};
+
+&tcphy0 {
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <1>;
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+
+	u2phy0_otg: otg-port {
+		phy-supply = <&vcc5v0_typec0>;
+		status = "okay";
+	};
+
+	u2phy0_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy1_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>;
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	status = "okay";
+	dr_mode = "otg";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};

arch/arm/dts/rk3399-puma.dtsi

@@ -492,7 +492,6 @@
 };
 
 &sdmmc {
-	u-boot,dm-pre-reloc;
 	clock-frequency = <150000000>;
 	max-frequency = <40000000>;
 	supports-sd;

arch/arm/dts/rk3399-u-boot.dtsi

@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+&sdmmc {
+	u-boot,dm-pre-reloc;
+};

arch/arm/include/asm/arch-rockchip/ddr_rk3188.h

@@ -6,7 +6,7 @@
 #ifndef _ASM_ARCH_DDR_RK3188_H
 #define _ASM_ARCH_DDR_RK3188_H
 
-#include <asm/arch/ddr_rk3288.h>
+#include <asm/arch-rockchip/ddr_rk3288.h>
 
 /*
  * RK3188 Memory scheduler register map.

arch/arm/include/asm/arch-rockchip/hardware.h

@@ -10,8 +10,6 @@
 #define RK_SETBITS(set)			RK_CLRSETBITS(0, set)
 #define RK_CLRBITS(clr)			RK_CLRSETBITS(clr, 0)
 
-#define TIMER7_BASE		0xff810020
-
 #define rk_clrsetreg(addr, clr, set)	\
 				writel(((clr) | (set)) << 16 | (set), addr)
 #define rk_clrreg(addr, clr)		writel((clr) << 16, addr)

arch/arm/include/asm/gpio.h

@@ -1,6 +1,6 @@
 #if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \
 	!defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM6858) && \
-	!defined(CONFIG_ARCH_BCM63158)
+	!defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP)
 #include <asm/arch/gpio.h>
 #endif
 #include <asm-generic/gpio.h>

arch/arm/lib/vectors.S

@@ -67,8 +67,11 @@
  *   (1) defines '_start:' as appropriate
  *   (2) inserts the vector table using ARM_VECTORS as appropriate
  */
+#ifdef CONFIG_ARCH_ROCKCHIP
+#include <asm/arch-rockchip/boot0.h>
+#else
 #include <asm/arch/boot0.h>
-
+#endif
 #else
 
 /*

arch/arm/mach-rockchip/Kconfig

@@ -34,7 +34,6 @@ config ROCKCHIP_RK3188
 	select SPL_RAM
 	select SPL_DRIVERS_MISC_SUPPORT
 	select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
-	select DEBUG_UART_BOARD_INIT
 	select BOARD_LATE_INIT
 	select ROCKCHIP_BROM_HELPER
 	help
@@ -50,7 +49,6 @@ config ROCKCHIP_RK322X
 	select SUPPORT_SPL
 	select SPL
 	select ROCKCHIP_BROM_HELPER
-	select DEBUG_UART_BOARD_INIT
 	help
 	  The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
 	  including NEON and GPU, Mali-400 graphics, several DDR3 options
@@ -102,7 +100,6 @@ config ROCKCHIP_RK3368
 	imply SPL_SEPARATE_BSS
 	imply SPL_SERIAL_SUPPORT
 	imply TPL_SERIAL_SUPPORT
-	select DEBUG_UART_BOARD_INIT
 	help
 	  The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
 	  into a big and little cluster with 4 cores each) Cortex-A53 including
@@ -135,7 +132,6 @@ config ROCKCHIP_RK3399
 	select SPL_SEPARATE_BSS
 	select SPL_SERIAL_SUPPORT
 	select SPL_DRIVERS_MISC_SUPPORT
-	select DEBUG_UART_BOARD_INIT
 	select BOARD_LATE_INIT
 	select ROCKCHIP_BROM_HELPER
 	help
@@ -192,7 +188,7 @@ config ROCKCHIP_BOOT_MODE_REG
 	default 0x10300580 if ROCKCHIP_RV1108
 	default 0
 	help
-	  The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h)
+	  The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
 	  according to the value from this register.
 
 config ROCKCHIP_SPL_RESERVE_IRAM

arch/arm/mach-rockchip/boot_mode.c

@@ -6,7 +6,7 @@
 #include <common.h>
 #include <adc.h>
 #include <asm/io.h>
-#include <asm/arch/boot_mode.h>
+#include <asm/arch-rockchip/boot_mode.h>
 
 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG == 0)
 

arch/arm/mach-rockchip/bootrom.c

@@ -4,8 +4,8 @@
  */
 
 #include <common.h>
-#include <asm/arch/bootrom.h>
+#include <asm/arch-rockchip/bootrom.h>
-#include <asm/arch/boot_mode.h>
+#include <asm/arch-rockchip/boot_mode.h>
 #include <asm/io.h>
 #include <asm/setjmp.h>
 #include <asm/system.h>

arch/arm/mach-rockchip/rk3036-board-spl.c

@@ -6,31 +6,13 @@
 #include <common.h>
 #include <debug_uart.h>
 #include <asm/io.h>
-#include <asm/arch/bootrom.h>
+#include <asm/arch-rockchip/bootrom.h>
-#include <asm/arch/grf_rk3036.h>
+#include <asm/arch-rockchip/sdram_rk3036.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/timer.h>
-#include <asm/arch/sdram_rk3036.h>
-#include <asm/arch/timer.h>
-#include <asm/arch/uart.h>
-
-#define GRF_BASE	0x20008000
-
-#define DEBUG_UART_BASE	0x20068000
 
 void board_init_f(ulong dummy)
 {
-#ifdef EARLY_DEBUG
+#ifdef CONFIG_DEBUG_UART
-	struct rk3036_grf * const grf = (void *)GRF_BASE;
-	/*
-	 * NOTE: sd card and debug uart use same iomux in rk3036,
-	 * so if you enable uart,
-	 * you can not boot from sdcard
-	 */
-	rk_clrsetreg(&grf->gpio1c_iomux,
-		     GPIO1C3_MASK << GPIO1C3_SHIFT |
-		     GPIO1C2_MASK << GPIO1C2_SHIFT,
-		     GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT |
-		     GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
 	debug_uart_init();
 #endif
 	rockchip_timer_init();

arch/arm/mach-rockchip/rk3036-board.c

@@ -9,11 +9,11 @@
 #include <ram.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/periph.h>
+#include <asm/arch-rockchip/periph.h>
-#include <asm/arch/grf_rk3036.h>
+#include <asm/arch-rockchip/grf_rk3036.h>
-#include <asm/arch/boot_mode.h>
+#include <asm/arch-rockchip/boot_mode.h>
-#include <asm/arch/sdram_rk3036.h>
+#include <asm/arch-rockchip/sdram_rk3036.h>
 #include <dm/pinctrl.h>
 
 DECLARE_GLOBAL_DATA_PTR;

arch/arm/mach-rockchip/rk3036/Kconfig

@@ -9,7 +9,7 @@ config TARGET_KYLIN_RK3036
 	select BOARD_LATE_INIT
 
 config SYS_SOC
-	default "rockchip"
+	default "rk3036"
 
 config SYS_MALLOC_F_LEN
 	default 0x400

arch/arm/mach-rockchip/rk3036/Makefile

@@ -10,4 +10,5 @@ ifndef CONFIG_SPL_BUILD
 obj-y += syscon_rk3036.o
 endif
 
+obj-y += rk3036.o
 obj-y += sdram_rk3036.o

arch/arm/mach-rockchip/rk3036/clk_rk3036.c

@@ -7,8 +7,8 @@
 #include <common.h>
 #include <dm.h>
 #include <syscon.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/cru_rk3036.h>
+#include <asm/arch-rockchip/cru_rk3036.h>
 
 int rockchip_get_clk(struct udevice **devp)
 {

arch/arm/mach-rockchip/rk3036/rk3036.c

@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+#include <asm/io.h>
+#include <asm/arch-rockchip/grf_rk3036.h>
+#include <asm/arch-rockchip/hardware.h>
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+#define GRF_BASE	0x20008000
+	struct rk3036_grf * const grf = (void *)GRF_BASE;
+	enum {
+		GPIO1C3_SHIFT		= 6,
+		GPIO1C3_MASK		= 3 << GPIO1C3_SHIFT,
+		GPIO1C3_GPIO		= 0,
+		GPIO1C3_MMC0_D1,
+		GPIO1C3_UART2_SOUT,
+
+		GPIO1C2_SHIFT		= 4,
+		GPIO1C2_MASK		= 3 << GPIO1C2_SHIFT,
+		GPIO1C2_GPIO		= 0,
+		GPIO1C2_MMC0_D0,
+		GPIO1C2_UART2_SIN,
+	};
+	/*
+	 * NOTE: sd card and debug uart use same iomux in rk3036,
+	 * so if you enable uart,
+	 * you can not boot from sdcard
+	 */
+	rk_clrsetreg(&grf->gpio1c_iomux,
+		     GPIO1C3_MASK << GPIO1C3_SHIFT |
+		     GPIO1C2_MASK << GPIO1C2_SHIFT,
+		     GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT |
+		     GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
+}
+#endif

arch/arm/mach-rockchip/rk3036/sdram_rk3036.c

@@ -5,12 +5,12 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/types.h>
-#include <asm/arch/cru_rk3036.h>
+#include <asm/arch-rockchip/cru_rk3036.h>
-#include <asm/arch/grf_rk3036.h>
+#include <asm/arch-rockchip/grf_rk3036.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
-#include <asm/arch/sdram_rk3036.h>
+#include <asm/arch-rockchip/sdram_rk3036.h>
-#include <asm/arch/timer.h>
+#include <asm/arch-rockchip/timer.h>
-#include <asm/arch/uart.h>
+#include <asm/arch-rockchip/uart.h>
 
 /*
  * we can not fit the code to access the device tree in SPL

arch/arm/mach-rockchip/rk3036/syscon_rk3036.c

@@ -6,7 +6,7 @@
 #include <common.h>
 #include <dm.h>
 #include <syscon.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
 
 static const struct udevice_id rk3036_syscon_ids[] = {
 	{ .compatible = "rockchip,rk3036-grf", .data = ROCKCHIP_SYSCON_GRF },

arch/arm/mach-rockchip/rk3128-board.c

@@ -8,11 +8,11 @@
 #include <ram.h>
 #include <syscon.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/periph.h>
+#include <asm/arch-rockchip/periph.h>
-#include <asm/arch/grf_rk3128.h>
+#include <asm/arch-rockchip/grf_rk3128.h>
-#include <asm/arch/boot_mode.h>
+#include <asm/arch-rockchip/boot_mode.h>
-#include <asm/arch/timer.h>
+#include <asm/arch-rockchip/timer.h>
 #include <power/regulator.h>
 
 DECLARE_GLOBAL_DATA_PTR;

arch/arm/mach-rockchip/rk3128/Kconfig

@@ -14,7 +14,7 @@ config TARGET_EVB_RK3128
 endchoice
 
 config SYS_SOC
-	default "rockchip"
+	default "rk3128"
 
 config SYS_MALLOC_F_LEN
 	default 0x0800

arch/arm/mach-rockchip/rk3128/clk_rk3128.c

@@ -6,8 +6,8 @@
 #include <common.h>
 #include <dm.h>
 #include <syscon.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/cru_rk3128.h>
+#include <asm/arch-rockchip/cru_rk3128.h>
 
 int rockchip_get_clk(struct udevice **devp)
 {

arch/arm/mach-rockchip/rk3128/syscon_rk3128.c

@@ -6,7 +6,7 @@
 #include <common.h>
 #include <dm.h>
 #include <syscon.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
 
 static const struct udevice_id rk3128_syscon_ids[] = {
 	{ .compatible = "rockchip,rk3128-grf", .data = ROCKCHIP_SYSCON_GRF },

arch/arm/mach-rockchip/rk3188-board-spl.c

@@ -15,14 +15,14 @@
 #include <syscon.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
-#include <asm/arch/bootrom.h>
+#include <asm/arch-rockchip/bootrom.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/grf_rk3188.h>
+#include <asm/arch-rockchip/grf_rk3188.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
-#include <asm/arch/periph.h>
+#include <asm/arch-rockchip/periph.h>
-#include <asm/arch/pmu_rk3188.h>
+#include <asm/arch-rockchip/pmu_rk3188.h>
-#include <asm/arch/sdram.h>
+#include <asm/arch-rockchip/sdram.h>
-#include <asm/arch/timer.h>
+#include <asm/arch-rockchip/timer.h>
 #include <dm/pinctrl.h>
 #include <dm/root.h>
 #include <dm/test.h>
@@ -93,38 +93,12 @@ static int setup_arm_clock(void)
 	return ret;
 }
 
-void board_debug_uart_init(void)
-{
-	/* Enable early UART on the RK3188 */
-#define GRF_BASE	0x20008000
-	struct rk3188_grf * const grf = (void *)GRF_BASE;
-	enum {
-		GPIO1B1_SHIFT		= 2,
-		GPIO1B1_MASK		= 3,
-		GPIO1B1_GPIO		= 0,
-		GPIO1B1_UART2_SOUT,
-
-		GPIO1B0_SHIFT		= 0,
-		GPIO1B0_MASK		= 3,
-		GPIO1B0_GPIO		= 0,
-		GPIO1B0_UART2_SIN,
-	};
-
-	/* Enable early UART on the RK3188 */
-	rk_clrsetreg(&grf->gpio1b_iomux,
-		     GPIO1B1_MASK << GPIO1B1_SHIFT |
-		     GPIO1B0_MASK << GPIO1B0_SHIFT,
-		     GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
-		     GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
-}
-
 void board_init_f(ulong dummy)
 {
 	struct udevice *dev;
 	int ret;
 
-#define EARLY_UART
+#ifdef CONFIG_DEBUG_UART
-#ifdef EARLY_UART
 	/*
 	 * Debug UART can be used from here if required:
 	 *

arch/arm/mach-rockchip/rk3188-board.c

@@ -10,11 +10,11 @@
 #include <syscon.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/grf_rk3188.h>
+#include <asm/arch-rockchip/grf_rk3188.h>
-#include <asm/arch/periph.h>
+#include <asm/arch-rockchip/periph.h>
-#include <asm/arch/pmu_rk3288.h>
+#include <asm/arch-rockchip/pmu_rk3288.h>
-#include <asm/arch/boot_mode.h>
+#include <asm/arch-rockchip/boot_mode.h>
 #include <dm/pinctrl.h>
 
 __weak int rk_board_late_init(void)

arch/arm/mach-rockchip/rk3188/Kconfig

@@ -10,7 +10,7 @@ config TARGET_ROCK
 	  UART and GPIOs.
 
 config SYS_SOC
-	default "rockchip"
+	default "rk3188"
 
 config SYS_MALLOC_F_LEN
 	default 0x0800

arch/arm/mach-rockchip/rk3188/Makefile

@@ -6,5 +6,6 @@
 
 ifndef CONFIG_TPL_BUILD
 obj-y += clk_rk3188.o
+obj-y += rk3188.o
 obj-y += syscon_rk3188.o
 endif

arch/arm/mach-rockchip/rk3188/clk_rk3188.c

@@ -7,8 +7,8 @@
 #include <common.h>
 #include <dm.h>
 #include <syscon.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/cru_rk3188.h>
+#include <asm/arch-rockchip/cru_rk3188.h>
 
 int rockchip_get_clk(struct udevice **devp)
 {

arch/arm/mach-rockchip/rk3188/rk3188.c

@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/grf_rk3188.h>
+#include <asm/arch-rockchip/hardware.h>
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	/* Enable early UART on the RK3188 */
+#define GRF_BASE	0x20008000
+	struct rk3188_grf * const grf = (void *)GRF_BASE;
+	enum {
+		GPIO1B1_SHIFT		= 2,
+		GPIO1B1_MASK		= 3,
+		GPIO1B1_GPIO		= 0,
+		GPIO1B1_UART2_SOUT,
+		GPIO1B1_JTAG_TDO,
+
+		GPIO1B0_SHIFT		= 0,
+		GPIO1B0_MASK		= 3,
+		GPIO1B0_GPIO		= 0,
+		GPIO1B0_UART2_SIN,
+		GPIO1B0_JTAG_TDI,
+	};
+
+	rk_clrsetreg(&grf->gpio1b_iomux,
+		     GPIO1B1_MASK << GPIO1B1_SHIFT |
+		     GPIO1B0_MASK << GPIO1B0_SHIFT,
+		     GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
+		     GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
+}
+#endif

arch/arm/mach-rockchip/rk3188/syscon_rk3188.c

@@ -7,7 +7,7 @@
 #include <common.h>
 #include <dm.h>
 #include <syscon.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
 
 static const struct udevice_id rk3188_syscon_ids[] = {
 	{ .compatible = "rockchip,rk3188-noc", .data = ROCKCHIP_SYSCON_NOC },

arch/arm/mach-rockchip/rk322x-board-spl.c

@@ -9,55 +9,14 @@
 #include <ram.h>
 #include <spl.h>
 #include <asm/io.h>
-#include <asm/arch/bootrom.h>
+#include <asm/arch-rockchip/bootrom.h>
-#include <asm/arch/cru_rk322x.h>
+#include <asm/arch-rockchip/hardware.h>
-#include <asm/arch/grf_rk322x.h>
+#include <asm/arch-rockchip/timer.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/timer.h>
-#include <asm/arch/uart.h>
 
 u32 spl_boot_device(void)
 {
 	return BOOT_DEVICE_MMC1;
 }
-#define GRF_BASE	0x11000000
-#define SGRF_BASE	0x10140000
-
-#define DEBUG_UART_BASE	0x11030000
-
-void board_debug_uart_init(void)
-{
-	static struct rk322x_grf * const grf = (void *)GRF_BASE;
-	enum {
-		GPIO1B2_SHIFT		= 4,
-		GPIO1B2_MASK		= 3 << GPIO1B2_SHIFT,
-		GPIO1B2_GPIO            = 0,
-		GPIO1B2_UART1_SIN,
-		GPIO1B2_UART21_SIN,
-
-		GPIO1B1_SHIFT		= 2,
-		GPIO1B1_MASK		= 3 << GPIO1B1_SHIFT,
-		GPIO1B1_GPIO            = 0,
-		GPIO1B1_UART1_SOUT,
-		GPIO1B1_UART21_SOUT,
-	};
-	enum {
-		CON_IOMUX_UART2SEL_SHIFT= 8,
-		CON_IOMUX_UART2SEL_MASK	= 1 << CON_IOMUX_UART2SEL_SHIFT,
-		CON_IOMUX_UART2SEL_2	= 0,
-		CON_IOMUX_UART2SEL_21,
-	};
-
-	/* Enable early UART2 channel 1 on the RK322x */
-	rk_clrsetreg(&grf->gpio1b_iomux,
-		     GPIO1B1_MASK | GPIO1B2_MASK,
-		     GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
-		     GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
-	/* Set channel C as UART2 input */
-	rk_clrsetreg(&grf->con_iomux,
-		     CON_IOMUX_UART2SEL_MASK,
-		     CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
-}
 
 #define SGRF_DDR_CON0 0x10150000
 void board_init_f(ulong dummy)
@@ -65,6 +24,7 @@ void board_init_f(ulong dummy)
 	struct udevice *dev;
 	int ret;
 
+#ifdef CONFIG_DEBUG_UART
 	/*
 	 * Debug UART can be used from here if required:
 	 *
@@ -75,7 +35,7 @@ void board_init_f(ulong dummy)
 	 */
 	debug_uart_init();
 	printascii("SPL Init");
-
+#endif
 	ret = spl_early_init();
 	if (ret) {
 		debug("spl_early_init() failed: %d\n", ret);

arch/arm/mach-rockchip/rk322x-board.c

@@ -8,10 +8,10 @@
 #include <ram.h>
 #include <syscon.h>
 #include <asm/io.h>
-#include <asm/arch/boot_mode.h>
+#include <asm/arch-rockchip/boot_mode.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/periph.h>
+#include <asm/arch-rockchip/grf_rk322x.h>
-#include <asm/arch/grf_rk322x.h>
+#include <asm/arch-rockchip/periph.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -29,37 +29,10 @@ int board_late_init(void)
 
 int board_init(void)
 {
-#include <asm/arch/grf_rk322x.h>
+#include <asm/arch-rockchip/grf_rk322x.h>
 	/* Enable early UART2 channel 1 on the RK322x */
 #define GRF_BASE	0x11000000
-	struct rk322x_grf * const grf = (void *)GRF_BASE;
+	static struct rk322x_grf * const grf = (void *)GRF_BASE;
-	enum {
-		GPIO1B2_SHIFT		= 4,
-		GPIO1B2_MASK		= 3 << GPIO1B2_SHIFT,
-		GPIO1B2_GPIO		= 0,
-		GPIO1B2_UART21_SIN,
-
-		GPIO1B1_SHIFT		= 2,
-		GPIO1B1_MASK		= 3 << GPIO1B1_SHIFT,
-		GPIO1B1_GPIO            = 0,
-		GPIO1B1_UART1_SOUT,
-		GPIO1B1_UART21_SOUT,
-	};
-	enum {
-		CON_IOMUX_UART2SEL_SHIFT= 8,
-		CON_IOMUX_UART2SEL_MASK	= 1 << CON_IOMUX_UART2SEL_SHIFT,
-		CON_IOMUX_UART2SEL_2	= 0,
-		CON_IOMUX_UART2SEL_21,
-	};
-
-	rk_clrsetreg(&grf->gpio1b_iomux,
-		     GPIO1B1_MASK | GPIO1B2_MASK,
-		     GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
-		     GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
-	/* Set channel C as UART2 input */
-	rk_clrsetreg(&grf->con_iomux,
-		     CON_IOMUX_UART2SEL_MASK,
-		     CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
 
 	/*
 	* The integrated macphy is enabled by default, disable it

arch/arm/mach-rockchip/rk322x/Kconfig

@@ -5,7 +5,7 @@ config TARGET_EVB_RK3229
 	select BOARD_LATE_INIT
 
 config SYS_SOC
-	default "rockchip"
+	default "rk322x"
 
 config SYS_MALLOC_F_LEN
 	default 0x400

arch/arm/mach-rockchip/rk322x/Makefile

@@ -4,6 +4,6 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-
 obj-y += clk_rk322x.o
+obj-y += rk322x.o
 obj-y += syscon_rk322x.o

arch/arm/mach-rockchip/rk322x/clk_rk322x.c

@@ -6,8 +6,8 @@
 #include <common.h>
 #include <dm.h>
 #include <syscon.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/cru_rk322x.h>
+#include <asm/arch-rockchip/cru_rk322x.h>
 
 int rockchip_get_clk(struct udevice **devp)
 {

arch/arm/mach-rockchip/rk322x/rk322x.c

@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+#include <asm/io.h>
+#include <asm/arch-rockchip/grf_rk322x.h>
+#include <asm/arch-rockchip/hardware.h>
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+#define GRF_BASE	0x11000000
+	static struct rk322x_grf * const grf = (void *)GRF_BASE;
+	enum {
+		GPIO1B2_SHIFT		= 4,
+		GPIO1B2_MASK		= 3 << GPIO1B2_SHIFT,
+		GPIO1B2_GPIO            = 0,
+		GPIO1B2_UART1_SIN,
+		GPIO1B2_UART21_SIN,
+
+		GPIO1B1_SHIFT		= 2,
+		GPIO1B1_MASK		= 3 << GPIO1B1_SHIFT,
+		GPIO1B1_GPIO            = 0,
+		GPIO1B1_UART1_SOUT,
+		GPIO1B1_UART21_SOUT,
+	};
+	enum {
+		CON_IOMUX_UART2SEL_SHIFT = 8,
+		CON_IOMUX_UART2SEL_MASK	= 1 << CON_IOMUX_UART2SEL_SHIFT,
+		CON_IOMUX_UART2SEL_2	= 0,
+		CON_IOMUX_UART2SEL_21,
+	};
+
+	/* Enable early UART2 channel 1 on the RK322x */
+	rk_clrsetreg(&grf->gpio1b_iomux,
+		     GPIO1B1_MASK | GPIO1B2_MASK,
+		     GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
+		     GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
+	/* Set channel C as UART2 input */
+	rk_clrsetreg(&grf->con_iomux,
+		     CON_IOMUX_UART2SEL_MASK,
+		     CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
+}
+#endif

arch/arm/mach-rockchip/rk322x/syscon_rk322x.c

@@ -6,7 +6,7 @@
 #include <common.h>
 #include <dm.h>
 #include <syscon.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
 
 static const struct udevice_id rk322x_syscon_ids[] = {
 	{ .compatible = "rockchip,rk3228-grf", .data = ROCKCHIP_SYSCON_GRF },

arch/arm/mach-rockchip/rk3288-board-spl.c

@@ -14,15 +14,15 @@
 #include <spl.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
-#include <asm/arch/bootrom.h>
+#include <asm/arch-rockchip/bootrom.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
-#include <asm/arch/periph.h>
+#include <asm/arch-rockchip/periph.h>
-#include <asm/arch/pmu_rk3288.h>
+#include <asm/arch-rockchip/pmu_rk3288.h>
-#include <asm/arch/sdram.h>
+#include <asm/arch-rockchip/sdram.h>
-#include <asm/arch/sdram_common.h>
+#include <asm/arch-rockchip/sdram_common.h>
-#include <asm/arch/sys_proto.h>
+#include <asm/arch-rockchip/sys_proto.h>
-#include <asm/arch/timer.h>
+#include <asm/arch-rockchip/timer.h>
 #include <dm/pinctrl.h>
 #include <dm/root.h>
 #include <dm/test.h>
@@ -109,16 +109,7 @@ void board_init_f(ulong dummy)
 	struct udevice *dev;
 	int ret;
 
-	/* Example code showing how to enable the debug UART on RK3288 */
+#ifdef CONFIG_DEBUG_UART
-#include <asm/arch/grf_rk3288.h>
-	/* Enable early UART on the RK3288 */
-#define GRF_BASE	0xff770000
-	struct rk3288_grf * const grf = (void *)GRF_BASE;
-
-	rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
-		     GPIO7C6_MASK << GPIO7C6_SHIFT,
-		     GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
-		     GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
 	/*
 	 * Debug UART can be used from here if required:
 	 *
@@ -129,6 +120,7 @@ void board_init_f(ulong dummy)
 	 */
 	debug_uart_init();
 	debug("\nspl:debug uart enabled in %s\n", __func__);
+#endif
 	ret = spl_early_init();
 	if (ret) {
 		debug("spl_early_init() failed: %d\n", ret);

arch/arm/mach-rockchip/rk3288-board-tpl.c

@@ -10,28 +10,17 @@
 #include <spl.h>
 #include <version.h>
 #include <asm/io.h>
-#include <asm/arch/bootrom.h>
+#include <asm/arch-rockchip/bootrom.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/grf_rk3288.h>
+#include <asm/arch-rockchip/sys_proto.h>
-#include <asm/arch/periph.h>
+#include <asm/arch-rockchip/timer.h>
-#include <asm/arch/pmu_rk3288.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/timer.h>
 
-#define GRF_BASE		0xff770000
 void board_init_f(ulong dummy)
 {
 	struct udevice *dev;
 	int ret;
 
-	/* Example code showing how to enable the debug UART on RK3288 */
+#ifdef CONFIG_DEBUG_UART
-	/* Enable early UART on the RK3288 */
-	struct rk3288_grf * const grf = (void *)GRF_BASE;
-
-	rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
-		     GPIO7C6_MASK << GPIO7C6_SHIFT,
-		     GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
-		     GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
 	/*
 	 * Debug UART can be used from here if required:
 	 *
@@ -41,7 +30,7 @@ void board_init_f(ulong dummy)
 	 * printascii("string");
 	 */
 	debug_uart_init();
-
+#endif
 	ret = spl_early_init();
 	if (ret) {
 		debug("spl_early_init() failed: %d\n", ret);

arch/arm/mach-rockchip/rk3288-board.c

@@ -9,12 +9,12 @@
 #include <ram.h>
 #include <syscon.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/cru_rk3288.h>
+#include <asm/arch-rockchip/cru_rk3288.h>
-#include <asm/arch/periph.h>
+#include <asm/arch-rockchip/periph.h>
-#include <asm/arch/pmu_rk3288.h>
+#include <asm/arch-rockchip/pmu_rk3288.h>
-#include <asm/arch/qos_rk3288.h>
+#include <asm/arch-rockchip/qos_rk3288.h>
-#include <asm/arch/boot_mode.h>
+#include <asm/arch-rockchip/boot_mode.h>
 #include <asm/gpio.h>
 #include <dm/pinctrl.h>
 #include <dt-bindings/clock/rk3288-cru.h>
@@ -321,7 +321,6 @@ int board_early_init_f(void)
 {
 	const uintptr_t GRF_SOC_CON0 = 0xff770244;
 	const uintptr_t GRF_SOC_CON2 = 0xff77024c;
-	struct udevice *pinctrl;
 	struct udevice *dev;
 	int ret;
 
@@ -335,18 +334,7 @@ int board_early_init_f(void)
 		debug("CLK init failed: %d\n", ret);
 		return ret;
 	}
-	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
-	if (ret) {
-		debug("%s: Cannot find pinctrl device\n", __func__);
-		return ret;
-	}
 
-	/* Enable debug UART */
-	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
-	if (ret) {
-		debug("%s: Failed to set up console UART\n", __func__);
-		return ret;
-	}
 	rk_setreg(GRF_SOC_CON2, 1 << 0);
 
 	/*

arch/arm/mach-rockchip/rk3288/Kconfig

@@ -148,7 +148,7 @@ config ROCKCHIP_FAST_SPL
 	  and have the required PMIC code.
 
 config SYS_SOC
-	default "rockchip"
+	default "rk3288"
 
 config SYS_MALLOC_F_LEN
 	default 0x0800

arch/arm/mach-rockchip/rk3288/clk_rk3288.c

@@ -7,8 +7,8 @@
 #include <common.h>
 #include <dm.h>
 #include <syscon.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/cru_rk3288.h>
+#include <asm/arch-rockchip/cru_rk3288.h>
 
 int rockchip_get_clk(struct udevice **devp)
 {

arch/arm/mach-rockchip/rk3288/rk3288.c

@@ -3,16 +3,31 @@
  * Copyright (c) 2016 Rockchip Electronics Co., Ltd
  */
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/grf_rk3288.h>
 
-#define GRF_SOC_CON2 0xff77024c
+#define GRF_BASE	0xff770000
 
 int arch_cpu_init(void)
 {
 	/* We do some SoC one time setting here. */
+	struct rk3288_grf * const grf = (void *)GRF_BASE;
 
 	/* Use rkpwm by default */
-	rk_setreg(GRF_SOC_CON2, 1 << 0);
+	rk_setreg(&grf->soc_con2, 1 << 0);
 
 	return 0;
 }
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	/* Enable early UART on the RK3288 */
+	struct rk3288_grf * const grf = (void *)GRF_BASE;
+
+	rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
+		     GPIO7C6_MASK << GPIO7C6_SHIFT,
+		     GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
+		     GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
+}
+#endif

arch/arm/mach-rockchip/rk3288/syscon_rk3288.c

@@ -7,7 +7,7 @@
 #include <common.h>
 #include <dm.h>
 #include <syscon.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
 
 static const struct udevice_id rk3288_syscon_ids[] = {
 	{ .compatible = "rockchip,rk3288-noc", .data = ROCKCHIP_SYSCON_NOC },

arch/arm/mach-rockchip/rk3328/Kconfig

@@ -13,7 +13,7 @@ config TARGET_EVB_RK3328
 endchoice
 
 config SYS_SOC
-	default "rockchip"
+	default "rk3328"
 
 config SYS_MALLOC_F_LEN
 	default 0x0800

arch/arm/mach-rockchip/rk3328/clk_rk3328.c

@@ -5,8 +5,8 @@
 
 #include <common.h>
 #include <dm.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/cru_rk3328.h>
+#include <asm/arch-rockchip/cru_rk3328.h>
 
 int rockchip_get_clk(struct udevice **devp)
 {

arch/arm/mach-rockchip/rk3328/rk3328.c

@@ -4,7 +4,7 @@
  */
 
 #include <common.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
 #include <asm/armv8/mmu.h>
 #include <asm/io.h>
 

arch/arm/mach-rockchip/rk3328/syscon_rk3328.c

@@ -4,7 +4,7 @@
  */
 
 #include <common.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
 #include <dm.h>
 #include <syscon.h>
 

arch/arm/mach-rockchip/rk3368-board-spl.c

@@ -9,17 +9,9 @@
 #include <ram.h>
 #include <spl.h>
 #include <asm/io.h>
-#include <asm/arch/cru_rk3368.h>
+#include <asm/arch-rockchip/periph.h>
-#include <asm/arch/grf_rk3368.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/timer.h>
 #include <dm/pinctrl.h>
 
-void board_debug_uart_init(void)
-{
-}
-
 void board_init_f(ulong dummy)
 {
 	struct udevice *pinctrl;

arch/arm/mach-rockchip/rk3368-board-tpl.c

@@ -10,12 +10,11 @@
 #include <spl.h>
 #include <syscon.h>
 #include <asm/io.h>
-#include <asm/arch/bootrom.h>
+#include <asm/arch-rockchip/bootrom.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/cru_rk3368.h>
+#include <asm/arch-rockchip/cru_rk3368.h>
-#include <asm/arch/grf_rk3368.h>
+#include <asm/arch-rockchip/hardware.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/timer.h>
-#include <asm/arch/timer.h>
 
 /*
  * The SPL (and also the full U-Boot stage on the RK3368) will run in
@@ -79,42 +78,12 @@ static void sgrf_init(void)
 	rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
 }
 
-void board_debug_uart_init(void)
-{
-	/*
-	 * N.B.: This is called before the device-model has been
-	 *       initialised. For this reason, we can not access
-	 *       the GRF address range using the syscon API.
-	 */
-	struct rk3368_grf * const grf =
-		(struct rk3368_grf * const)0xff770000;
-
-	enum {
-		GPIO2D1_MASK            = GENMASK(3, 2),
-		GPIO2D1_GPIO            = 0,
-		GPIO2D1_UART0_SOUT      = (1 << 2),
-
-		GPIO2D0_MASK            = GENMASK(1, 0),
-		GPIO2D0_GPIO            = 0,
-		GPIO2D0_UART0_SIN       = (1 << 0),
-	};
-
-#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
-	/* Enable early UART0 on the RK3368 */
-	rk_clrsetreg(&grf->gpio2d_iomux,
-		     GPIO2D0_MASK, GPIO2D0_UART0_SIN);
-	rk_clrsetreg(&grf->gpio2d_iomux,
-		     GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
-#endif
-}
-
 void board_init_f(ulong dummy)
 {
 	struct udevice *dev;
 	int ret;
 
-#define EARLY_UART
+#ifdef CONFIG_DEBUG_UART
-#ifdef EARLY_UART
 	/*
 	 * Debug UART can be used from here if required:
 	 *

arch/arm/mach-rockchip/rk3368/Kconfig

@@ -43,7 +43,7 @@ config TARGET_EVB_PX5
 endchoice
 
 config SYS_SOC
-	default "rockchip"
+	default "rk3368"
 
 source "board/theobroma-systems/lion_rk3368/Kconfig"
 source "board/rockchip/sheep_rk3368/Kconfig"

arch/arm/mach-rockchip/rk3368/clk_rk3368.c

@@ -7,8 +7,8 @@
 #include <common.h>
 #include <dm.h>
 #include <syscon.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/cru_rk3368.h>
+#include <asm/arch-rockchip/cru_rk3368.h>
 
 int rockchip_get_clk(struct udevice **devp)
 {

arch/arm/mach-rockchip/rk3368/rk3368.c

@@ -7,9 +7,9 @@
 #include <common.h>
 #include <asm/armv8/mmu.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/cru_rk3368.h>
+#include <asm/arch-rockchip/cru_rk3368.h>
-#include <asm/arch/grf_rk3368.h>
+#include <asm/arch-rockchip/grf_rk3368.h>
 #include <syscon.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -96,3 +96,34 @@ int arch_early_init_r(void)
 	return mcu_init();
 }
 #endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	/*
+	 * N.B.: This is called before the device-model has been
+	 *       initialised. For this reason, we can not access
+	 *       the GRF address range using the syscon API.
+	 */
+#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
+	struct rk3368_grf * const grf =
+		(struct rk3368_grf * const)0xff770000;
+
+	enum {
+		GPIO2D1_MASK            = GENMASK(3, 2),
+		GPIO2D1_GPIO            = 0,
+		GPIO2D1_UART0_SOUT      = (1 << 2),
+
+		GPIO2D0_MASK            = GENMASK(1, 0),
+		GPIO2D0_GPIO            = 0,
+		GPIO2D0_UART0_SIN       = (1 << 0),
+	};
+
+	/* Enable early UART0 on the RK3368 */
+	rk_clrsetreg(&grf->gpio2d_iomux,
+		     GPIO2D0_MASK, GPIO2D0_UART0_SIN);
+	rk_clrsetreg(&grf->gpio2d_iomux,
+		     GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
+#endif
+}
+#endif

arch/arm/mach-rockchip/rk3368/syscon_rk3368.c

@@ -8,7 +8,7 @@
 #include <common.h>
 #include <dm.h>
 #include <syscon.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
 
 static const struct udevice_id rk3368_syscon_ids[] = {
 	{ .compatible = "rockchip,rk3368-grf",

arch/arm/mach-rockchip/rk3399-board-spl.c

@@ -12,12 +12,12 @@
 #include <spl_gpio.h>
 #include <syscon.h>
 #include <asm/io.h>
-#include <asm/arch/bootrom.h>
+#include <asm/arch-rockchip/bootrom.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/grf_rk3399.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
-#include <asm/arch/periph.h>
+#include <asm/arch-rockchip/periph.h>
-#include <asm/arch/sys_proto.h>
+#include <asm/arch-rockchip/sys_proto.h>
 #include <dm/pinctrl.h>
 
 void board_return_to_bootrom(void)
@@ -127,53 +127,6 @@ void secure_timer_init(void)
 	writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
 }
 
-void board_debug_uart_init(void)
-{
-#define GRF_BASE	0xff770000
-#define GPIO0_BASE	0xff720000
-#define PMUGRF_BASE	0xff320000
-	struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
-#ifdef CONFIG_TARGET_CHROMEBOOK_BOB
-	struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
-	struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
-#endif
-
-#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
-	/* Enable early UART0 on the RK3399 */
-	rk_clrsetreg(&grf->gpio2c_iomux,
-		     GRF_GPIO2C0_SEL_MASK,
-		     GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
-	rk_clrsetreg(&grf->gpio2c_iomux,
-		     GRF_GPIO2C1_SEL_MASK,
-		     GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
-#else
-# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
-	rk_setreg(&grf->io_vsel, 1 << 0);
-
-	/*
-	 * Let's enable these power rails here, we are already running the SPI
-	 * Flash based code.
-	 */
-	spl_gpio_output(gpio, GPIO(BANK_B, 2), 1);  /* PP1500_EN */
-	spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
-
-	spl_gpio_output(gpio, GPIO(BANK_B, 4), 1);  /* PP3000_EN */
-	spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
-#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
-
-	/* Enable early UART2 channel C on the RK3399 */
-	rk_clrsetreg(&grf->gpio4c_iomux,
-		     GRF_GPIO4C3_SEL_MASK,
-		     GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
-	rk_clrsetreg(&grf->gpio4c_iomux,
-		     GRF_GPIO4C4_SEL_MASK,
-		     GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
-	/* Set channel C as UART2 input */
-	rk_clrsetreg(&grf->soc_con7,
-		     GRF_UART_DBG_SEL_MASK,
-		     GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
-#endif
-}
 
 void board_init_f(ulong dummy)
 {
@@ -183,8 +136,7 @@ void board_init_f(ulong dummy)
 	struct rk3399_grf_regs *grf;
 	int ret;
 
-#define EARLY_UART
+#ifdef CONFIG_DEBUG_UART
-#ifdef EARLY_UART
 	debug_uart_init();
 
 # ifdef CONFIG_TARGET_CHROMEBOOK_BOB

arch/arm/mach-rockchip/rk3399-board.c

@@ -4,7 +4,7 @@
  */
 
 #include <common.h>
-#include <asm/arch/boot_mode.h>
+#include <asm/arch-rockchip/boot_mode.h>
 
 int board_late_init(void)
 {

arch/arm/mach-rockchip/rk3399/Kconfig

@@ -65,7 +65,7 @@ config TARGET_CHROMEBOOK_BOB
 endchoice
 
 config SYS_SOC
-	default "rockchip"
+	default "rk3399"
 
 config SYS_MALLOC_F_LEN
 	default 0x0800

arch/arm/mach-rockchip/rk3399/clk_rk3399.c

@@ -7,8 +7,8 @@
 #include <common.h>
 #include <dm.h>
 #include <syscon.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/cru_rk3399.h>
+#include <asm/arch-rockchip/cru_rk3399.h>
 
 static int rockchip_get_cruclk(struct udevice **devp)
 {

arch/arm/mach-rockchip/rk3399/rk3399.c

@@ -4,13 +4,17 @@
  */
 
 #include <common.h>
+#include <spl_gpio.h>
 #include <asm/armv8/mmu.h>
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/gpio.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/hardware.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 #define GRF_EMMCCORE_CON11 0xff77f02c
+#define GRF_BASE	0xff770000
 
 static struct mm_region rk3399_mem_map[] = {
 	{
@@ -48,9 +52,60 @@ int dram_init_banksize(void)
 int arch_cpu_init(void)
 {
 	/* We do some SoC one time setting here. */
+	struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
 
 	/* Emmc clock generator: disable the clock multipilier */
-	rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff);
+	rk_clrreg(&grf->emmccore_con[11], 0x0ff);
 
 	return 0;
 }
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+#define GRF_BASE	0xff770000
+#define GPIO0_BASE	0xff720000
+#define PMUGRF_BASE	0xff320000
+	struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
+#ifdef CONFIG_TARGET_CHROMEBOOK_BOB
+	struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
+	struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
+#endif
+
+#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
+	/* Enable early UART0 on the RK3399 */
+	rk_clrsetreg(&grf->gpio2c_iomux,
+		     GRF_GPIO2C0_SEL_MASK,
+		     GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
+	rk_clrsetreg(&grf->gpio2c_iomux,
+		     GRF_GPIO2C1_SEL_MASK,
+		     GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
+#else
+# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
+	rk_setreg(&grf->io_vsel, 1 << 0);
+
+	/*
+	 * Let's enable these power rails here, we are already running the SPI
+	 * Flash based code.
+	 */
+	spl_gpio_output(gpio, GPIO(BANK_B, 2), 1);  /* PP1500_EN */
+	spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
+
+	spl_gpio_output(gpio, GPIO(BANK_B, 4), 1);  /* PP3000_EN */
+	spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
+#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
+
+	/* Enable early UART2 channel C on the RK3399 */
+	rk_clrsetreg(&grf->gpio4c_iomux,
+		     GRF_GPIO4C3_SEL_MASK,
+		     GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
+	rk_clrsetreg(&grf->gpio4c_iomux,
+		     GRF_GPIO4C4_SEL_MASK,
+		     GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
+	/* Set channel C as UART2 input */
+	rk_clrsetreg(&grf->soc_con7,
+		     GRF_UART_DBG_SEL_MASK,
+		     GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
+#endif
+}
+#endif

arch/arm/mach-rockchip/rk3399/syscon_rk3399.c

@@ -6,7 +6,7 @@
 #include <common.h>
 #include <dm.h>
 #include <syscon.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
 
 static const struct udevice_id rk3399_syscon_ids[] = {
 	{ .compatible = "rockchip,rk3399-grf", .data = ROCKCHIP_SYSCON_GRF },

arch/arm/mach-rockchip/rk_timer.c

@@ -4,7 +4,7 @@
  */
 
 #include <common.h>
-#include <asm/arch/timer.h>
+#include <asm/arch-rockchip/timer.h>
 #include <asm/io.h>
 #include <linux/types.h>
 

arch/arm/mach-rockchip/rv1108/Kconfig

@@ -23,7 +23,7 @@ config TARGET_ELGIN_RV1108
 	  RV1108 ELGIN is a board based on the Rockchip RV1108.
 
 config SYS_SOC
-	default "rockchip"
+	default "rv1108"
 
 config SYS_MALLOC_F_LEN
 	default 0x400

arch/arm/mach-rockchip/rv1108/clk_rv1108.c

@@ -7,8 +7,8 @@
 #include <common.h>
 #include <dm.h>
 #include <syscon.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/cru_rv1108.h>
+#include <asm/arch-rockchip/cru_rv1108.h>
 
 int rockchip_get_clk(struct udevice **devp)
 {

arch/arm/mach-rockchip/rv1108/syscon_rv1108.c

@@ -6,7 +6,7 @@
 #include <common.h>
 #include <dm.h>
 #include <syscon.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
 
 static const struct udevice_id rv1108_syscon_ids[] = {
 	{ .compatible = "rockchip,rv1108-grf", .data = ROCKCHIP_SYSCON_GRF },

arch/arm/mach-rockchip/sdram_common.c

@@ -7,7 +7,7 @@
 #include <dm.h>
 #include <ram.h>
 #include <asm/io.h>
-#include <asm/arch/sdram_common.h>
+#include <asm/arch-rockchip/sdram_common.h>
 #include <dm/uclass-internal.h>
 
 DECLARE_GLOBAL_DATA_PTR;

board/elgin/elgin_rv1108/elgin_rv1108.c

@@ -7,8 +7,8 @@
 #include <common.h>
 #include <asm/io.h>
 #include <fdtdec.h>
-#include <asm/arch/grf_rv1108.h>
+#include <asm/arch-rockchip/grf_rv1108.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
 #include <asm/gpio.h>
 
 DECLARE_GLOBAL_DATA_PTR;

board/rockchip/evb_rk3036/evb_rk3036.c

@@ -6,8 +6,8 @@
 #include <common.h>
 #include <dm.h>
 #include <asm/io.h>
-#include <asm/arch/uart.h>
+#include <asm/arch-rockchip/uart.h>
-#include <asm/arch/sdram_rk3036.h>
+#include <asm/arch-rockchip/sdram_rk3036.h>
 
 void get_ddr_config(struct rk3036_ddr_config *config)
 {

board/rockchip/evb_rk3229/evb_rk3229.c

@@ -6,5 +6,5 @@
 #include <common.h>
 #include <dm.h>
 #include <asm/io.h>
-#include <asm/arch/uart.h>
+#include <asm/arch-rockchip/uart.h>
 

board/rockchip/evb_rk3399/MAINTAINERS

@@ -5,3 +5,10 @@ F:      board/rockchip/evb_rk3399
 F:      include/configs/evb_rk3399.h
 F:      configs/evb-rk3399_defconfig
 F:      configs/firefly-rk3399_defconfig
+
+ORANGEPI-RK3399
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/orangepi-rk3399_defconfig
+F:	arch/arm/dts/rk3399-u-boot.dtsi
+F:	arch/arm/dts/rk3399-orangepi-u-boot.dtsi

board/rockchip/evb_rk3399/evb-rk3399.c

@@ -7,7 +7,7 @@
 #include <dm.h>
 #include <dm/pinctrl.h>
 #include <dm/uclass-internal.h>
-#include <asm/arch/periph.h>
+#include <asm/arch-rockchip/periph.h>
 #include <power/regulator.h>
 #include <spl.h>
 

board/rockchip/evb_rv1108/evb_rv1108.c

@@ -7,8 +7,8 @@
 #include <common.h>
 #include <asm/io.h>
 #include <fdtdec.h>
-#include <asm/arch/grf_rv1108.h>
+#include <asm/arch-rockchip/grf_rv1108.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

board/rockchip/kylin_rk3036/kylin_rk3036.c

@@ -6,8 +6,8 @@
 #include <common.h>
 #include <dm.h>
 #include <asm/io.h>
-#include <asm/arch/uart.h>
+#include <asm/arch-rockchip/uart.h>
-#include <asm/arch/sdram_rk3036.h>
+#include <asm/arch-rockchip/sdram_rk3036.h>
 #include <asm/gpio.h>
 
 void get_ddr_config(struct rk3036_ddr_config *config)

board/rockchip/sheep_rk3368/sheep_rk3368.c

@@ -4,8 +4,8 @@
  */
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/grf_rk3368.h>
+#include <asm/arch-rockchip/grf_rk3368.h>
 #include <syscon.h>
 
 int mach_cpu_init(void)

board/theobroma-systems/lion_rk3368/lion_rk3368.c

@@ -6,9 +6,9 @@
 #include <dm.h>
 #include <ram.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/grf_rk3368.h>
+#include <asm/arch-rockchip/grf_rk3368.h>
-#include <asm/arch/timer.h>
+#include <asm/arch-rockchip/timer.h>
 #include <syscon.h>
 
 int mach_cpu_init(void)

board/theobroma-systems/puma_rk3399/puma-rk3399.c

@@ -15,11 +15,11 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 #include <asm/setup.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/cru_rk3399.h>
+#include <asm/arch-rockchip/cru_rk3399.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
-#include <asm/arch/grf_rk3399.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
-#include <asm/arch/periph.h>
+#include <asm/arch-rockchip/periph.h>
 #include <power/regulator.h>
 #include <u-boot/sha256.h>
 

board/vamrs/rock960_rk3399/rock960-rk3399.c

@@ -7,7 +7,7 @@
 #include <dm.h>
 #include <dm/pinctrl.h>
 #include <dm/uclass-internal.h>
-#include <asm/arch/periph.h>
+#include <asm/arch-rockchip/periph.h>
 #include <power/regulator.h>
 #include <spl.h>
 

cmd/rockusb.c

@@ -8,7 +8,7 @@
 #include <console.h>
 #include <g_dnl.h>
 #include <usb.h>
-#include <asm/arch/f_rockusb.h>
+#include <asm/arch-rockchip/f_rockusb.h>
 
 static int do_rockusb(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {

configs/kylin-rk3036_defconfig

@@ -7,8 +7,11 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ROCKCHIP_RK3036=y
 CONFIG_TARGET_KYLIN_RK3036=y
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x0
-CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEBUG_UART_BASE=0x20068000
+CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DEBUG_UART=y
+CONFIG_NR_DRAM_BANKS=1
 # CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_DEFAULT_FDT_FILE="rk3036-kylin.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
@@ -46,6 +49,7 @@ CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_PINCTRL=y
 CONFIG_DM_REGULATOR_FIXED=y
 # CONFIG_SPL_DM_SERIAL is not set
+CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y

configs/orangepi-rk3399_defconfig

@@ -0,0 +1,75 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DEBUG_UART=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-orangepi"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_ERRNO_STR=y

configs/puma-rk3399_defconfig

@@ -69,6 +69,7 @@ CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y

doc/git-mailrc

@@ -26,6 +26,7 @@ alias iwamatsu       Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 alias jaehoon        Jaehoon Chung <jh80.chung@samsung.com>
 alias jagan          Jagan Teki <jagan@amarulasolutions.com>
 alias jhersh         Joe Hershberger <joe.hershberger@ni.com>
+alias kevery         Kever Yang <kever.yang@rock-chips.com>
 alias lukma          Lukasz Majewski <lukma@denx.de>
 alias macpaul        Macpaul Lin <macpaul@andestech.com>
 alias marex          Marek Vasut <marex@denx.de>
@@ -70,7 +71,7 @@ alias tegra2         tegra
 alias ti             uboot, trini
 alias uniphier       uboot, masahiro
 alias zynq           uboot, monstr
-alias rockchip       uboot, sjg, Kever Yang <kever.yang@rock-chips.com>, ptomsich
+alias rockchip       uboot, sjg, kevery, ptomsich
 
 alias m68k           uboot, alisonwang, angelo_ts
 alias coldfire       m68k

drivers/clk/rockchip/clk_rk3036.c

@@ -9,9 +9,9 @@
 #include <errno.h>
 #include <syscon.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/cru_rk3036.h>
+#include <asm/arch-rockchip/cru_rk3036.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
 #include <dm/lists.h>
 #include <dt-bindings/clock/rk3036-cru.h>
 #include <linux/log2.h>

drivers/clk/rockchip/clk_rk3128.c

@@ -9,9 +9,9 @@
 #include <errno.h>
 #include <syscon.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/cru_rk3128.h>
+#include <asm/arch-rockchip/cru_rk3128.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
 #include <bitfield.h>
 #include <dm/lists.h>
 #include <dt-bindings/clock/rk3128-cru.h>

drivers/clk/rockchip/clk_rk3188.c

@@ -12,10 +12,10 @@
 #include <mapmem.h>
 #include <syscon.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/cru_rk3188.h>
+#include <asm/arch-rockchip/cru_rk3188.h>
-#include <asm/arch/grf_rk3188.h>
+#include <asm/arch-rockchip/grf_rk3188.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
 #include <dt-bindings/clock/rk3188-cru.h>
 #include <dm/device-internal.h>
 #include <dm/lists.h>

drivers/clk/rockchip/clk_rk322x.c

@@ -9,9 +9,9 @@
 #include <errno.h>
 #include <syscon.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/cru_rk322x.h>
+#include <asm/arch-rockchip/cru_rk322x.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
 #include <dm/lists.h>
 #include <dt-bindings/clock/rk3228-cru.h>
 #include <linux/log2.h>

drivers/clk/rockchip/clk_rk3288.c

@@ -13,10 +13,10 @@
 #include <mapmem.h>
 #include <syscon.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/cru_rk3288.h>
+#include <asm/arch-rockchip/cru_rk3288.h>
-#include <asm/arch/grf_rk3288.h>
+#include <asm/arch-rockchip/grf_rk3288.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
 #include <dt-bindings/clock/rk3288-cru.h>
 #include <dm/device-internal.h>
 #include <dm/lists.h>

drivers/clk/rockchip/clk_rk3328.c

@@ -9,10 +9,10 @@
 #include <dm.h>
 #include <errno.h>
 #include <syscon.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/cru_rk3328.h>
+#include <asm/arch-rockchip/cru_rk3328.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
-#include <asm/arch/grf_rk3328.h>
+#include <asm/arch-rockchip/grf_rk3328.h>
 #include <asm/io.h>
 #include <dm/lists.h>
 #include <dt-bindings/clock/rk3328-cru.h>

drivers/clk/rockchip/clk_rk3368.c

@@ -13,9 +13,9 @@
 #include <mapmem.h>
 #include <syscon.h>
 #include <bitfield.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/cru_rk3368.h>
+#include <asm/arch-rockchip/cru_rk3368.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
 #include <asm/io.h>
 #include <dm/lists.h>
 #include <dt-bindings/clock/rk3368-cru.h>

drivers/clk/rockchip/clk_rk3399.c

@@ -13,9 +13,9 @@
 #include <syscon.h>
 #include <bitfield.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/cru_rk3399.h>
+#include <asm/arch-rockchip/cru_rk3399.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
 #include <dm/lists.h>
 #include <dt-bindings/clock/rk3399-cru.h>
 

drivers/clk/rockchip/clk_rv1108.c

@@ -11,9 +11,9 @@
 #include <errno.h>
 #include <syscon.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/cru_rv1108.h>
+#include <asm/arch-rockchip/cru_rv1108.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
 #include <dm/lists.h>
 #include <dt-bindings/clock/rv1108-cru.h>
 

drivers/gpio/rk_gpio.c

@@ -12,7 +12,8 @@
 #include <linux/errno.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/gpio.h>
 #include <dm/pinctrl.h>
 #include <dt-bindings/clock/rk3288-cru.h>
 

drivers/i2c/rk_i2c.c

@@ -12,9 +12,9 @@
 #include <errno.h>
 #include <i2c.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/i2c.h>
+#include <asm/arch-rockchip/i2c.h>
-#include <asm/arch/periph.h>
+#include <asm/arch-rockchip/periph.h>
 #include <dm/pinctrl.h>
 #include <linux/sizes.h>
 

drivers/mmc/rockchip_dw_mmc.c

@@ -13,8 +13,8 @@
 #include <pwrseq.h>
 #include <syscon.h>
 #include <asm/gpio.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
-#include <asm/arch/periph.h>
+#include <asm/arch-rockchip/periph.h>
 #include <linux/err.h>
 
 struct rockchip_mmc_plat {