mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-19 05:31:32 +00:00
clk: stm32mp1: fix CK_MPU calculation
When the CK_MPU used PLL1_MPUDIV, the current rate is wrong. The clock must use stm32mp1_mpu_div as a shift value. Fix the check value used to enter PLL_MPUDIV. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This commit is contained in:
parent
d7244e4a1f
commit
36911fca63
1 changed files with 4 additions and 3 deletions
|
@ -954,10 +954,11 @@ static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
|
|||
case RCC_MPCKSELR_PLL:
|
||||
case RCC_MPCKSELR_PLL_MPUDIV:
|
||||
clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
|
||||
if (p == RCC_MPCKSELR_PLL_MPUDIV) {
|
||||
if ((reg & RCC_SELR_SRC_MASK) ==
|
||||
RCC_MPCKSELR_PLL_MPUDIV) {
|
||||
reg = readl(priv->base + RCC_MPCKDIVR);
|
||||
clock /= stm32mp1_mpu_div[reg &
|
||||
RCC_MPUDIV_MASK];
|
||||
clock >>= stm32mp1_mpu_div[reg &
|
||||
RCC_MPUDIV_MASK];
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
|
Loading…
Add table
Reference in a new issue