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armv8: Ensure EL1&0 VMSA is enabled
On Armv8-R, the EL1&0 memory system architecture is configurable as a VMSA or PMSA, and resets to an "architecturally unknown" value. Add code to armv8_switch_to_el1_m which detects whether the MSA at EL1&0 is configurable using the id_aa64mmfr0_el1 register MSA fields. If it is we must ensure the VMSA is enabled so that a rich OS can boot. The MSA and MSA_FRAC fields are described in the Armv8-R architecture profile supplement (section G1.3.7): https://developer.arm.com/documentation/ddi0600/latest/ Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
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2 changed files with 41 additions and 0 deletions
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@ -316,6 +316,23 @@ lr .req x30
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csel \tmp, \tmp2, \tmp, eq
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csel \tmp, \tmp2, \tmp, eq
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msr hcr_el2, \tmp
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msr hcr_el2, \tmp
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/*
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* Detect whether the system has a configurable memory system
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* architecture at EL1&0
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*/
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mrs \tmp, id_aa64mmfr0_el1
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lsr \tmp, \tmp, #48
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and \tmp, \tmp, #((ID_AA64MMFR0_EL1_MSA_MASK | \
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ID_AA64MMFR0_EL1_MSA_FRAC_MASK) >> 48)
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cmp \tmp, #((ID_AA64MMFR0_EL1_MSA_USE_FRAC | \
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ID_AA64MMFR0_EL1_MSA_FRAC_VMSA) >> 48)
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bne 2f
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/* Ensure the EL1&0 VMSA is enabled */
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mov \tmp, #(VTCR_EL2_MSA)
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msr vtcr_el2, \tmp
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2:
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/* Return to the EL1_SP1 mode from EL2 */
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/* Return to the EL1_SP1 mode from EL2 */
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ldr \tmp, =(SPSR_EL_DEBUG_MASK | SPSR_EL_SERR_MASK |\
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ldr \tmp, =(SPSR_EL_DEBUG_MASK | SPSR_EL_SERR_MASK |\
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SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
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SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
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@ -83,6 +83,30 @@
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#define HCR_EL2_RW_AARCH32 (0 << 31) /* Lower levels are AArch32 */
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#define HCR_EL2_RW_AARCH32 (0 << 31) /* Lower levels are AArch32 */
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#define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */
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#define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */
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/*
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* VTCR_EL2 bits definitions
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*/
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#define VTCR_EL2_MSA (1 << 31) /* EL1&0 memory architecture */
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/*
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* ID_AA64MMFR0_EL1 bits definitions
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*/
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#define ID_AA64MMFR0_EL1_MSA_FRAC_MASK (0xFUL << 52) /* Memory system
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architecture
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frac */
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#define ID_AA64MMFR0_EL1_MSA_FRAC_VMSA (0x2UL << 52) /* EL1&0 supports
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VMSA */
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#define ID_AA64MMFR0_EL1_MSA_FRAC_PMSA (0x1UL << 52) /* EL1&0 only
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supports PMSA*/
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#define ID_AA64MMFR0_EL1_MSA_FRAC_NO_PMSA (0x0UL << 52) /* No PMSA
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support */
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#define ID_AA64MMFR0_EL1_MSA_MASK (0xFUL << 48) /* Memory system
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architecture */
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#define ID_AA64MMFR0_EL1_MSA_USE_FRAC (0xFUL << 48) /* Use MSA_FRAC */
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#define ID_AA64MMFR0_EL1_MSA_VMSA (0x0UL << 48) /* Memory system
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architecture
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is VMSA */
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/*
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/*
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* ID_AA64ISAR1_EL1 bits definitions
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* ID_AA64ISAR1_EL1 bits definitions
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*/
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*/
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