mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-19 05:31:32 +00:00
dm: pch: Add get_gpio_base op
x86 GPIO registers are accessed via I/O port whose base address is configured in a PCI configuration register on the PCH device. Add an op get_gpio_base to get the GPIO base address from PCH. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
parent
3e389d8ba6
commit
384980c687
2 changed files with 29 additions and 0 deletions
|
@ -33,6 +33,17 @@ int pch_set_spi_protect(struct udevice *dev, bool protect)
|
||||||
return ops->set_spi_protect(dev, protect);
|
return ops->set_spi_protect(dev, protect);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
int pch_get_gpio_base(struct udevice *dev, u32 *gbasep)
|
||||||
|
{
|
||||||
|
struct pch_ops *ops = pch_get_ops(dev);
|
||||||
|
|
||||||
|
*gbasep = 0;
|
||||||
|
if (!ops->get_gpio_base)
|
||||||
|
return -ENOSYS;
|
||||||
|
|
||||||
|
return ops->get_gpio_base(dev, gbasep);
|
||||||
|
}
|
||||||
|
|
||||||
static int pch_uclass_post_bind(struct udevice *bus)
|
static int pch_uclass_post_bind(struct udevice *bus)
|
||||||
{
|
{
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -32,6 +32,15 @@ struct pch_ops {
|
||||||
* @return 0 on success, -ENOSYS if not implemented
|
* @return 0 on success, -ENOSYS if not implemented
|
||||||
*/
|
*/
|
||||||
int (*set_spi_protect)(struct udevice *dev, bool protect);
|
int (*set_spi_protect)(struct udevice *dev, bool protect);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* get_gpio_base() - get the address of GPIO base
|
||||||
|
*
|
||||||
|
* @dev: PCH device to check
|
||||||
|
* @gbasep: Returns address of GPIO base if available, else 0
|
||||||
|
* @return 0 if OK, -ve on error (e.g. there is no GPIO base)
|
||||||
|
*/
|
||||||
|
int (*get_gpio_base)(struct udevice *dev, u32 *gbasep);
|
||||||
};
|
};
|
||||||
|
|
||||||
#define pch_get_ops(dev) ((struct pch_ops *)(dev)->driver->ops)
|
#define pch_get_ops(dev) ((struct pch_ops *)(dev)->driver->ops)
|
||||||
|
@ -55,4 +64,13 @@ int pch_get_spi_base(struct udevice *dev, ulong *sbasep);
|
||||||
*/
|
*/
|
||||||
int pch_set_spi_protect(struct udevice *dev, bool protect);
|
int pch_set_spi_protect(struct udevice *dev, bool protect);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* pch_get_gpio_base() - get the address of GPIO base
|
||||||
|
*
|
||||||
|
* @dev: PCH device to check
|
||||||
|
* @gbasep: Returns address of GPIO base if available, else 0
|
||||||
|
* @return 0 if OK, -ve on error (e.g. there is no GPIO base)
|
||||||
|
*/
|
||||||
|
int pch_get_gpio_base(struct udevice *dev, u32 *gbasep);
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
Loading…
Add table
Reference in a new issue