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ARM: HYP/non-sec: add the option for a second-stage monitor

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Allow the switch to a second stage secure monitor just before
switching to non-secure.

This allows a resident piece of firmware to be active once the
kernel has been entered (the u-boot monitor is dead anyway,
its pages being reused).

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This commit is contained in:
Marc Zyngier 2014-07-12 14:24:05 +01:00 • committed by Albert ARIBAUD
parent ecf07a7930
commit 38510a4b34
1 changed files with 12 additions and 3 deletions
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15
arch/arm/cpu/armv7/nonsec_virt.S
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@ -44,10 +44,19 @@ _monitor_vectors:
* ip: target PC
*/
_secure_monitor:
mrc p15, 0, r5, c1, c1, 0 @ read SCR
bic r5, r5, #0x4e @ clear IRQ, FIQ, EA, nET bits
orr r5, r5, #0x31 @ enable NS, AW, FW bits
#ifdef CONFIG_ARMV7_PSCI
ldr r5, =_psci_vectors @ Switch to the next monitor
mcr p15, 0, r5, c12, c0, 1
isb
@ Obtain a secure stack, and configure the PSCI backend
bl psci_arch_init
#endif
mrc p15, 0, r5, c1, c1, 0 @ read SCR
bic r5, r5, #0x4a @ clear IRQ, EA, nET bits
orr r5, r5, #0x31 @ enable NS, AW, FW bits
@ FIQ preserved for secure mode
mov r6, #SVC_MODE @ default mode is SVC
is_cpu_virt_capable r4
#ifdef CONFIG_ARMV7_VIRT