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da850evm: Use clrbits function with correct endianess
The current code uses clrbits_be32 which is incorrect since we are on a little endian machine here. This patch fixes this issue and also removes some unnecessary code: Reading the current GPIO bank state is not required if we are using the SET and CLEAR GPIO registers for setting/clearing bits. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com> Cc: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
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parent
bf0e86606d
commit
3864cb2133
1 changed files with 3 additions and 11 deletions
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@ -323,10 +323,6 @@ int board_early_init_f(void)
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int board_init(void)
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{
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#if defined(CONFIG_USE_NOR) || defined(CONFIG_DAVINCI_MMC)
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u32 val;
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#endif
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#ifndef CONFIG_USE_IRQ
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irq_init();
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#endif
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@ -366,12 +362,10 @@ int board_init(void)
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#ifdef CONFIG_USE_NOR
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/* Set the GPIO direction as output */
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clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
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clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
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/* Set the output as low */
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val = readl(GPIO_BANK0_REG_SET_ADDR);
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val |= (0x01 << 11);
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writel(val, GPIO_BANK0_REG_CLR_ADDR);
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writel(0x01 << 11, GPIO_BANK0_REG_CLR_ADDR);
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#endif
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#ifdef CONFIG_DAVINCI_MMC
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@ -379,9 +373,7 @@ int board_init(void)
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clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
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/* Set the output as high */
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val = readl(GPIO_BANK0_REG_SET_ADDR);
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val |= (0x01 << 11);
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writel(val, GPIO_BANK0_REG_SET_ADDR);
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writel(0x01 << 11, GPIO_BANK0_REG_SET_ADDR);
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#endif
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#ifdef CONFIG_DRIVER_TI_EMAC
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