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da850evm: Use clrbits function with correct endianess

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The current code uses clrbits_be32 which is incorrect since we are on
a little endian machine here. This patch fixes this issue and also removes
some unnecessary code: Reading the current GPIO bank state is not required
if we are using the SET and CLEAR GPIO registers for setting/clearing
bits.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
Cc: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
This commit is contained in:
Christian Riesch 2013-06-14 14:22:36 +02:00 • committed by Tom Rini
parent bf0e86606d
commit 3864cb2133
1 changed files with 3 additions and 11 deletions
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14
board/davinci/da8xxevm/da850evm.c
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@ -323,10 +323,6 @@ int board_early_init_f(void)
int board_init(void) int board_init(void)
{ {
#if defined(CONFIG_USE_NOR) || defined(CONFIG_DAVINCI_MMC)
u32 val;
#endif
#ifndef CONFIG_USE_IRQ #ifndef CONFIG_USE_IRQ
irq_init(); irq_init();
#endif #endif
@ -366,12 +362,10 @@ int board_init(void)
#ifdef CONFIG_USE_NOR #ifdef CONFIG_USE_NOR
/* Set the GPIO direction as output */ /* Set the GPIO direction as output */
clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
/* Set the output as low */ /* Set the output as low */
val = readl(GPIO_BANK0_REG_SET_ADDR); writel(0x01 << 11, GPIO_BANK0_REG_CLR_ADDR);
val |= (0x01 << 11);
writel(val, GPIO_BANK0_REG_CLR_ADDR);
#endif #endif
#ifdef CONFIG_DAVINCI_MMC #ifdef CONFIG_DAVINCI_MMC
@ -379,9 +373,7 @@ int board_init(void)
clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
/* Set the output as high */ /* Set the output as high */
val = readl(GPIO_BANK0_REG_SET_ADDR); writel(0x01 << 11, GPIO_BANK0_REG_SET_ADDR);
val |= (0x01 << 11);
writel(val, GPIO_BANK0_REG_SET_ADDR);
#endif #endif
#ifdef CONFIG_DRIVER_TI_EMAC #ifdef CONFIG_DRIVER_TI_EMAC