Merge git://www.denx.de/git/u-boot-marvell

arch/arm/mach-mvebu/include/mach/soc.h

@@ -55,6 +55,7 @@
 #define MVEBU_L2_CACHE_BASE	(MVEBU_REGISTER(0x08000))
 #define CONFIG_SYS_PL310_BASE	MVEBU_L2_CACHE_BASE
 #define MVEBU_TWSI_BASE		(MVEBU_REGISTER(0x11000))
+#define MVEBU_TWSI1_BASE	(MVEBU_REGISTER(0x11100))
 #define MVEBU_MPP_BASE		(MVEBU_REGISTER(0x18000))
 #define MVEBU_GPIO0_BASE	(MVEBU_REGISTER(0x18100))
 #define MVEBU_GPIO1_BASE	(MVEBU_REGISTER(0x18140))

board/theadorable/theadorable.c

@@ -5,9 +5,13 @@
  */
 
 #include <common.h>
+#include <i2c.h>
+#include <pci.h>
+#include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
+#include <linux/crc8.h>
 #include <linux/mbus.h>
 #ifdef CONFIG_NET
 #include <netdev.h>
@@ -19,6 +23,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define MV_USB_PHY_BASE			(MVEBU_AXP_USB_BASE + 0x800)
+#define PHY_CHANNEL_RX_CTRL0_REG(port, chan) \
+	(MV_USB_PHY_BASE + ((port) << 12) + ((chan) << 6) + 0x8)
+
 #define THEADORABLE_GPP_OUT_ENA_LOW	0x00336780
 #define THEADORABLE_GPP_OUT_ENA_MID	0x00003cf0
 #define THEADORABLE_GPP_OUT_ENA_HIGH	(~(0x0))
@@ -27,6 +35,15 @@ DECLARE_GLOBAL_DATA_PTR;
 #define THEADORABLE_GPP_OUT_VAL_MID	0x0007000c
 #define THEADORABLE_GPP_OUT_VAL_HIGH	0x00000000
 
+#define GPIO_USB0_PWR_ON		18
+#define GPIO_USB1_PWR_ON		19
+
+#define PEX_SWITCH_NOT_FOUNT_LIMIT	3
+
+#define STM_I2C_BUS	1
+#define STM_I2C_ADDR	0x27
+#define REBOOT_DELAY	1000		/* reboot-delay in ms */
+
 /* DDR3 static configuration */
 static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = {
 	{0x00001400, 0x7301ca28},	/* DDR SDRAM Configuration Register */
@@ -135,6 +152,8 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
+	int ret;
+
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 
@@ -147,13 +166,33 @@ int board_init(void)
 	mbus_dt_setup_win(&mbus_state, SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE,
 			  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2);
 
+	/*
+	 * Set RX Channel Control 0 Register:
+	 * Tests have shown, that setting the LPF_COEF from 0 (1/8)
+	 * to 3 (1/1) results in a more stable USB connection.
+	 */
+	setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 1), 0xc);
+	setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 2), 0xc);
+	setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 3), 0xc);
+
+	/* Toggle USB power */
+	ret = gpio_request(GPIO_USB0_PWR_ON, "USB0_PWR_ON");
+	if (ret < 0)
+		return ret;
+	gpio_direction_output(GPIO_USB0_PWR_ON, 0);
+	ret = gpio_request(GPIO_USB1_PWR_ON, "USB1_PWR_ON");
+	if (ret < 0)
+		return ret;
+	gpio_direction_output(GPIO_USB1_PWR_ON, 0);
+	mdelay(1);
+	gpio_set_value(GPIO_USB0_PWR_ON, 1);
+	gpio_set_value(GPIO_USB1_PWR_ON, 1);
+
 	return 0;
 }
 
 int checkboard(void)
 {
-	puts("Board: theadorable\n");
-
 	board_fpga_add();
 
 	return 0;
@@ -182,3 +221,63 @@ int board_video_init(void)
 
 	return mvebu_lcd_register_init(&lcd_info);
 }
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	pci_dev_t bdf;
+	ulong bootcount;
+
+	/*
+	 * Check if the PEX switch is detected (somtimes its not available
+	 * on the PCIe bus). In this case, try to recover by issuing a
+	 * soft-reset or even a power-cycle, depending on the bootcounter
+	 * value.
+	 */
+	bdf = pci_find_device(PCI_VENDOR_ID_PLX, 0x8619, 0);
+	if (bdf == -1) {
+		u8 i2c_buf[8];
+		int ret;
+
+		/* PEX switch not found! */
+		bootcount = bootcount_load();
+		printf("Failed to find PLX PEX-switch (bootcount=%ld)\n",
+		       bootcount);
+		if (bootcount > PEX_SWITCH_NOT_FOUNT_LIMIT) {
+			printf("Issuing power-switch via uC!\n");
+
+			printf("Issuing power-switch via uC!\n");
+			i2c_set_bus_num(STM_I2C_BUS);
+			i2c_buf[0] = STM_I2C_ADDR << 1;
+			i2c_buf[1] = 0xc5;	/* cmd */
+			i2c_buf[2] = 0x01;	/* enable */
+			/* Delay before reboot */
+			i2c_buf[3] = REBOOT_DELAY & 0x00ff;
+			i2c_buf[4] = (REBOOT_DELAY & 0xff00) >> 8;
+			/* Delay before shutdown */
+			i2c_buf[5] = 0x00;
+			i2c_buf[6] = 0x00;
+			i2c_buf[7] = crc8(0x72, &i2c_buf[0], 7);
+
+			ret = i2c_write(STM_I2C_ADDR, 0, 0, &i2c_buf[1], 7);
+			if (ret) {
+				printf("I2C write error (ret=%d)\n", ret);
+				printf("Issuing soft-reset...\n");
+				/* default handling: SOFT reset */
+				do_reset(NULL, 0, 0, NULL);
+			}
+
+			/* Wait for power-cycle to occur... */
+			printf("Waiting for power-cycle via uC...\n");
+			while (1)
+				;
+		} else {
+			printf("Issuing soft-reset...\n");
+			/* default handling: SOFT reset */
+			do_reset(NULL, 0, 0, NULL);
+		}
+	}
+
+	return 0;
+}
+#endif

drivers/gpio/mvebu_gpio.c

@@ -43,6 +43,10 @@ static int mvebu_gpio_direction_output(struct udevice *dev, unsigned gpio,
 	struct mvebu_gpio_priv *priv = dev_get_priv(dev);
 	struct mvebu_gpio_regs *regs = priv->regs;
 
+	if (value)
+		setbits_le32(&regs->data_out, BIT(gpio));
+	else
+		clrbits_le32(&regs->data_out, BIT(gpio));
 	clrbits_le32(&regs->io_conf, BIT(gpio));
 
 	return 0;

include/configs/theadorable.h

@@ -51,6 +51,7 @@
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MVTWSI
 #define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
+#define CONFIG_I2C_MVTWSI_BASE1		MVEBU_TWSI1_BASE
 #define CONFIG_SYS_I2C_SLAVE		0x0
 #define CONFIG_SYS_I2C_SPEED		100000
 
@@ -103,6 +104,7 @@
 #define CONFIG_PCI
 #define CONFIG_PCI_MVEBU
 #define CONFIG_PCI_PNP
+#define CONFIG_BOARD_LATE_INIT		/* for PEX switch test */
 #endif
 #endif
 
@@ -119,6 +121,14 @@
 #define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_STRATIX_V
 
+/*
+ * Bootcounter
+ */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_RAM
+/* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
+#define BOOTCOUNT_ADDR			0x1000
+
 /*
  * mv-common.h should be defined after CMD configs since it used them
  * to enable certain macros