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arm64: zynqmp: Fix si570 clock output names and references
Align clock output names with node references. Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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parent
052451c10b
commit
3ab205c117
1 changed files with 5 additions and 5 deletions
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@ -2,7 +2,7 @@
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/*
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/*
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* dts file for Xilinx Versal a2197 RevA System Controller
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* dts file for Xilinx Versal a2197 RevA System Controller
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*
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*
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* (C) Copyright 2019, Xilinx, Inc.
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* (C) Copyright 2019 - 2020, Xilinx, Inc.
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*
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*
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* Michal Simek <michal.simek@xilinx.com>
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* Michal Simek <michal.simek@xilinx.com>
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*/
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*/
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@ -421,14 +421,14 @@
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temperature-stability = <50>;
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temperature-stability = <50>;
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factory-fout = <156250000>;
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factory-fout = <156250000>;
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clock-frequency = <156250000>;
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clock-frequency = <156250000>;
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clock-output-names = "si570_hsdp_clk";
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clock-output-names = "si570_zsfp_clk";
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};
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};
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};
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};
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i2c@6 { /* USER_SI570_1 */
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i2c@6 { /* USER_SI570_1 */
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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#size-cells = <0>;
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reg = <6>;
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reg = <6>;
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si570_user1_clk: clock-generator@5d { /* u205 */
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si570_user1: clock-generator@5d { /* u205 */
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#clock-cells = <0>;
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#clock-cells = <0>;
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compatible = "silabs,si570";
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compatible = "silabs,si570";
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reg = <0x5f>;
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reg = <0x5f>;
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@ -510,7 +510,7 @@
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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#size-cells = <0>;
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reg = <4>;
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reg = <4>;
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si570_ddr_dimm2: clock-generator@60 { /* u3 */
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si570_lpddr4clk2: clock-generator@60 { /* u3 */
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#clock-cells = <0>;
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#clock-cells = <0>;
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compatible = "silabs,si570";
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compatible = "silabs,si570";
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reg = <0x60>;
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reg = <0x60>;
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@ -524,7 +524,7 @@
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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#size-cells = <0>;
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reg = <5>;
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reg = <5>;
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si570_lpddr4: clock-generator@60 { /* u4 */
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si570_lpddr4clk1: clock-generator@60 { /* u4 */
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#clock-cells = <0>;
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#clock-cells = <0>;
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compatible = "silabs,si570";
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compatible = "silabs,si570";
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reg = <0x60>;
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reg = <0x60>;
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