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avr32: Rename pm_init() as clk_init() and make SoC-specific
pm_init() was always more about clock initialization than anything else. Dealing with PLLs, clock gating and such is also inherently SoC-specific, so move it into a SoC-specific directory. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
This commit is contained in:
Haavard Skinnemoen
parent
4f5972c3b2
commit
3ace2527ba
5 changed files with 76 additions and 44 deletions
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@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk
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LIB := $(obj)lib$(SOC).a
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COBJS := gpio.o
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COBJS := gpio.o clk.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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68
cpu/at32ap/at32ap700x/clk.c
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68
cpu/at32ap/at32ap700x/clk.c
Normal file
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@ -0,0 +1,68 @@
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/*
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* Copyright (C) 2005-2008 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/memory-map.h>
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#include "sm.h"
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void clk_init(void)
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{
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uint32_t cksel;
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/* in case of soft resets, disable watchdog */
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sm_writel(WDT_CTRL, SM_BF(KEY, 0x55));
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sm_writel(WDT_CTRL, SM_BF(KEY, 0xaa));
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#ifdef CONFIG_PLL
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/* Initialize the PLL */
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sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
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| SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
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| SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
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| SM_BF(PLLOPT, CFG_PLL0_OPT)
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| SM_BF(PLLOSC, 0)
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| SM_BIT(PLLEN)));
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/* Wait for lock */
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while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ;
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#endif
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/* Set up clocks for the CPU and all peripheral buses */
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cksel = 0;
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if (CFG_CLKDIV_CPU)
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cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
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if (CFG_CLKDIV_HSB)
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cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
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if (CFG_CLKDIV_PBA)
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cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
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if (CFG_CLKDIV_PBB)
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cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
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sm_writel(PM_CKSEL, cksel);
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#ifdef CONFIG_PLL
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/* Use PLL0 as main clock */
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sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));
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#endif
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}
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@ -30,7 +30,6 @@
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#include <asm/arch/memory-map.h>
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#include "hsmc3.h"
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#include "sm.h"
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/* Sanity checks */
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#if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB) \
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@ -44,51 +43,10 @@
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DECLARE_GLOBAL_DATA_PTR;
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static void pm_init(void)
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{
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uint32_t cksel;
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#ifdef CONFIG_PLL
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/* Initialize the PLL */
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sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
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| SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
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| SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
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| SM_BF(PLLOPT, CFG_PLL0_OPT)
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| SM_BF(PLLOSC, 0)
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| SM_BIT(PLLEN)));
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/* Wait for lock */
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while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ;
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#endif
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/* Set up clocks for the CPU and all peripheral buses */
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cksel = 0;
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if (CFG_CLKDIV_CPU)
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cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
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if (CFG_CLKDIV_HSB)
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cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
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if (CFG_CLKDIV_PBA)
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cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
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if (CFG_CLKDIV_PBB)
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cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
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sm_writel(PM_CKSEL, cksel);
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gd->cpu_hz = get_cpu_clk_rate();
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#ifdef CONFIG_PLL
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/* Use PLL0 as main clock */
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sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));
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#endif
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}
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int cpu_init(void)
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{
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extern void _evba(void);
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/* in case of soft resets, disable watchdog */
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sm_writel(WDT_CTRL, SM_BF(KEY, 0x55));
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sm_writel(WDT_CTRL, SM_BF(KEY, 0xaa));
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gd->cpu_hz = CFG_OSC0_HZ;
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/* TODO: Move somewhere else, but needs to be run before we
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@ -98,8 +56,12 @@ int cpu_init(void)
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hsmc3_writel(PULSE0, 0x0b0a0906);
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hsmc3_writel(SETUP0, 0x00010002);
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pm_init();
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clk_init();
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/* Update the CPU speed according to the PLL configuration */
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gd->cpu_hz = get_cpu_clk_rate();
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/* Set up the exception handler table and enable exceptions */
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sysreg_write(EVBA, (unsigned long)&_evba);
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asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET));
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@ -75,6 +75,8 @@ static inline unsigned long get_mci_clk_rate(void)
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}
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#endif
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extern void clk_init(void);
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/* Board code may need the SDRAM base clock as a compile-time constant */
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#define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CFG_CLKDIV_HSB)
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