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spi: mxc_spi: Fix spi clock glitch durant reset

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Measuring the spi clock line on a scope shows a 'glitch' during the reset of the
spi.

Fix this by toggling only the MXC_CSPICTRL_EN bit, so that the clock line becomes
always stable.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Fabio Estevam 2012-11-15 11:23:24 +00:00 • committed by Stefano Babic
parent de5bf02cb1
commit 3cea335c34
1 changed files with 2 additions and 2 deletions
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4
drivers/spi/mxc_spi.c
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@ -140,8 +140,8 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
reg_ctrl = reg_read(&regs->ctrl); reg_ctrl = reg_read(&regs->ctrl);
/* Reset spi */ /* Reset spi */
reg_write(&regs->ctrl, 0); reg_write(&regs->ctrl, (reg_ctrl & ~MXC_CSPICTRL_EN));
reg_write(&regs->ctrl, (reg_ctrl | 0x1)); reg_write(&regs->ctrl, (reg_ctrl | MXC_CSPICTRL_EN));
/* /*
* The following computation is taken directly from Freescale's code. * The following computation is taken directly from Freescale's code.