mirror of
https://github.com/Fishwaldo/u-boot.git
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- Fix sifive serial y-modem transfer. - Access CSRs using CSR numbers. - Update doc sifive-fu540 - Support big endian hosts and target.
This commit is contained in:
Tom Rini
commit
3d240d89c4
9 changed files with 430 additions and 488 deletions
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@ -7,7 +7,6 @@
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#include <cpu.h>
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#include <dm.h>
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#include <log.h>
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#include <asm/csr.h>
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#include <asm/encoding.h>
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#include <dm/uclass-internal.h>
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@ -48,7 +47,7 @@ static inline bool supports_extension(char ext)
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return false;
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#else /* !CONFIG_CPU */
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#ifdef CONFIG_RISCV_MMODE
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return csr_read(misa) & (1 << (ext - 'a'));
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return csr_read(CSR_MISA) & (1 << (ext - 'a'));
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#else /* !CONFIG_RISCV_MMODE */
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#warning "There is no way to determine the available extensions in S-mode."
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#warning "Please convert your board to use the RISC-V CPU driver."
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@ -82,7 +81,7 @@ int arch_cpu_init_dm(void)
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/* Enable FPU */
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if (supports_extension('d') || supports_extension('f')) {
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csr_set(MODE_PREFIX(status), MSTATUS_FS);
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csr_write(fcsr, 0);
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csr_write(CSR_FCSR, 0);
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}
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if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
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@ -90,11 +89,11 @@ int arch_cpu_init_dm(void)
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* Enable perf counters for cycle, time,
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* and instret counters only
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*/
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csr_write(mcounteren, GENMASK(2, 0));
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csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
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/* Disable paging */
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if (supports_extension('s'))
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csr_write(satp, 0);
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csr_write(CSR_SATP, 0);
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}
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return 0;
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@ -13,7 +13,6 @@
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#include <config.h>
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#include <common.h>
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#include <elf.h>
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#include <asm/csr.h>
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#include <asm/encoding.h>
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#include <generated/asm-offsets.h>
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@ -41,7 +40,7 @@ secondary_harts_relocation_error:
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.globl _start
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_start:
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#ifdef CONFIG_RISCV_MMODE
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csrr a0, mhartid
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csrr a0, CSR_MHARTID
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#endif
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/* save hart id and dtb pointer */
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68
arch/riscv/include/asm/asm.h
Normal file
68
arch/riscv/include/asm/asm.h
Normal file
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@ -0,0 +1,68 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_ASM_H
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#define _ASM_RISCV_ASM_H
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#ifdef __ASSEMBLY__
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#define __ASM_STR(x) x
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#else
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#define __ASM_STR(x) #x
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#endif
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#if __riscv_xlen == 64
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#define __REG_SEL(a, b) __ASM_STR(a)
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#elif __riscv_xlen == 32
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#define __REG_SEL(a, b) __ASM_STR(b)
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#else
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#error "Unexpected __riscv_xlen"
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#endif
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#define REG_L __REG_SEL(ld, lw)
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#define REG_S __REG_SEL(sd, sw)
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#define SZREG __REG_SEL(8, 4)
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#define LGREG __REG_SEL(3, 2)
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#if __SIZEOF_POINTER__ == 8
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#ifdef __ASSEMBLY__
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#define RISCV_PTR .dword
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#define RISCV_SZPTR 8
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#define RISCV_LGPTR 3
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#else
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#define RISCV_PTR ".dword"
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#define RISCV_SZPTR "8"
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#define RISCV_LGPTR "3"
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#endif
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#elif __SIZEOF_POINTER__ == 4
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#ifdef __ASSEMBLY__
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#define RISCV_PTR .word
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#define RISCV_SZPTR 4
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#define RISCV_LGPTR 2
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#else
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#define RISCV_PTR ".word"
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#define RISCV_SZPTR "4"
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#define RISCV_LGPTR "2"
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#endif
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#else
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#error "Unexpected __SIZEOF_POINTER__"
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#endif
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#if (__SIZEOF_INT__ == 4)
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#define RISCV_INT __ASM_STR(.word)
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#define RISCV_SZINT __ASM_STR(4)
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#define RISCV_LGINT __ASM_STR(2)
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#else
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#error "Unexpected __SIZEOF_INT__"
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#endif
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#if (__SIZEOF_SHORT__ == 2)
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#define RISCV_SHORT __ASM_STR(.half)
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#define RISCV_SZSHORT __ASM_STR(2)
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#define RISCV_LGSHORT __ASM_STR(1)
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#else
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#error "Unexpected __SIZEOF_SHORT__"
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#endif
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#endif /* _ASM_RISCV_ASM_H */
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@ -1,4 +1,4 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 Regents of the University of California
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*
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@ -8,13 +8,14 @@
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#ifndef _ASM_RISCV_CSR_H
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#define _ASM_RISCV_CSR_H
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#include <asm/asm.h>
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#include <linux/const.h>
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/* Status register flags */
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#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
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#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
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#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
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#define SR_SUM _AC(0x00040000, UL) /* Supervisor access User Memory */
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#define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
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#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
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#define SR_FS_OFF _AC(0x00000000, UL)
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@ -35,7 +36,7 @@
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#endif
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/* SATP flags */
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#if __riscv_xlen == 32
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#ifndef CONFIG_64BIT
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#define SATP_PPN _AC(0x003FFFFF, UL)
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#define SATP_MODE_32 _AC(0x80000000, UL)
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#define SATP_MODE SATP_MODE_32
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@ -45,10 +46,18 @@
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#define SATP_MODE SATP_MODE_39
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#endif
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/* Interrupt Enable and Interrupt Pending flags */
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#define MIE_MSIE _AC(0x00000008, UL) /* Software Interrupt Enable */
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#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */
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#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */
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/* SCAUSE */
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#define SCAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1))
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#define IRQ_U_SOFT 0
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#define IRQ_S_SOFT 1
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#define IRQ_M_SOFT 3
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#define IRQ_U_TIMER 4
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#define IRQ_S_TIMER 5
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#define IRQ_M_TIMER 7
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#define IRQ_U_EXT 8
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#define IRQ_S_EXT 9
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#define IRQ_M_EXT 11
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#define EXC_INST_MISALIGNED 0
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#define EXC_INST_ACCESS 1
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@ -60,14 +69,47 @@
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#define EXC_LOAD_PAGE_FAULT 13
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#define EXC_STORE_PAGE_FAULT 15
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#ifndef __ASSEMBLY__
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/* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */
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#define MIE_MSIE (_AC(0x1, UL) << IRQ_M_SOFT)
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#define SIE_SSIE (_AC(0x1, UL) << IRQ_S_SOFT)
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#define SIE_STIE (_AC(0x1, UL) << IRQ_S_TIMER)
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#define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT)
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#define xcsr(csr) #csr
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#define CSR_FCSR 0x003
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#define CSR_CYCLE 0xc00
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#define CSR_TIME 0xc01
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#define CSR_INSTRET 0xc02
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#define CSR_SSTATUS 0x100
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#define CSR_SIE 0x104
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#define CSR_STVEC 0x105
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#define CSR_SCOUNTEREN 0x106
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#define CSR_SSCRATCH 0x140
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#define CSR_SEPC 0x141
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#define CSR_SCAUSE 0x142
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#define CSR_STVAL 0x143
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#define CSR_SIP 0x144
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#define CSR_SATP 0x180
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#define CSR_MSTATUS 0x300
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#define CSR_MISA 0x301
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#define CSR_MIE 0x304
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#define CSR_MTVEC 0x305
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#define CSR_MCOUNTEREN 0x306
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#define CSR_MSCRATCH 0x340
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#define CSR_MEPC 0x341
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#define CSR_MCAUSE 0x342
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#define CSR_MTVAL 0x343
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#define CSR_MIP 0x344
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#define CSR_CYCLEH 0xc80
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#define CSR_TIMEH 0xc81
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#define CSR_INSTRETH 0xc82
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#define CSR_MHARTID 0xf14
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#ifndef __ASSEMBLY__
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#define csr_swap(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrrw %0, " xcsr(csr) ", %1" \
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__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
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: "=r" (__v) : "rK" (__v) \
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: "memory"); \
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__v; \
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@ -76,7 +118,7 @@
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#define csr_read(csr) \
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({ \
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register unsigned long __v; \
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__asm__ __volatile__ ("csrr %0, " xcsr(csr) \
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__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \
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: "=r" (__v) : \
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: "memory"); \
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__v; \
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@ -85,7 +127,7 @@
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#define csr_write(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrw " xcsr(csr) ", %0" \
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__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \
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: : "rK" (__v) \
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: "memory"); \
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})
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@ -93,7 +135,7 @@
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#define csr_read_set(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrrs %0, " xcsr(csr) ", %1" \
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__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
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: "=r" (__v) : "rK" (__v) \
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: "memory"); \
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__v; \
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@ -102,7 +144,7 @@
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#define csr_set(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrs " xcsr(csr) ", %0" \
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__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \
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: : "rK" (__v) \
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: "memory"); \
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})
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@ -110,7 +152,7 @@
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#define csr_read_clear(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrrc %0, " xcsr(csr) ", %1" \
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__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
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: "=r" (__v) : "rK" (__v) \
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: "memory"); \
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__v; \
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@ -119,7 +161,7 @@
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#define csr_clear(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrc " xcsr(csr) ", %0" \
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__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \
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: : "rK" (__v) \
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: "memory"); \
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})
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@ -7,6 +7,8 @@
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#ifndef RISCV_CSR_ENCODING_H
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#define RISCV_CSR_ENCODING_H
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#include <asm/csr.h>
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#ifdef CONFIG_RISCV_SMODE
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#define MODE_PREFIX(__suffix) s##__suffix
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#else
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@ -49,13 +51,10 @@
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#define SSTATUS64_SD 0x8000000000000000
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#define MIP_SSIP BIT(IRQ_S_SOFT)
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#define MIP_HSIP BIT(IRQ_H_SOFT)
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#define MIP_MSIP BIT(IRQ_M_SOFT)
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#define MIP_STIP BIT(IRQ_S_TIMER)
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#define MIP_HTIP BIT(IRQ_H_TIMER)
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#define MIP_MTIP BIT(IRQ_M_TIMER)
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#define MIP_SEIP BIT(IRQ_S_EXT)
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#define MIP_HEIP BIT(IRQ_H_EXT)
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#define MIP_MEIP BIT(IRQ_M_EXT)
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#define SIP_SSIP MIP_SSIP
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@ -73,18 +72,6 @@
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#define VM_SV39 9
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#define VM_SV48 10
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#define IRQ_S_SOFT 1
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#define IRQ_H_SOFT 2
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#define IRQ_M_SOFT 3
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#define IRQ_S_TIMER 5
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#define IRQ_H_TIMER 6
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#define IRQ_M_TIMER 7
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#define IRQ_S_EXT 9
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#define IRQ_H_EXT 10
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#define IRQ_M_EXT 11
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#define IRQ_COP 12
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#define IRQ_HOST 13
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#define CAUSE_MISALIGNED_FETCH 0
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#define CAUSE_FETCH_ACCESS 1
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#define CAUSE_ILLEGAL_INSTRUCTION 2
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@ -167,227 +154,6 @@
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#define RISCV_PGSHIFT 12
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#define RISCV_PGSIZE BIT(RISCV_PGSHIFT)
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/* CSR numbers */
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#define CSR_FFLAGS 0x1
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#define CSR_FRM 0x2
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#define CSR_FCSR 0x3
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#define CSR_SSTATUS 0x100
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#define CSR_SEDELEG 0x102
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#define CSR_SIDELEG 0x103
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#define CSR_SIE 0x104
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#define CSR_STVEC 0x105
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#define CSR_SCOUNTEREN 0x106
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#define CSR_SSCRATCH 0x140
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#define CSR_SEPC 0x141
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#define CSR_SCAUSE 0x142
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#define CSR_STVAL 0x143
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#define CSR_SIP 0x144
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#define CSR_SATP 0x180
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#define CSR_MSTATUS 0x300
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#define CSR_MISA 0x301
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#define CSR_MEDELEG 0x302
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#define CSR_MIDELEG 0x303
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#define CSR_MIE 0x304
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#define CSR_MTVEC 0x305
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#define CSR_MCOUNTEREN 0x306
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#define CSR_MHPMEVENT3 0x323
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#define CSR_MHPMEVENT4 0x324
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#define CSR_MHPMEVENT5 0x325
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#define CSR_MHPMEVENT6 0x326
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#define CSR_MHPMEVENT7 0x327
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#define CSR_MHPMEVENT8 0x328
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#define CSR_MHPMEVENT9 0x329
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#define CSR_MHPMEVENT10 0x32a
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#define CSR_MHPMEVENT11 0x32b
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#define CSR_MHPMEVENT12 0x32c
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#define CSR_MHPMEVENT13 0x32d
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#define CSR_MHPMEVENT14 0x32e
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#define CSR_MHPMEVENT15 0x32f
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#define CSR_MHPMEVENT16 0x330
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#define CSR_MHPMEVENT17 0x331
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#define CSR_MHPMEVENT18 0x332
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#define CSR_MHPMEVENT19 0x333
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#define CSR_MHPMEVENT20 0x334
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#define CSR_MHPMEVENT21 0x335
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#define CSR_MHPMEVENT22 0x336
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#define CSR_MHPMEVENT23 0x337
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#define CSR_MHPMEVENT24 0x338
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#define CSR_MHPMEVENT25 0x339
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#define CSR_MHPMEVENT26 0x33a
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#define CSR_MHPMEVENT27 0x33b
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#define CSR_MHPMEVENT28 0x33c
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#define CSR_MHPMEVENT29 0x33d
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#define CSR_MHPMEVENT30 0x33e
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#define CSR_MHPMEVENT31 0x33f
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#define CSR_MSCRATCH 0x340
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#define CSR_MEPC 0x341
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#define CSR_MCAUSE 0x342
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#define CSR_MTVAL 0x343
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#define CSR_MIP 0x344
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#define CSR_PMPCFG0 0x3a0
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#define CSR_PMPCFG1 0x3a1
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#define CSR_PMPCFG2 0x3a2
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#define CSR_PMPCFG3 0x3a3
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#define CSR_PMPADDR0 0x3b0
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#define CSR_PMPADDR1 0x3b1
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#define CSR_PMPADDR2 0x3b2
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#define CSR_PMPADDR3 0x3b3
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#define CSR_PMPADDR4 0x3b4
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#define CSR_PMPADDR5 0x3b5
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#define CSR_PMPADDR6 0x3b6
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#define CSR_PMPADDR7 0x3b7
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#define CSR_PMPADDR8 0x3b8
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#define CSR_PMPADDR9 0x3b9
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#define CSR_PMPADDR10 0x3ba
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#define CSR_PMPADDR11 0x3bb
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#define CSR_PMPADDR12 0x3bc
|
||||
#define CSR_PMPADDR13 0x3bd
|
||||
#define CSR_PMPADDR14 0x3be
|
||||
#define CSR_PMPADDR15 0x3bf
|
||||
|
||||
#define CSR_TSELECT 0x7a0
|
||||
#define CSR_TDATA1 0x7a1
|
||||
#define CSR_TDATA2 0x7a2
|
||||
#define CSR_TDATA3 0x7a3
|
||||
#define CSR_DCSR 0x7b0
|
||||
#define CSR_DPC 0x7b1
|
||||
#define CSR_DSCRATCH 0x7b2
|
||||
|
||||
#define CSR_MCYCLE 0xb00
|
||||
#define CSR_MINSTRET 0xb02
|
||||
#define CSR_MHPMCOUNTER3 0xb03
|
||||
#define CSR_MHPMCOUNTER4 0xb04
|
||||
#define CSR_MHPMCOUNTER5 0xb05
|
||||
#define CSR_MHPMCOUNTER6 0xb06
|
||||
#define CSR_MHPMCOUNTER7 0xb07
|
||||
#define CSR_MHPMCOUNTER8 0xb08
|
||||
#define CSR_MHPMCOUNTER9 0xb09
|
||||
#define CSR_MHPMCOUNTER10 0xb0a
|
||||
#define CSR_MHPMCOUNTER11 0xb0b
|
||||
#define CSR_MHPMCOUNTER12 0xb0c
|
||||
#define CSR_MHPMCOUNTER13 0xb0d
|
||||
#define CSR_MHPMCOUNTER14 0xb0e
|
||||
#define CSR_MHPMCOUNTER15 0xb0f
|
||||
#define CSR_MHPMCOUNTER16 0xb10
|
||||
#define CSR_MHPMCOUNTER17 0xb11
|
||||
#define CSR_MHPMCOUNTER18 0xb12
|
||||
#define CSR_MHPMCOUNTER19 0xb13
|
||||
#define CSR_MHPMCOUNTER20 0xb14
|
||||
#define CSR_MHPMCOUNTER21 0xb15
|
||||
#define CSR_MHPMCOUNTER22 0xb16
|
||||
#define CSR_MHPMCOUNTER23 0xb17
|
||||
#define CSR_MHPMCOUNTER24 0xb18
|
||||
#define CSR_MHPMCOUNTER25 0xb19
|
||||
#define CSR_MHPMCOUNTER26 0xb1a
|
||||
#define CSR_MHPMCOUNTER27 0xb1b
|
||||
#define CSR_MHPMCOUNTER28 0xb1c
|
||||
#define CSR_MHPMCOUNTER29 0xb1d
|
||||
#define CSR_MHPMCOUNTER30 0xb1e
|
||||
#define CSR_MHPMCOUNTER31 0xb1f
|
||||
#define CSR_MCYCLEH 0xb80
|
||||
#define CSR_MINSTRETH 0xb82
|
||||
#define CSR_MHPMCOUNTER3H 0xb83
|
||||
#define CSR_MHPMCOUNTER4H 0xb84
|
||||
#define CSR_MHPMCOUNTER5H 0xb85
|
||||
#define CSR_MHPMCOUNTER6H 0xb86
|
||||
#define CSR_MHPMCOUNTER7H 0xb87
|
||||
#define CSR_MHPMCOUNTER8H 0xb88
|
||||
#define CSR_MHPMCOUNTER9H 0xb89
|
||||
#define CSR_MHPMCOUNTER10H 0xb8a
|
||||
#define CSR_MHPMCOUNTER11H 0xb8b
|
||||
#define CSR_MHPMCOUNTER12H 0xb8c
|
||||
#define CSR_MHPMCOUNTER13H 0xb8d
|
||||
#define CSR_MHPMCOUNTER14H 0xb8e
|
||||
#define CSR_MHPMCOUNTER15H 0xb8f
|
||||
#define CSR_MHPMCOUNTER16H 0xb90
|
||||
#define CSR_MHPMCOUNTER17H 0xb91
|
||||
#define CSR_MHPMCOUNTER18H 0xb92
|
||||
#define CSR_MHPMCOUNTER19H 0xb93
|
||||
#define CSR_MHPMCOUNTER20H 0xb94
|
||||
#define CSR_MHPMCOUNTER21H 0xb95
|
||||
#define CSR_MHPMCOUNTER22H 0xb96
|
||||
#define CSR_MHPMCOUNTER23H 0xb97
|
||||
#define CSR_MHPMCOUNTER24H 0xb98
|
||||
#define CSR_MHPMCOUNTER25H 0xb99
|
||||
#define CSR_MHPMCOUNTER26H 0xb9a
|
||||
#define CSR_MHPMCOUNTER27H 0xb9b
|
||||
#define CSR_MHPMCOUNTER28H 0xb9c
|
||||
#define CSR_MHPMCOUNTER29H 0xb9d
|
||||
#define CSR_MHPMCOUNTER30H 0xb9e
|
||||
#define CSR_MHPMCOUNTER31H 0xb9f
|
||||
|
||||
#define CSR_CYCLE 0xc00
|
||||
#define CSR_TIME 0xc01
|
||||
#define CSR_INSTRET 0xc02
|
||||
#define CSR_HPMCOUNTER3 0xc03
|
||||
#define CSR_HPMCOUNTER4 0xc04
|
||||
#define CSR_HPMCOUNTER5 0xc05
|
||||
#define CSR_HPMCOUNTER6 0xc06
|
||||
#define CSR_HPMCOUNTER7 0xc07
|
||||
#define CSR_HPMCOUNTER8 0xc08
|
||||
#define CSR_HPMCOUNTER9 0xc09
|
||||
#define CSR_HPMCOUNTER10 0xc0a
|
||||
#define CSR_HPMCOUNTER11 0xc0b
|
||||
#define CSR_HPMCOUNTER12 0xc0c
|
||||
#define CSR_HPMCOUNTER13 0xc0d
|
||||
#define CSR_HPMCOUNTER14 0xc0e
|
||||
#define CSR_HPMCOUNTER15 0xc0f
|
||||
#define CSR_HPMCOUNTER16 0xc10
|
||||
#define CSR_HPMCOUNTER17 0xc11
|
||||
#define CSR_HPMCOUNTER18 0xc12
|
||||
#define CSR_HPMCOUNTER19 0xc13
|
||||
#define CSR_HPMCOUNTER20 0xc14
|
||||
#define CSR_HPMCOUNTER21 0xc15
|
||||
#define CSR_HPMCOUNTER22 0xc16
|
||||
#define CSR_HPMCOUNTER23 0xc17
|
||||
#define CSR_HPMCOUNTER24 0xc18
|
||||
#define CSR_HPMCOUNTER25 0xc19
|
||||
#define CSR_HPMCOUNTER26 0xc1a
|
||||
#define CSR_HPMCOUNTER27 0xc1b
|
||||
#define CSR_HPMCOUNTER28 0xc1c
|
||||
#define CSR_HPMCOUNTER29 0xc1d
|
||||
#define CSR_HPMCOUNTER30 0xc1e
|
||||
#define CSR_HPMCOUNTER31 0xc1f
|
||||
#define CSR_CYCLEH 0xc80
|
||||
#define CSR_TIMEH 0xc81
|
||||
#define CSR_INSTRETH 0xc82
|
||||
#define CSR_HPMCOUNTER3H 0xc83
|
||||
#define CSR_HPMCOUNTER4H 0xc84
|
||||
#define CSR_HPMCOUNTER5H 0xc85
|
||||
#define CSR_HPMCOUNTER6H 0xc86
|
||||
#define CSR_HPMCOUNTER7H 0xc87
|
||||
#define CSR_HPMCOUNTER8H 0xc88
|
||||
#define CSR_HPMCOUNTER9H 0xc89
|
||||
#define CSR_HPMCOUNTER10H 0xc8a
|
||||
#define CSR_HPMCOUNTER11H 0xc8b
|
||||
#define CSR_HPMCOUNTER12H 0xc8c
|
||||
#define CSR_HPMCOUNTER13H 0xc8d
|
||||
#define CSR_HPMCOUNTER14H 0xc8e
|
||||
#define CSR_HPMCOUNTER15H 0xc8f
|
||||
#define CSR_HPMCOUNTER16H 0xc90
|
||||
#define CSR_HPMCOUNTER17H 0xc91
|
||||
#define CSR_HPMCOUNTER18H 0xc92
|
||||
#define CSR_HPMCOUNTER19H 0xc93
|
||||
#define CSR_HPMCOUNTER20H 0xc94
|
||||
#define CSR_HPMCOUNTER21H 0xc95
|
||||
#define CSR_HPMCOUNTER22H 0xc96
|
||||
#define CSR_HPMCOUNTER23H 0xc97
|
||||
#define CSR_HPMCOUNTER24H 0xc98
|
||||
#define CSR_HPMCOUNTER25H 0xc99
|
||||
#define CSR_HPMCOUNTER26H 0xc9a
|
||||
#define CSR_HPMCOUNTER27H 0xc9b
|
||||
#define CSR_HPMCOUNTER28H 0xc9c
|
||||
#define CSR_HPMCOUNTER29H 0xc9d
|
||||
#define CSR_HPMCOUNTER30H 0xc9e
|
||||
#define CSR_HPMCOUNTER31H 0xc9f
|
||||
|
||||
#define CSR_MVENDORID 0xf11
|
||||
#define CSR_MARCHID 0xf12
|
||||
#define CSR_MIMPID 0xf13
|
||||
#define CSR_MHARTID 0xf14
|
||||
|
||||
#endif /* __riscv */
|
||||
|
||||
#endif /* RISCV_CSR_ENCODING_H */
|
||||
|
|
|
|||
|
|
@ -17,6 +17,8 @@ The support for following drivers are already enabled:
|
|||
1. SiFive UART Driver.
|
||||
2. SiFive PRCI Driver for clock.
|
||||
3. Cadence MACB ethernet driver for networking support.
|
||||
4. SiFive SPI Driver.
|
||||
5. MMC SPI Driver for MMC/SD support.
|
||||
|
||||
TODO:
|
||||
|
||||
|
|
@ -48,14 +50,22 @@ Flashing
|
|||
|
||||
The current U-Boot port is supported in S-mode only and loaded from DRAM.
|
||||
|
||||
A prior stage (M-mode) firmware/bootloader (e.g OpenSBI or BBL) is required to
|
||||
load the u-boot.bin into memory and provide runtime services. The u-boot.bin
|
||||
can be given as a payload to the prior stage (M-mode) firmware/bootloader.
|
||||
A prior stage M-mode firmware/bootloader (e.g OpenSBI) is required to
|
||||
boot the u-boot.bin in S-mode and provide M-mode runtime services.
|
||||
|
||||
The description of steps required to build the firmware is beyond the scope of
|
||||
this document. Please refer OpenSBI or BBL documenation.
|
||||
Currently, the u-boot.bin is used as a payload of the OpenSBI FW_PAYLOAD
|
||||
firmware. We need to compile OpenSBI with below command:
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=<path to u-boot.bin> FW_PAYLOAD_FDT_PATH=<path to hifive-unleashed-a00.dtb from Linux>
|
||||
|
||||
(Note: Prefer hifive-unleashed-a00.dtb from Linux-5.3 or higher)
|
||||
(Note: Linux-5.2 is also fine but it does not have ethernet DT node)
|
||||
|
||||
More detailed description of steps required to build FW_PAYLOAD firmware
|
||||
is beyond the scope of this document. Please refer OpenSBI documenation.
|
||||
(Note: OpenSBI git repo is at https://github.com/riscv/opensbi.git)
|
||||
(Note: BBL git repo is at https://github.com/riscv/riscv-pk.git)
|
||||
|
||||
Once the prior stage firmware/bootloader binary is generated, it should be
|
||||
copied to the first partition of the sdcard.
|
||||
|
|
@ -73,53 +83,70 @@ Sample boot log from HiFive Unleashed board
|
|||
|
||||
.. code-block:: none
|
||||
|
||||
U-Boot 2019.01-00019-gc7953536-dirty (Jan 22 2019 - 11:05:40 -0800)
|
||||
U-Boot 2019.07-00024-g350ff02f5b (Jul 22 2019 - 11:45:02 +0530)
|
||||
|
||||
CPU: rv64imafdc
|
||||
Model: sifive,hifive-unleashed-a00
|
||||
Model: SiFive HiFive Unleashed A00
|
||||
DRAM: 8 GiB
|
||||
MMC: spi@10050000:mmc@0: 0
|
||||
In: serial@10010000
|
||||
Out: serial@10010000
|
||||
Err: serial@10010000
|
||||
Net:
|
||||
Warning: ethernet@10090000 (eth0) using random MAC address - b6:75:4d:48:50:94
|
||||
eth0: ethernet@10090000
|
||||
Net: eth0: ethernet@10090000
|
||||
Hit any key to stop autoboot: 0
|
||||
=> version
|
||||
U-Boot 2019.01-00019-gc7953536-dirty (Jan 22 2019 - 11:05:40 -0800)
|
||||
U-Boot 2019.07-00024-g350ff02f5b (Jul 22 2019 - 11:45:02 +0530)
|
||||
|
||||
riscv64-linux-gcc.br_real (Buildroot 2018.11-rc2-00003-ga0787e9) 8.2.0
|
||||
GNU ld (GNU Binutils) 2.31.1
|
||||
=> mmc info
|
||||
Device: spi@10050000:mmc@0
|
||||
Manufacturer ID: 3
|
||||
OEM: 5344
|
||||
Name: SU08G
|
||||
Bus Speed: 20000000
|
||||
Mode: SD Legacy
|
||||
Rd Block Len: 512
|
||||
SD version 2.0
|
||||
High Capacity: Yes
|
||||
Capacity: 7.4 GiB
|
||||
Bus Width: 1-bit
|
||||
Erase Group Size: 512 Bytes
|
||||
=> mmc part
|
||||
|
||||
Partition Map for MMC device 0 -- Partition Type: EFI
|
||||
|
||||
Part Start LBA End LBA Name
|
||||
Attributes
|
||||
Type GUID
|
||||
Partition GUID
|
||||
1 0x00000800 0x000107ff "bootloader"
|
||||
attrs: 0x0000000000000000
|
||||
type: 2e54b353-1271-4842-806f-e436d6af6985
|
||||
guid: 393bbd36-7111-491c-9869-ce24008f6403
|
||||
2 0x00040800 0x00ecdfde ""
|
||||
attrs: 0x0000000000000000
|
||||
type: 0fc63daf-8483-4772-8e79-3d69d8477de4
|
||||
guid: 7fc9a949-5480-48c7-b623-04923080757f
|
||||
|
||||
Now you can configure your networking, tftp server and use tftp boot method to
|
||||
load uImage.
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
=> setenv ethaddr 70:B3:D5:92:F0:C2
|
||||
=> setenv ipaddr 10.196.157.189
|
||||
=> setenv serverip 10.11.143.218
|
||||
=> setenv gatewayip 10.196.156.1
|
||||
=> setenv ipaddr 10.206.7.133
|
||||
=> setenv netmask 255.255.252.0
|
||||
=> bdinfo
|
||||
boot_params = 0x0000000000000000
|
||||
DRAM bank = 0x0000000000000000
|
||||
-> start = 0x0000000080000000
|
||||
-> size = 0x0000000200000000
|
||||
relocaddr = 0x00000000fff90000
|
||||
reloc off = 0x000000007fd90000
|
||||
ethaddr = 70:B3:D5:92:F0:C2
|
||||
IP addr = 10.196.157.189
|
||||
baudrate = 115200 bps
|
||||
=> tftpboot uImage
|
||||
=> setenv serverip 10.206.4.143
|
||||
=> setenv gateway 10.206.4.1
|
||||
=> tftpboot ${kernel_addr_r} /sifive/fu540/Image
|
||||
ethernet@10090000: PHY present at 0
|
||||
ethernet@10090000: Starting autonegotiation...
|
||||
ethernet@10090000: Autonegotiation complete
|
||||
ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x3800)
|
||||
ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x3c00)
|
||||
Using ethernet@10090000 device
|
||||
TFTP from server 10.11.143.218; our IP address is 10.196.157.189; sending through gateway 10.196.156.1
|
||||
Filename 'uImage'.
|
||||
Load address: 0x80200000
|
||||
TFTP from server 10.206.4.143; our IP address is 10.206.7.133
|
||||
Filename '/sifive/fu540/Image'.
|
||||
Load address: 0x84000000
|
||||
Loading: #################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
|
|
@ -146,175 +173,196 @@ load uImage.
|
|||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
##########################################################
|
||||
2.5 MiB/s
|
||||
##########################################
|
||||
1.2 MiB/s
|
||||
done
|
||||
Bytes transferred = 14939132 (e3f3fc hex)
|
||||
=> bootm 0x80200000 - 0x82200000
|
||||
## Booting kernel from Legacy Image at 80200000 ...
|
||||
Image Name: Linux
|
||||
Image Type: RISC-V Linux Kernel Image (uncompressed)
|
||||
Data Size: 14939068 Bytes = 14.2 MiB
|
||||
Load Address: 80200000
|
||||
Entry Point: 80200000
|
||||
Bytes transferred = 8867100 (874d1c hex)
|
||||
=> tftpboot ${ramdisk_addr_r} /sifive/fu540/uRamdisk
|
||||
ethernet@10090000: PHY present at 0
|
||||
ethernet@10090000: Starting autonegotiation...
|
||||
ethernet@10090000: Autonegotiation complete
|
||||
ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x3c00)
|
||||
Using ethernet@10090000 device
|
||||
TFTP from server 10.206.4.143; our IP address is 10.206.7.133
|
||||
Filename '/sifive/fu540/uRamdisk'.
|
||||
Load address: 0x88300000
|
||||
Loading: #################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
#################################################################
|
||||
##############
|
||||
418.9 KiB/s
|
||||
done
|
||||
Bytes transferred = 2398272 (249840 hex)
|
||||
=> tftpboot ${fdt_addr_r} /sifive/fu540/hifive-unleashed-a00.dtb
|
||||
ethernet@10090000: PHY present at 0
|
||||
ethernet@10090000: Starting autonegotiation...
|
||||
ethernet@10090000: Autonegotiation complete
|
||||
ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x7c00)
|
||||
Using ethernet@10090000 device
|
||||
TFTP from server 10.206.4.143; our IP address is 10.206.7.133
|
||||
Filename '/sifive/fu540/hifive-unleashed-a00.dtb'.
|
||||
Load address: 0x88000000
|
||||
Loading: ##
|
||||
1000 Bytes/s
|
||||
done
|
||||
Bytes transferred = 5614 (15ee hex)
|
||||
=> setenv bootargs "root=/dev/ram rw console=ttySIF0 ip=dhcp earlycon=sbi"
|
||||
=> booti ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}
|
||||
## Loading init Ramdisk from Legacy Image at 88300000 ...
|
||||
Image Name: Linux RootFS
|
||||
Image Type: RISC-V Linux RAMDisk Image (uncompressed)
|
||||
Data Size: 2398208 Bytes = 2.3 MiB
|
||||
Load Address: 00000000
|
||||
Entry Point: 00000000
|
||||
Verifying Checksum ... OK
|
||||
## Flattened Device Tree blob at 82200000
|
||||
Booting using the fdt blob at 0x82200000
|
||||
Loading Kernel Image ... OK
|
||||
Using Device Tree in place at 0000000082200000, end 0000000082205c69
|
||||
## Flattened Device Tree blob at 88000000
|
||||
Booting using the fdt blob at 0x88000000
|
||||
Using Device Tree in place at 0000000088000000, end 00000000880045ed
|
||||
|
||||
Starting kernel ...
|
||||
|
||||
[ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000
|
||||
[ 0.000000] Linux version 5.0.0-rc1-00020-g4b51f736 (atish@jedi-01) (gcc version 7.2.0 (GCC)) #262 SMP Mon Jan 21 17:39:27 PST 2019
|
||||
[ 0.000000] initrd not found or empty - disabling initrd
|
||||
[ 0.000000] Linux version 5.3.0-rc1-00003-g460ac558152f (anup@anup-lab-machine) (gcc version 8.2.0 (Buildroot 2018.11-rc2-00003-ga0787e9)) #6 SMP Mon Jul 22 10:01:01 IST 2019
|
||||
[ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '')
|
||||
[ 0.000000] printk: bootconsole [sbi0] enabled
|
||||
[ 0.000000] Initial ramdisk at: 0x(____ptrval____) (2398208 bytes)
|
||||
[ 0.000000] Zone ranges:
|
||||
[ 0.000000] DMA32 [mem 0x0000000080200000-0x00000000ffffffff]
|
||||
[ 0.000000] Normal [mem 0x0000000100000000-0x000027ffffffffff]
|
||||
[ 0.000000] Normal [mem 0x0000000100000000-0x000000027fffffff]
|
||||
[ 0.000000] Movable zone start for each node
|
||||
[ 0.000000] Early memory node ranges
|
||||
[ 0.000000] node 0: [mem 0x0000000080200000-0x000000027fffffff]
|
||||
[ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x000000027fffffff]
|
||||
[ 0.000000] software IO TLB: mapped [mem 0xfbfff000-0xfffff000] (64MB)
|
||||
[ 0.000000] CPU with hartid=0 has a non-okay status of "masked"
|
||||
[ 0.000000] CPU with hartid=0 has a non-okay status of "masked"
|
||||
[ 0.000000] CPU with hartid=0 is not available
|
||||
[ 0.000000] CPU with hartid=0 is not available
|
||||
[ 0.000000] elf_hwcap is 0x112d
|
||||
[ 0.000000] percpu: Embedded 15 pages/cpu @(____ptrval____) s29720 r0 d31720 u61440
|
||||
[ 0.000000] percpu: Embedded 18 pages/cpu s34584 r8192 d30952 u73728
|
||||
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2067975
|
||||
[ 0.000000] Kernel command line: earlyprintk
|
||||
[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes)
|
||||
[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes)
|
||||
[ 0.000000] Kernel command line: root=/dev/ram rw console=ttySIF0 ip=dhcp earlycon=sbi
|
||||
[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
|
||||
[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
|
||||
[ 0.000000] Sorting __ex_table...
|
||||
[ 0.000000] Memory: 8178760K/8386560K available (3309K kernel code, 248K rwdata, 872K rodata, 9381K init, 763K bss, 207800K reserved, 0K cma-reserved)
|
||||
[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
|
||||
[ 0.000000] Memory: 8182308K/8386560K available (5916K kernel code, 368K rwdata, 1840K rodata, 213K init, 304K bss, 204252K reserved, 0K cma-reserved)
|
||||
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
|
||||
[ 0.000000] rcu: Hierarchical RCU implementation.
|
||||
[ 0.000000] rcu: RCU event tracing is enabled.
|
||||
[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
|
||||
[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
|
||||
[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
|
||||
[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
|
||||
[ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
|
||||
[ 0.000000] plic: mapped 53 interrupts to 4 (out of 9) handlers.
|
||||
[ 0.000000] plic: mapped 53 interrupts with 4 handlers for 9 contexts.
|
||||
[ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [1]
|
||||
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 3526361616960 ns
|
||||
[ 0.000008] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns
|
||||
[ 0.000221] Console: colour dummy device 80x25
|
||||
[ 0.000902] printk: console [tty0] enabled
|
||||
[ 0.000963] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.00 BogoMIPS (lpj=10000)
|
||||
[ 0.001034] pid_max: default: 32768 minimum: 301
|
||||
[ 0.001541] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
[ 0.001912] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
[ 0.003542] rcu: Hierarchical SRCU implementation.
|
||||
[ 0.004347] smp: Bringing up secondary CPUs ...
|
||||
[ 1.040259] CPU1: failed to come online
|
||||
[ 2.080483] CPU2: failed to come online
|
||||
[ 3.120699] CPU3: failed to come online
|
||||
[ 3.120765] smp: Brought up 1 node, 1 CPU
|
||||
[ 3.121923] devtmpfs: initialized
|
||||
[ 3.124649] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
|
||||
[ 3.124727] futex hash table entries: 1024 (order: 4, 65536 bytes)
|
||||
[ 3.125346] random: get_random_u32 called from bucket_table_alloc+0x72/0x172 with crng_init=0
|
||||
[ 3.125578] NET: Registered protocol family 16
|
||||
[ 3.126400] sifive-u54-prci 10000000.prci: Registered U54 core clocks
|
||||
[ 3.126649] sifive-gemgxl-mgmt 100a0000.cadence-gemgxl-mgmt: Registered clock switch 'cadence-gemgxl-mgmt'
|
||||
[ 3.135572] vgaarb: loaded
|
||||
[ 3.135858] SCSI subsystem initialized
|
||||
[ 3.136193] usbcore: registered new interface driver usbfs
|
||||
[ 3.136266] usbcore: registered new interface driver hub
|
||||
[ 3.136348] usbcore: registered new device driver usb
|
||||
[ 3.136446] pps_core: LinuxPPS API ver. 1 registered
|
||||
[ 3.136484] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
[ 3.136575] PTP clock support registered
|
||||
[ 3.137256] clocksource: Switched to clocksource riscv_clocksource
|
||||
[ 3.142711] NET: Registered protocol family 2
|
||||
[ 3.143322] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes)
|
||||
[ 3.143634] TCP established hash table entries: 65536 (order: 7, 524288 bytes)
|
||||
[ 3.145799] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
|
||||
[ 3.149121] TCP: Hash tables configured (established 65536 bind 65536)
|
||||
[ 3.149591] UDP hash table entries: 4096 (order: 5, 131072 bytes)
|
||||
[ 3.150094] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes)
|
||||
[ 3.150781] NET: Registered protocol family 1
|
||||
[ 3.230693] workingset: timestamp_bits=62 max_order=21 bucket_order=0
|
||||
[ 3.241224] io scheduler mq-deadline registered
|
||||
[ 3.241269] io scheduler kyber registered
|
||||
[ 3.242143] sifive_gpio 10060000.gpio: SiFive GPIO chip registered 16 GPIOs
|
||||
[ 3.242357] pwm-sifivem 10020000.pwm: Unable to find controller clock
|
||||
[ 3.242439] pwm-sifivem 10021000.pwm: Unable to find controller clock
|
||||
[ 3.243228] xilinx-pcie 2000000000.pci: PCIe Link is DOWN
|
||||
[ 3.243289] xilinx-pcie 2000000000.pci: host bridge /soc/pci@2000000000 ranges:
|
||||
[ 3.243360] xilinx-pcie 2000000000.pci: No bus range found for /soc/pci@2000000000, using [bus 00-ff]
|
||||
[ 3.243447] xilinx-pcie 2000000000.pci: MEM 0x40000000..0x5fffffff -> 0x40000000
|
||||
[ 3.243591] xilinx-pcie 2000000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 3.243636] pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
[ 3.243676] pci_bus 0000:00: root bus resource [mem 0x40000000-0x5fffffff]
|
||||
[ 3.276547] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 3.277689] 10010000.serial: ttySIF0 at MMIO 0x10010000 (irq = 39, base_baud = 0) is a SiFive UART v0
|
||||
[ 3.786963] printk: console [ttySIF0] enabled
|
||||
[ 3.791504] 10011000.serial: ttySIF1 at MMIO 0x10011000 (irq = 40, base_baud = 0) is a SiFive UART v0
|
||||
[ 3.801251] sifive_spi 10040000.spi: mapped; irq=41, cs=1
|
||||
[ 3.806362] m25p80 spi0.0: unrecognized JEDEC id bytes: 9d, 70, 19
|
||||
[ 3.812084] m25p80: probe of spi0.0 failed with error -2
|
||||
[ 3.817453] sifive_spi 10041000.spi: mapped; irq=42, cs=4
|
||||
[ 3.823027] sifive_spi 10050000.spi: mapped; irq=43, cs=1
|
||||
[ 3.828604] libphy: Fixed MDIO Bus: probed
|
||||
[ 3.832623] macb: GEM doesn't support hardware ptp.
|
||||
[ 3.837196] libphy: MACB_mii_bus: probed
|
||||
[ 4.041156] Microsemi VSC8541 SyncE 10090000.ethernet-ffffffff:00: attached PHY driver [Microsemi VSC8541 SyncE] (mii_bus:phy_addr=10090000.ethernet-ffffffff:00, irq=POLL)
|
||||
[ 4.055779] macb 10090000.ethernet eth0: Cadence GEM rev 0x10070109 at 0x10090000 irq 12 (70:b3:d5:92:f0:c2)
|
||||
[ 4.065780] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
|
||||
[ 4.072033] ehci-pci: EHCI PCI platform driver
|
||||
[ 4.076521] usbcore: registered new interface driver usb-storage
|
||||
[ 4.082843] softdog: initialized. soft_noboot=0 soft_margin=60 sec soft_panic=0 (nowayout=0)
|
||||
[ 4.127465] mmc_spi spi2.0: SD/MMC host mmc0, no DMA, no WP, no poweroff
|
||||
[ 4.133645] usbcore: registered new interface driver usbhid
|
||||
[ 4.138980] usbhid: USB HID core driver
|
||||
[ 4.143017] NET: Registered protocol family 17
|
||||
[ 4.147885] pwm-sifivem 10020000.pwm: SiFive PWM chip registered 4 PWMs
|
||||
[ 4.153945] pwm-sifivem 10021000.pwm: SiFive PWM chip registered 4 PWMs
|
||||
[ 4.186407] Freeing unused kernel memory: 9380K
|
||||
[ 4.190224] This architecture does not have kernel memory protection.
|
||||
[ 4.196609] Run /init as init process
|
||||
Starting logging: OK
|
||||
Starting mdev...
|
||||
[ 4.303785] mmc0: host does not support reading read-only switch, assuming write-enable
|
||||
[ 4.311109] mmc0: new SDHC card on SPI
|
||||
[ 4.317103] mmcblk0: mmc0:0000 SS08G 7.40 GiB
|
||||
[ 4.386471] mmcblk0: p1 p2
|
||||
sort: /sys/devices/platform/Fixed: No such file or directory
|
||||
modprobe: can't change directory to '/lib/modules': No such file or directory
|
||||
Initializing random[ 4.759075] random: dd: uninitialized urandom read (512 bytes read)
|
||||
number generator... done.
|
||||
Starting network...
|
||||
udhcpc (v1.24.2) started
|
||||
Sending discover...
|
||||
Sending discover...
|
||||
[ 7.927510] macb 10090000.ethernet eth0: link up (1000/Full)
|
||||
Sending discover...
|
||||
Sending select for 10.196.157.190...
|
||||
Lease of 10.196.157.190 obtained, lease time 499743
|
||||
deleting routers
|
||||
adding dns 10.86.1.1
|
||||
adding dns 10.86.2.1
|
||||
/etc/init.d/S50dropbear
|
||||
Starting dropbear sshd: [ 12.772393] random: dropbear: uninitialized urandom read (32 bytes read)
|
||||
OK
|
||||
[ 0.000006] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns
|
||||
[ 0.008559] Console: colour dummy device 80x25
|
||||
[ 0.012989] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.00 BogoMIPS (lpj=4000)
|
||||
[ 0.023104] pid_max: default: 32768 minimum: 301
|
||||
[ 0.028273] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
|
||||
[ 0.035765] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
|
||||
[ 0.045307] rcu: Hierarchical SRCU implementation.
|
||||
[ 0.049875] smp: Bringing up secondary CPUs ...
|
||||
[ 0.055729] smp: Brought up 1 node, 4 CPUs
|
||||
[ 0.060599] devtmpfs: initialized
|
||||
[ 0.064819] random: get_random_u32 called from bucket_table_alloc.isra.10+0x4e/0x160 with crng_init=0
|
||||
[ 0.073720] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
|
||||
[ 0.083176] futex hash table entries: 1024 (order: 4, 65536 bytes, linear)
|
||||
[ 0.090721] NET: Registered protocol family 16
|
||||
[ 0.106319] vgaarb: loaded
|
||||
[ 0.108670] SCSI subsystem initialized
|
||||
[ 0.112515] usbcore: registered new interface driver usbfs
|
||||
[ 0.117758] usbcore: registered new interface driver hub
|
||||
[ 0.123167] usbcore: registered new device driver usb
|
||||
[ 0.128905] clocksource: Switched to clocksource riscv_clocksource
|
||||
[ 0.141239] NET: Registered protocol family 2
|
||||
[ 0.145506] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
|
||||
[ 0.153754] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
|
||||
[ 0.163466] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes, linear)
|
||||
[ 0.173468] TCP: Hash tables configured (established 65536 bind 65536)
|
||||
[ 0.179739] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
|
||||
[ 0.186627] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
|
||||
[ 0.194117] NET: Registered protocol family 1
|
||||
[ 0.198417] RPC: Registered named UNIX socket transport module.
|
||||
[ 0.203887] RPC: Registered udp transport module.
|
||||
[ 0.208664] RPC: Registered tcp transport module.
|
||||
[ 0.213429] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
[ 0.219944] PCI: CLS 0 bytes, default 64
|
||||
[ 0.224170] Unpacking initramfs...
|
||||
[ 0.262347] Freeing initrd memory: 2336K
|
||||
[ 0.266531] workingset: timestamp_bits=62 max_order=21 bucket_order=0
|
||||
[ 0.280406] NFS: Registering the id_resolver key type
|
||||
[ 0.284798] Key type id_resolver registered
|
||||
[ 0.289048] Key type id_legacy registered
|
||||
[ 0.293114] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
|
||||
[ 0.300262] NET: Registered protocol family 38
|
||||
[ 0.304432] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
|
||||
[ 0.311862] io scheduler mq-deadline registered
|
||||
[ 0.316461] io scheduler kyber registered
|
||||
[ 0.356421] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 0.363004] 10010000.serial: ttySIF0 at MMIO 0x10010000 (irq = 4, base_baud = 0) is a SiFive UART v0
|
||||
[ 0.371468] printk: console [ttySIF0] enabled
|
||||
[ 0.371468] printk: console [ttySIF0] enabled
|
||||
[ 0.380223] printk: bootconsole [sbi0] disabled
|
||||
[ 0.380223] printk: bootconsole [sbi0] disabled
|
||||
[ 0.389589] 10011000.serial: ttySIF1 at MMIO 0x10011000 (irq = 1, base_baud = 0) is a SiFive UART v0
|
||||
[ 0.398680] [drm] radeon kernel modesetting enabled.
|
||||
[ 0.412395] loop: module loaded
|
||||
[ 0.415214] sifive_spi 10040000.spi: mapped; irq=3, cs=1
|
||||
[ 0.420628] sifive_spi 10050000.spi: mapped; irq=5, cs=1
|
||||
[ 0.425897] libphy: Fixed MDIO Bus: probed
|
||||
[ 0.429964] macb 10090000.ethernet: Registered clk switch 'sifive-gemgxl-mgmt'
|
||||
[ 0.436743] macb: GEM doesn't support hardware ptp.
|
||||
[ 0.441621] libphy: MACB_mii_bus: probed
|
||||
[ 0.601316] Microsemi VSC8541 SyncE 10090000.ethernet-ffffffff:00: attached PHY driver [Microsemi VSC8541 SyncE] (mii_bus:phy_addr=10090000.ethernet-ffffffff:00, irq=POLL)
|
||||
[ 0.615857] macb 10090000.ethernet eth0: Cadence GEM rev 0x10070109 at 0x10090000 irq 6 (70:b3:d5:92:f2:f3)
|
||||
[ 0.625634] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
|
||||
[ 0.631381] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
|
||||
[ 0.637382] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
|
||||
[ 0.643799] ehci-pci: EHCI PCI platform driver
|
||||
[ 0.648261] ehci-platform: EHCI generic platform driver
|
||||
[ 0.653497] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
|
||||
[ 0.659599] ohci-pci: OHCI PCI platform driver
|
||||
[ 0.664055] ohci-platform: OHCI generic platform driver
|
||||
[ 0.669448] usbcore: registered new interface driver uas
|
||||
[ 0.674575] usbcore: registered new interface driver usb-storage
|
||||
[ 0.680642] mousedev: PS/2 mouse device common for all mice
|
||||
[ 0.709493] mmc_spi spi1.0: SD/MMC host mmc0, no DMA, no WP, no poweroff, cd polling
|
||||
[ 0.716615] usbcore: registered new interface driver usbhid
|
||||
[ 0.722023] usbhid: USB HID core driver
|
||||
[ 0.726738] NET: Registered protocol family 10
|
||||
[ 0.731359] Segment Routing with IPv6
|
||||
[ 0.734332] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
|
||||
[ 0.740687] NET: Registered protocol family 17
|
||||
[ 0.744660] Key type dns_resolver registered
|
||||
[ 0.806775] mmc0: host does not support reading read-only switch, assuming write-enable
|
||||
[ 0.814020] mmc0: new SDHC card on SPI
|
||||
[ 0.820137] mmcblk0: mmc0:0000 SU08G 7.40 GiB
|
||||
[ 0.850220] mmcblk0: p1 p2
|
||||
[ 3.821524] macb 10090000.ethernet eth0: link up (1000/Full)
|
||||
[ 3.828938] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
|
||||
[ 3.848919] Sending DHCP requests .., OK
|
||||
[ 6.252076] IP-Config: Got DHCP answer from 10.206.4.1, my address is 10.206.7.133
|
||||
[ 6.259624] IP-Config: Complete:
|
||||
[ 6.262831] device=eth0, hwaddr=70:b3:d5:92:f2:f3, ipaddr=10.206.7.133, mask=255.255.252.0, gw=10.206.4.1
|
||||
[ 6.272809] host=dhcp-10-206-7-133, domain=sdcorp.global.sandisk.com, nis-domain=(none)
|
||||
[ 6.281228] bootserver=10.206.126.11, rootserver=10.206.126.11, rootpath=
|
||||
[ 6.281232] nameserver0=10.86.1.1, nameserver1=10.86.2.1
|
||||
[ 6.294179] ntpserver0=10.86.1.1, ntpserver1=10.86.2.1
|
||||
[ 6.301026] Freeing unused kernel memory: 212K
|
||||
[ 6.304683] This architecture does not have kernel memory protection.
|
||||
[ 6.311121] Run /init as init process
|
||||
_ _
|
||||
| ||_|
|
||||
| | _ ____ _ _ _ _
|
||||
| || | _ \| | | |\ \/ /
|
||||
| || | | | | |_| |/ \
|
||||
|_||_|_| |_|\____|\_/\_/
|
||||
|
||||
Welcome to Buildroot
|
||||
buildroot login:
|
||||
Busybox Rootfs
|
||||
|
||||
Please press Enter to activate this console.
|
||||
/ #
|
||||
|
|
|
|||
|
|
@ -22,6 +22,9 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
#define UART_TXCTRL_TXEN 0x1
|
||||
#define UART_RXCTRL_RXEN 0x1
|
||||
|
||||
/* IP register */
|
||||
#define UART_IP_RXWM 0x2
|
||||
|
||||
struct uart_sifive {
|
||||
u32 txfifo;
|
||||
u32 rxfifo;
|
||||
|
|
@ -34,7 +37,6 @@ struct uart_sifive {
|
|||
|
||||
struct sifive_uart_platdata {
|
||||
unsigned long clock;
|
||||
int saved_input_char;
|
||||
struct uart_sifive *regs;
|
||||
};
|
||||
|
||||
|
|
@ -94,7 +96,7 @@ static int _sifive_serial_getc(struct uart_sifive *regs)
|
|||
return -EAGAIN;
|
||||
ch &= UART_RXFIFO_DATA;
|
||||
|
||||
return (!ch) ? -EAGAIN : ch;
|
||||
return ch;
|
||||
}
|
||||
|
||||
static int sifive_serial_setbrg(struct udevice *dev, int baudrate)
|
||||
|
|
@ -133,7 +135,6 @@ static int sifive_serial_probe(struct udevice *dev)
|
|||
if (gd->flags & GD_FLG_RELOC)
|
||||
return 0;
|
||||
|
||||
platdata->saved_input_char = 0;
|
||||
_sifive_serial_init(platdata->regs);
|
||||
|
||||
return 0;
|
||||
|
|
@ -145,12 +146,6 @@ static int sifive_serial_getc(struct udevice *dev)
|
|||
struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
|
||||
struct uart_sifive *regs = platdata->regs;
|
||||
|
||||
if (platdata->saved_input_char > 0) {
|
||||
c = platdata->saved_input_char;
|
||||
platdata->saved_input_char = 0;
|
||||
return c;
|
||||
}
|
||||
|
||||
while ((c = _sifive_serial_getc(regs)) == -EAGAIN) ;
|
||||
|
||||
return c;
|
||||
|
|
@ -171,14 +166,10 @@ static int sifive_serial_pending(struct udevice *dev, bool input)
|
|||
struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
|
||||
struct uart_sifive *regs = platdata->regs;
|
||||
|
||||
if (input) {
|
||||
if (platdata->saved_input_char > 0)
|
||||
return 1;
|
||||
platdata->saved_input_char = _sifive_serial_getc(regs);
|
||||
return (platdata->saved_input_char > 0) ? 1 : 0;
|
||||
} else {
|
||||
if (input)
|
||||
return (readl(®s->ip) & UART_IP_RXWM);
|
||||
else
|
||||
return !!(readl(®s->txfifo) & UART_TXFIFO_FULL);
|
||||
}
|
||||
}
|
||||
|
||||
static int sifive_serial_ofdata_to_platdata(struct udevice *dev)
|
||||
|
|
|
|||
|
|
@ -8,10 +8,6 @@
|
|||
* without fixup. Both RV32 and RV64 are supported.
|
||||
*/
|
||||
|
||||
#if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__
|
||||
#error "Only little-endian host is supported"
|
||||
#endif
|
||||
|
||||
#include <errno.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
|
@ -25,6 +21,7 @@
|
|||
#include <sys/stat.h>
|
||||
#include <sys/types.h>
|
||||
#include <unistd.h>
|
||||
#include <compiler.h>
|
||||
|
||||
#ifndef EM_RISCV
|
||||
#define EM_RISCV 243
|
||||
|
|
@ -50,12 +47,28 @@ const char *argv0;
|
|||
exit(EXIT_FAILURE); \
|
||||
} while (0)
|
||||
|
||||
#define PRELINK_BYTEORDER le
|
||||
#define PRELINK_INC_BITS 32
|
||||
#include "prelink-riscv.inc"
|
||||
#undef PRELINK_BYTEORDER
|
||||
#undef PRELINK_INC_BITS
|
||||
|
||||
#define PRELINK_BYTEORDER le
|
||||
#define PRELINK_INC_BITS 64
|
||||
#include "prelink-riscv.inc"
|
||||
#undef PRELINK_BYTEORDER
|
||||
#undef PRELINK_INC_BITS
|
||||
|
||||
#define PRELINK_BYTEORDER be
|
||||
#define PRELINK_INC_BITS 32
|
||||
#include "prelink-riscv.inc"
|
||||
#undef PRELINK_BYTEORDER
|
||||
#undef PRELINK_INC_BITS
|
||||
|
||||
#define PRELINK_BYTEORDER be
|
||||
#define PRELINK_INC_BITS 64
|
||||
#include "prelink-riscv.inc"
|
||||
#undef PRELINK_BYTEORDER
|
||||
#undef PRELINK_INC_BITS
|
||||
|
||||
int main(int argc, const char *const *argv)
|
||||
|
|
@ -91,11 +104,19 @@ int main(int argc, const char *const *argv)
|
|||
die("Invalid ELF file %s", argv[1]);
|
||||
|
||||
bool is64 = e_ident[EI_CLASS] == ELFCLASS64;
|
||||
bool isbe = e_ident[EI_DATA] == ELFDATA2MSB;
|
||||
|
||||
if (is64)
|
||||
prelink64(data);
|
||||
else
|
||||
prelink32(data);
|
||||
if (is64) {
|
||||
if (isbe)
|
||||
prelink_be64(data);
|
||||
else
|
||||
prelink_le64(data);
|
||||
} else {
|
||||
if (isbe)
|
||||
prelink_be32(data);
|
||||
else
|
||||
prelink_le32(data);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -12,9 +12,9 @@
|
|||
#define CONCAT(x, y) CONCAT_IMPL(x, y)
|
||||
#define CONCAT3(x, y, z) CONCAT(CONCAT(x, y), z)
|
||||
|
||||
#define prelink_nn CONCAT(prelink, PRELINK_INC_BITS)
|
||||
#define prelink_bonn CONCAT3(prelink_, PRELINK_BYTEORDER, PRELINK_INC_BITS)
|
||||
#define uintnn_t CONCAT3(uint, PRELINK_INC_BITS, _t)
|
||||
#define get_offset_nn CONCAT(get_offset_, PRELINK_INC_BITS)
|
||||
#define get_offset_bonn CONCAT3(get_offset_, PRELINK_BYTEORDER, PRELINK_INC_BITS)
|
||||
#define Elf_Ehdr CONCAT3(Elf, PRELINK_INC_BITS, _Ehdr)
|
||||
#define Elf_Phdr CONCAT3(Elf, PRELINK_INC_BITS, _Phdr)
|
||||
#define Elf_Rela CONCAT3(Elf, PRELINK_INC_BITS, _Rela)
|
||||
|
|
@ -23,34 +23,38 @@
|
|||
#define Elf_Addr CONCAT3(Elf, PRELINK_INC_BITS, _Addr)
|
||||
#define ELF_R_TYPE CONCAT3(ELF, PRELINK_INC_BITS, _R_TYPE)
|
||||
#define ELF_R_SYM CONCAT3(ELF, PRELINK_INC_BITS, _R_SYM)
|
||||
#define target16_to_cpu CONCAT(PRELINK_BYTEORDER, 16_to_cpu)
|
||||
#define target32_to_cpu CONCAT(PRELINK_BYTEORDER, 32_to_cpu)
|
||||
#define target64_to_cpu CONCAT(PRELINK_BYTEORDER, 64_to_cpu)
|
||||
#define targetnn_to_cpu CONCAT3(PRELINK_BYTEORDER, PRELINK_INC_BITS, _to_cpu)
|
||||
|
||||
static void* get_offset_nn (void* data, Elf_Phdr* phdrs, size_t phnum, Elf_Addr addr)
|
||||
static void* get_offset_bonn (void* data, Elf_Phdr* phdrs, size_t phnum, Elf_Addr addr)
|
||||
{
|
||||
Elf_Phdr *p;
|
||||
|
||||
for (p = phdrs; p < phdrs + phnum; ++p)
|
||||
if (p->p_vaddr <= addr && p->p_vaddr + p->p_memsz > addr)
|
||||
return data + p->p_offset + (addr - p->p_vaddr);
|
||||
if (targetnn_to_cpu(p->p_vaddr) <= addr && targetnn_to_cpu(p->p_vaddr) + targetnn_to_cpu(p->p_memsz) > addr)
|
||||
return data + targetnn_to_cpu(p->p_offset) + (addr - targetnn_to_cpu(p->p_vaddr));
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void prelink_nn(void *data)
|
||||
static void prelink_bonn(void *data)
|
||||
{
|
||||
Elf_Ehdr *ehdr = data;
|
||||
Elf_Phdr *p;
|
||||
Elf_Dyn *dyn;
|
||||
Elf_Rela *r;
|
||||
|
||||
if (ehdr->e_machine != EM_RISCV)
|
||||
if (target16_to_cpu(ehdr->e_machine) != EM_RISCV)
|
||||
die("Machine type is not RISC-V");
|
||||
|
||||
Elf_Phdr *phdrs = data + ehdr->e_phoff;
|
||||
Elf_Phdr *phdrs = data + targetnn_to_cpu(ehdr->e_phoff);
|
||||
|
||||
Elf_Dyn *dyns = NULL;
|
||||
for (p = phdrs; p < phdrs + ehdr->e_phnum; ++p) {
|
||||
if (p->p_type == PT_DYNAMIC) {
|
||||
dyns = data + p->p_offset;
|
||||
for (p = phdrs; p < phdrs + target16_to_cpu(ehdr->e_phnum); ++p) {
|
||||
if (target32_to_cpu(p->p_type) == PT_DYNAMIC) {
|
||||
dyns = data + targetnn_to_cpu(p->p_offset);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -62,14 +66,14 @@ static void prelink_nn(void *data)
|
|||
size_t rela_count = 0;
|
||||
Elf_Sym *dynsym = NULL;
|
||||
for (dyn = dyns;; ++dyn) {
|
||||
if (dyn->d_tag == DT_NULL)
|
||||
if (targetnn_to_cpu(dyn->d_tag) == DT_NULL)
|
||||
break;
|
||||
else if (dyn->d_tag == DT_RELA)
|
||||
rela_dyn = get_offset_nn(data, phdrs, ehdr->e_phnum, + dyn->d_un.d_ptr);
|
||||
else if (dyn->d_tag == DT_RELASZ)
|
||||
rela_count = dyn->d_un.d_val / sizeof(Elf_Rela);
|
||||
else if (dyn->d_tag == DT_SYMTAB)
|
||||
dynsym = get_offset_nn(data, phdrs, ehdr->e_phnum, + dyn->d_un.d_ptr);
|
||||
else if (targetnn_to_cpu(dyn->d_tag) == DT_RELA)
|
||||
rela_dyn = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), + targetnn_to_cpu(dyn->d_un.d_ptr));
|
||||
else if (targetnn_to_cpu(dyn->d_tag) == DT_RELASZ)
|
||||
rela_count = targetnn_to_cpu(dyn->d_un.d_val) / sizeof(Elf_Rela);
|
||||
else if (targetnn_to_cpu(dyn->d_tag) == DT_SYMTAB)
|
||||
dynsym = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), + targetnn_to_cpu(dyn->d_un.d_ptr));
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -80,23 +84,23 @@ static void prelink_nn(void *data)
|
|||
die("No .dynsym found");
|
||||
|
||||
for (r = rela_dyn; r < rela_dyn + rela_count; ++r) {
|
||||
void* buf = get_offset_nn(data, phdrs, ehdr->e_phnum, r->r_offset);
|
||||
void* buf = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), targetnn_to_cpu(r->r_offset));
|
||||
|
||||
if (buf == NULL)
|
||||
continue;
|
||||
|
||||
if (ELF_R_TYPE(r->r_info) == R_RISCV_RELATIVE)
|
||||
if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_RELATIVE)
|
||||
*((uintnn_t*) buf) = r->r_addend;
|
||||
else if (ELF_R_TYPE(r->r_info) == R_RISCV_32)
|
||||
*((uint32_t*) buf) = dynsym[ELF_R_SYM(r->r_info)].st_value;
|
||||
else if (ELF_R_TYPE(r->r_info) == R_RISCV_64)
|
||||
*((uint64_t*) buf) = dynsym[ELF_R_SYM(r->r_info)].st_value;
|
||||
else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_32)
|
||||
*((uint32_t*) buf) = dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value;
|
||||
else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_64)
|
||||
*((uint64_t*) buf) = dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value;
|
||||
}
|
||||
}
|
||||
|
||||
#undef prelink_nn
|
||||
#undef prelink_bonn
|
||||
#undef uintnn_t
|
||||
#undef get_offset_nn
|
||||
#undef get_offset_bonn
|
||||
#undef Elf_Ehdr
|
||||
#undef Elf_Phdr
|
||||
#undef Elf_Rela
|
||||
|
|
@ -105,6 +109,10 @@ static void prelink_nn(void *data)
|
|||
#undef Elf_Addr
|
||||
#undef ELF_R_TYPE
|
||||
#undef ELF_R_SYM
|
||||
#undef target16_to_cpu
|
||||
#undef target32_to_cpu
|
||||
#undef target64_to_cpu
|
||||
#undef targetnn_to_cpu
|
||||
|
||||
#undef CONCAT_IMPL
|
||||
#undef CONCAT
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue