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mx6: soc: Introduce set_ldo_voltage()
Introduce set_ldo_voltage() so that all three LDO regulators can be configured. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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1 changed files with 26 additions and 7 deletions
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@ -19,6 +19,12 @@
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/crm_regs.h>
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enum ldo_reg {
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LDO_ARM,
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LDO_SOC,
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LDO_PU,
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};
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struct scu_regs {
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struct scu_regs {
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u32 ctrl;
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u32 ctrl;
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u32 config;
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u32 config;
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@ -115,10 +121,11 @@ static void clear_ldo_ramp(void)
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* Possible values are from 0.725V to 1.450V in steps of
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* Possible values are from 0.725V to 1.450V in steps of
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* 0.025V (25mV).
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* 0.025V (25mV).
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*/
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*/
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static void set_vddsoc(u32 mv)
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static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
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{
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{
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struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
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struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
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u32 val, reg = readl(&anatop->reg_core);
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u32 val, reg = readl(&anatop->reg_core);
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u8 shift;
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if (mv < 725)
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if (mv < 725)
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val = 0x00; /* Power gated off */
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val = 0x00; /* Power gated off */
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@ -129,12 +136,24 @@ static void set_vddsoc(u32 mv)
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clear_ldo_ramp();
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clear_ldo_ramp();
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/*
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switch (ldo) {
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* Mask out the REG_CORE[22:18] bits (REG2_TRIG)
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case LDO_SOC:
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* and set them to the calculated value (0.7V + val * 0.25V)
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shift = 18;
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*/
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break;
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reg = (reg & ~(0x1F << 18)) | (val << 18);
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case LDO_PU:
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shift = 9;
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break;
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case LDO_ARM:
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shift = 0;
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break;
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default:
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return -EINVAL;
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}
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reg = (reg & ~(0x1F << shift)) | (val << shift);
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writel(reg, &anatop->reg_core);
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writel(reg, &anatop->reg_core);
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return 0;
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}
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}
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static void imx_set_wdog_powerdown(bool enable)
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static void imx_set_wdog_powerdown(bool enable)
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@ -151,7 +170,7 @@ int arch_cpu_init(void)
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{
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{
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init_aips();
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init_aips();
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set_vddsoc(1175); /* Set VDDSOC to 1.175V */
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set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
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imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
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imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
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