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pci: layerscape: add LS2088A series SoC pcie support
The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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3 changed files with 89 additions and 0 deletions
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@ -89,6 +89,49 @@ static inline void early_mmu_setup(void)
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set_sctlr(get_sctlr() | CR_M);
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set_sctlr(get_sctlr() | CR_M);
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}
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}
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static void fix_pcie_mmu_map(void)
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{
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#ifdef CONFIG_LS2080A
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unsigned int i;
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u32 svr, ver;
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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svr = gur_in32(&gur->svr);
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ver = SVR_SOC_VER(svr);
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/* Fix PCIE base and size for LS2088A */
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if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
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(ver == SVR_LS2048A) || (ver == SVR_LS2044A)) {
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for (i = 0; i < ARRAY_SIZE(final_map); i++) {
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switch (final_map[i].phys) {
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case CONFIG_SYS_PCIE1_PHYS_ADDR:
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final_map[i].phys = 0x2000000000ULL;
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final_map[i].virt = 0x2000000000ULL;
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final_map[i].size = 0x800000000ULL;
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break;
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case CONFIG_SYS_PCIE2_PHYS_ADDR:
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final_map[i].phys = 0x2800000000ULL;
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final_map[i].virt = 0x2800000000ULL;
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final_map[i].size = 0x800000000ULL;
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break;
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case CONFIG_SYS_PCIE3_PHYS_ADDR:
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final_map[i].phys = 0x3000000000ULL;
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final_map[i].virt = 0x3000000000ULL;
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final_map[i].size = 0x800000000ULL;
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break;
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case CONFIG_SYS_PCIE4_PHYS_ADDR:
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final_map[i].phys = 0x3800000000ULL;
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final_map[i].virt = 0x3800000000ULL;
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final_map[i].size = 0x800000000ULL;
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break;
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default:
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break;
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}
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}
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}
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#endif
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}
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/*
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/*
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* The final tables look similar to early tables, but different in detail.
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* The final tables look similar to early tables, but different in detail.
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* These tables are in DRAM. Sub tables are added to enable cache for
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* These tables are in DRAM. Sub tables are added to enable cache for
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@ -103,6 +146,9 @@ static inline void final_mmu_setup(void)
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unsigned int el = current_el();
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unsigned int el = current_el();
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int index;
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int index;
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/* fix the final_map before filling in the block entries */
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fix_pcie_mmu_map();
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mem_map = final_map;
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mem_map = final_map;
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/* Update mapping for DDR to actual size */
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/* Update mapping for DDR to actual size */
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@ -167,6 +167,27 @@ static void ls_pcie_setup_atu(struct ls_pcie *pcie)
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pci_get_regions(pcie->bus, &io, &mem, &pref);
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pci_get_regions(pcie->bus, &io, &mem, &pref);
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idx = PCIE_ATU_REGION_INDEX1 + 1;
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idx = PCIE_ATU_REGION_INDEX1 + 1;
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/* Fix the pcie memory map for LS2088A series SoCs */
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svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
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if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
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svr == SVR_LS2048A || svr == SVR_LS2044A) {
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if (io)
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io->phys_start = (io->phys_start &
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(PCIE_PHYS_SIZE - 1)) +
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LS2088A_PCIE1_PHYS_ADDR +
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LS2088A_PCIE_PHYS_SIZE * pcie->idx;
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if (mem)
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mem->phys_start = (mem->phys_start &
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(PCIE_PHYS_SIZE - 1)) +
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LS2088A_PCIE1_PHYS_ADDR +
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LS2088A_PCIE_PHYS_SIZE * pcie->idx;
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if (pref)
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pref->phys_start = (pref->phys_start &
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(PCIE_PHYS_SIZE - 1)) +
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LS2088A_PCIE1_PHYS_ADDR +
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LS2088A_PCIE_PHYS_SIZE * pcie->idx;
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}
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if (io)
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if (io)
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/* ATU : OUTBOUND : IO */
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/* ATU : OUTBOUND : IO */
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ls_pcie_atu_outbound_set(pcie, idx++,
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ls_pcie_atu_outbound_set(pcie, idx++,
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@ -449,6 +470,7 @@ static int ls_pcie_probe(struct udevice *dev)
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u8 header_type;
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u8 header_type;
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u16 link_sta;
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u16 link_sta;
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bool ep_mode;
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bool ep_mode;
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uint svr;
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int ret;
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int ret;
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pcie->bus = dev;
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pcie->bus = dev;
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@ -502,6 +524,19 @@ static int ls_pcie_probe(struct udevice *dev)
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return ret;
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return ret;
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}
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}
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/*
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* Fix the pcie memory map address and PF control registers address
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* for LS2088A series SoCs
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*/
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svr = get_svr();
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svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
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if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
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svr == SVR_LS2048A || svr == SVR_LS2044A) {
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pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
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LS2088A_PCIE_PHYS_SIZE * pcie->idx;
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pcie->ctrl = pcie->lut + 0x40000;
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}
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pcie->cfg0 = map_physmem(pcie->cfg_res.start,
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pcie->cfg0 = map_physmem(pcie->cfg_res.start,
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fdt_resource_size(&pcie->cfg_res),
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fdt_resource_size(&pcie->cfg_res),
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MAP_NOCACHE);
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MAP_NOCACHE);
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@ -26,6 +26,10 @@
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#define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR
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#define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR
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#endif
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#endif
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#define PCIE_PHYS_SIZE 0x200000000
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#define LS2088A_PCIE_PHYS_SIZE 0x800000000
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#define LS2088A_PCIE1_PHYS_ADDR 0x2000000000
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/* iATU registers */
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/* iATU registers */
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#define PCIE_ATU_VIEWPORT 0x900
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#define PCIE_ATU_VIEWPORT 0x900
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#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
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#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
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@ -109,6 +113,10 @@
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#define SVR_LS102XA 0
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#define SVR_LS102XA 0
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#define SVR_VAR_PER_SHIFT 8
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#define SVR_VAR_PER_SHIFT 8
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#define SVR_LS102XA_MASK 0x700
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#define SVR_LS102XA_MASK 0x700
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#define SVR_LS2088A 0x870900
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#define SVR_LS2084A 0x870910
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#define SVR_LS2048A 0x870920
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#define SVR_LS2044A 0x870930
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/* LS1021a PCIE space */
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/* LS1021a PCIE space */
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#define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL
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#define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL
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