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Add support for NetSilicon NS7520 processor.

Browse source 
Patch by Art Shipkowski, 12 May 2005

Cleanup.
This commit is contained in:
Wolfgang Denk 2005-10-09 01:41:48 +02:00
parent 7521af1c7d
commit 3df5bea0b0
19 changed files with 3290 additions and 1949 deletions
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5
CHANGELOG
View file

@ -2,6 +2,11 @@
Changes for U-Boot 1.1.4:
======================================================================
* Cleanup
* Add support for NetSilicon NS7520 processor.
Patch by Art Shipkowski, 12 May 2005
* Add support for AP1000 board.
Patch by James MacAulay, 07 Oct 2005

4
CREDITS
View file

@ -377,6 +377,10 @@ N: Robert Schwebel
E: r.schwebel@pengutronix.de
D: Support for csb226, logodl and innokom boards (PXA2xx)
N: Art Shipkowski
E: art@videon-central.com
D: Support for NetSilicon NS7520
N: Yasushi Shoji
E: yashi@atmark-techno.com
D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board

325
board/amirix/ap1000/ap1000.c
View file

@ -42,87 +42,71 @@ int checkboard (void)
/* After a loadace command, the SystemAce control register is left in a wonky state. */
/* this code did not work in board_pre_init */
unsigned char *p = (unsigned char *) AP1000_SYSACE_REGBASE;
p[SYSACE_CTRLREG0] = 0x0;
/* add platform and device to banner */
switch (get_device ()) {
case AP1xx_AP107_TARGET:{
case AP1xx_AP107_TARGET:
puts (AP1xx_AP107_TARGET_STR);
break;
}
case AP1xx_AP120_TARGET:{
case AP1xx_AP120_TARGET:
puts (AP1xx_AP120_TARGET_STR);
break;
}
case AP1xx_AP130_TARGET:{
case AP1xx_AP130_TARGET:
puts (AP1xx_AP130_TARGET_STR);
break;
}
case AP1xx_AP1070_TARGET:{
case AP1xx_AP1070_TARGET:
puts (AP1xx_AP1070_TARGET_STR);
break;
}
case AP1xx_AP1100_TARGET:{
case AP1xx_AP1100_TARGET:
puts (AP1xx_AP1100_TARGET_STR);
break;
}
default:{
default:
puts (AP1xx_UNKNOWN_STR);
break;
}
}
puts (AP1xx_TARGET_STR);
puts (" with ");
switch (get_platform ()) {
case AP100_BASELINE_PLATFORM:
case AP1000_BASELINE_PLATFORM:{
case AP1000_BASELINE_PLATFORM:
puts (AP1xx_BASELINE_PLATFORM_STR);
break;
}
case AP1xx_QUADGE_PLATFORM:{
case AP1xx_QUADGE_PLATFORM:
puts (AP1xx_QUADGE_PLATFORM_STR);
break;
}
case AP1xx_MGT_REF_PLATFORM:{
case AP1xx_MGT_REF_PLATFORM:
puts (AP1xx_MGT_REF_PLATFORM_STR);
break;
}
case AP1xx_STANDARD_PLATFORM:{
case AP1xx_STANDARD_PLATFORM:
puts (AP1xx_STANDARD_PLATFORM_STR);
break;
}
case AP1xx_DUAL_PLATFORM:{
case AP1xx_DUAL_PLATFORM:
puts (AP1xx_DUAL_PLATFORM_STR);
break;
}
case AP1xx_BASE_SRAM_PLATFORM:{
case AP1xx_BASE_SRAM_PLATFORM:
puts (AP1xx_BASE_SRAM_PLATFORM_STR);
break;
}
case AP1xx_PCI_PCB_TESTPLATFORM:
case AP1000_PCI_PCB_TESTPLATFORM:{
case AP1000_PCI_PCB_TESTPLATFORM:
puts (AP1xx_PCI_PCB_TESTPLATFORM_STR);
break;
}
case AP1xx_DUAL_GE_MEZZ_TESTPLATFORM:{
case AP1xx_DUAL_GE_MEZZ_TESTPLATFORM:
puts (AP1xx_DUAL_GE_MEZZ_TESTPLATFORM_STR);
break;
}
case AP1xx_SFP_MEZZ_TESTPLATFORM:{
case AP1xx_SFP_MEZZ_TESTPLATFORM:
puts (AP1xx_SFP_MEZZ_TESTPLATFORM_STR);
break;
}
default:{
default:
puts (AP1xx_UNKNOWN_STR);
break;
}
}
if ((get_platform () & AP1xx_TESTPLATFORM_MASK) != 0) {
puts (AP1xx_TESTPLATFORM_STR);
}
else{
} else {
puts (AP1xx_PLATFORM_STR);
}
@ -158,25 +142,27 @@ long int initdram (int board_type)
s += 2;
}
return simple_strtoul (s, NULL, 16);
}
else{
} else {
/* give all 64 MB */
return 64 * 1024 * 1024;
}
}
unsigned int get_platform(void){
unsigned int get_platform (void)
{
unsigned int *revision_reg_ptr = (unsigned int *) AP1xx_FPGA_REV_ADDR;
return (*revision_reg_ptr & AP1xx_PLATFORM_MASK);
}
unsigned int get_device(void){
unsigned int get_device (void)
{
unsigned int *revision_reg_ptr = (unsigned int *) AP1xx_FPGA_REV_ADDR;
return (*revision_reg_ptr & AP1xx_TARGET_MASK);
}
#if 0 // loadace is not working; it appears to be a hardware issue with the system ace.
#if 0 /* loadace is not working; it appears to be a hardware issue with the system ace. */
/*
This function loads FPGA configurations from the SystemACE CompactFlash
*/
@ -192,19 +178,19 @@ int do_loadace (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 1;
}
// reset configuration controller: | 0x80
// select cpflash & ~0x40
// cfg start | 0x20
// wait for cfgstart & ~0x10
// force cfgmode: | 0x08
// do no force cfgaddr: & ~0x04
// clear mpulock: & ~0x02
// do not force lock request & ~0x01
/* reset configuration controller: | 0x80 */
/* select cpflash & ~0x40 */
/* cfg start | 0x20 */
/* wait for cfgstart & ~0x10 */
/* force cfgmode: | 0x08 */
/* do no force cfgaddr: & ~0x04 */
/* clear mpulock: & ~0x02 */
/* do not force lock request & ~0x01 */
p[SYSACE_CTRLREG0] = 0x80 | 0x20 | 0x08;
p[SYSACE_CTRLREG1] = 0x00;
// force config address if arg2 exists
/* force config address if arg2 exists */
if (argc == 2) {
cfg = simple_strtoul (argv[1], NULL, 10);
@ -213,9 +199,9 @@ int do_loadace (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
p[SYSACE_CTRLREG0] = 0x00;
return 1;
}
// Set config address
/* Set config address */
p[SYSACE_CTRLREG1] = (cfg << 5);
// force cfgaddr
/* force cfgaddr */
p[SYSACE_CTRLREG0] |= 0x04;
} else {
@ -230,8 +216,8 @@ int do_loadace (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
while ((p[SYSACE_STATREG1] & 0x01) == 0) {
if (p[SYSACE_ERRREG0] & 0x80) {
// attempting to load an invalid configuration makes the cpflash
// appear to be removed. Reset here to avoid that problem
/* attempting to load an invalid configuration makes the cpflash */
/* appear to be removed. Reset here to avoid that problem */
p[SYSACE_CTRLREG0] = 0x80;
printf ("\nConfiguration %d Read Error\n\n", cfg);
p[SYSACE_CTRLREG0] = 0x00;
@ -260,7 +246,8 @@ int do_loadace (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
* -1 if failed
* </pre>
*/
int do_swconfigbyte(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
int do_swconfigbyte (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
unsigned char *sector_buffer = NULL;
unsigned char input_char;
int write_result;
@ -269,10 +256,10 @@ int do_swconfigbyte(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
/* display value if no argument */
if (argc < 2) {
printf ("Software configuration byte is currently: 0x%02x\n",
*((unsigned char *) (SW_BYTE_SECTOR_ADDR + SW_BYTE_SECTOR_OFFSET)));
*((unsigned char *) (SW_BYTE_SECTOR_ADDR +
SW_BYTE_SECTOR_OFFSET)));
return 0;
}
else if(argc > 3){
} else if (argc > 3) {
printf ("Too many arguments\n");
return -1;
}
@ -281,8 +268,7 @@ int do_swconfigbyte(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
if (argc == 3) {
input_uint = simple_strtoul (argv[1], NULL, 16);
sector_buffer = (unsigned char *) input_uint;
}
else{
} else {
sector_buffer = (unsigned char *) DEFAULT_TEMP_ADDR;
}
@ -293,25 +279,30 @@ int do_swconfigbyte(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
input_char = input_char & SW_BYTE_MASK;
}
memcpy(sector_buffer, (void *)SW_BYTE_SECTOR_ADDR, SW_BYTE_SECTOR_SIZE);
memcpy (sector_buffer, (void *) SW_BYTE_SECTOR_ADDR,
SW_BYTE_SECTOR_SIZE);
sector_buffer[SW_BYTE_SECTOR_OFFSET] = input_char;
printf ("Erasing Flash...");
if (flash_sect_erase (SW_BYTE_SECTOR_ADDR, (SW_BYTE_SECTOR_ADDR + SW_BYTE_SECTOR_OFFSET))){
if (flash_sect_erase
(SW_BYTE_SECTOR_ADDR,
(SW_BYTE_SECTOR_ADDR + SW_BYTE_SECTOR_OFFSET))) {
return -1;
}
printf ("Writing to Flash... ");
write_result = flash_write(sector_buffer, SW_BYTE_SECTOR_ADDR, SW_BYTE_SECTOR_SIZE);
write_result =
flash_write (sector_buffer, SW_BYTE_SECTOR_ADDR,
SW_BYTE_SECTOR_SIZE);
if (write_result != 0) {
flash_perror (write_result);
return -1;
}
else{
} else {
printf ("done\n");
printf ("Software configuration byte is now: 0x%02x\n",
*((unsigned char *) (SW_BYTE_SECTOR_ADDR + SW_BYTE_SECTOR_OFFSET)));
*((unsigned char *) (SW_BYTE_SECTOR_ADDR +
SW_BYTE_SECTOR_OFFSET)));
}
return 0;
@ -319,7 +310,8 @@ int do_swconfigbyte(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
#define ONE_SECOND 1000000
int do_pause(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
int do_pause (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
int pause_time;
unsigned int delay_time;
int break_loop = 0;
@ -332,8 +324,7 @@ int do_pause(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
else if (argc > 2) {
printf ("Too many arguments\n");
return -1;
}
else{
} else {
pause_time = simple_strtoul (argv[1], NULL, 0);
}
@ -353,7 +344,8 @@ int do_pause(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
return 0;
}
int do_swreconfig(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
int do_swreconfig (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
printf ("Triggering software reconfigure (software config byte is 0x%02x)...\n",
*((unsigned char *) (SW_BYTE_SECTOR_ADDR + SW_BYTE_SECTOR_OFFSET)));
udelay (1000);
@ -372,7 +364,8 @@ int do_swreconfig(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
#define TEMP_ETHERM_BIT 0x02
#define TEMP_LTHERM_BIT 0x01
int do_temp_sensor(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
int do_temp_sensor (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
char cmd;
int ret_val = 0;
unsigned char temp_byte;
@ -389,8 +382,7 @@ int do_temp_sensor(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
if (argc > 1) {
cmd = argv[1][0];
}
else{
} else {
cmd = 's'; /* default to status */
}
@ -399,211 +391,259 @@ int do_temp_sensor(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
user_data[ii] = simple_strtoul (argv[2 + ii], NULL, 0);
}
switch (cmd) {
case 's':{
if(I2CAccess(0x2, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &temp_byte, I2C_READ) != 0){
case 's':
if (I2CAccess
(0x2, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
&temp_byte, I2C_READ) != 0) {
goto fail;
}
printf ("Status : 0x%02x ", temp_byte);
if(temp_byte & TEMP_BUSY_BIT){
if (temp_byte & TEMP_BUSY_BIT)
printf ("BUSY ");
}
if(temp_byte & TEMP_LHIGH_BIT){
if (temp_byte & TEMP_LHIGH_BIT)
printf ("LHIGH ");
}
if(temp_byte & TEMP_LLOW_BIT){
if (temp_byte & TEMP_LLOW_BIT)
printf ("LLOW ");
}
if(temp_byte & TEMP_EHIGH_BIT){
if (temp_byte & TEMP_EHIGH_BIT)
printf ("EHIGH ");
}
if(temp_byte & TEMP_ELOW_BIT){
if (temp_byte & TEMP_ELOW_BIT)
printf ("ELOW ");
}
if(temp_byte & TEMP_OPEN_BIT){
if (temp_byte & TEMP_OPEN_BIT)
printf ("OPEN ");
}
if(temp_byte & TEMP_ETHERM_BIT){
if (temp_byte & TEMP_ETHERM_BIT)
printf ("ETHERM ");
}
if(temp_byte & TEMP_LTHERM_BIT){
if (temp_byte & TEMP_LTHERM_BIT)
printf ("LTHERM");
}
printf ("\n");
if(I2CAccess(0x3, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &temp_byte, I2C_READ) != 0){
if (I2CAccess
(0x3, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
&temp_byte, I2C_READ) != 0) {
goto fail;
}
printf ("Config : 0x%02x ", temp_byte);
if(I2CAccess(0x4, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &temp_byte, I2C_READ) != 0){
if (I2CAccess
(0x4, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
&temp_byte, I2C_READ) != 0) {
printf ("\n");
goto fail;
}
printf ("Conversion: 0x%02x\n", temp_byte);
if(I2CAccess(0x22, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &temp_byte, I2C_READ) != 0){
if (I2CAccess
(0x22, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
&temp_byte, I2C_READ) != 0) {
goto fail;
}
printf ("Cons Alert: 0x%02x ", temp_byte);
if(I2CAccess(0x21, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &temp_byte, I2C_READ) != 0){
if (I2CAccess
(0x21, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
&temp_byte, I2C_READ) != 0) {
printf ("\n");
goto fail;
}
printf ("Therm Hyst: %d\n", temp_byte);
if(I2CAccess(0x0, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &temp_byte, I2C_READ) != 0){
if (I2CAccess
(0x0, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
&temp_byte, I2C_READ) != 0) {
goto fail;
}
temp = temp_byte;
if(I2CAccess(0x6, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &temp_byte, I2C_READ) != 0){
if (I2CAccess
(0x6, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
&temp_byte, I2C_READ) != 0) {
goto fail;
}
low = temp_byte;
if(I2CAccess(0x5, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &temp_byte, I2C_READ) != 0){
if (I2CAccess
(0x5, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
&temp_byte, I2C_READ) != 0) {
goto fail;
}
high = temp_byte;
if(I2CAccess(0x20, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &temp_byte, I2C_READ) != 0){
if (I2CAccess
(0x20, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
&temp_byte, I2C_READ) != 0) {
goto fail;
}
therm = temp_byte;
printf ("Local Temp: %2d Low: %2d High: %2d THERM: %2d\n", temp, low, high, therm);
if(I2CAccess(0x1, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &temp_byte, I2C_READ) != 0){
if (I2CAccess
(0x1, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
&temp_byte, I2C_READ) != 0) {
goto fail;
}
temp = temp_byte;
if(I2CAccess(0x10, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &temp_byte, I2C_READ) != 0){
if (I2CAccess
(0x10, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
&temp_byte, I2C_READ) != 0) {
goto fail;
}
temp_low = temp_byte;
if(I2CAccess(0x8, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &temp_byte, I2C_READ) != 0){
if (I2CAccess
(0x8, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
&temp_byte, I2C_READ) != 0) {
goto fail;
}
low = temp_byte;
if(I2CAccess(0x14, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &temp_byte, I2C_READ) != 0){
if (I2CAccess
(0x14, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
&temp_byte, I2C_READ) != 0) {
goto fail;
}
low_low = temp_byte;
if(I2CAccess(0x7, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &temp_byte, I2C_READ) != 0){
if (I2CAccess
(0x7, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
&temp_byte, I2C_READ) != 0) {
goto fail;
}
high = temp_byte;
if(I2CAccess(0x13, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &temp_byte, I2C_READ) != 0){
if (I2CAccess
(0x13, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
&temp_byte, I2C_READ) != 0) {
goto fail;
}
high_low = temp_byte;
if(I2CAccess(0x19, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &temp_byte, I2C_READ) != 0){
if (I2CAccess
(0x19, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
&temp_byte, I2C_READ) != 0) {
goto fail;
}
therm = temp_byte;
if(I2CAccess(0x11, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &temp_byte, I2C_READ) != 0){
if (I2CAccess
(0x11, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
&temp_byte, I2C_READ) != 0) {
goto fail;
}
printf ("Ext Temp : %2d.%03d Low: %2d.%03d High: %2d.%03d THERM: %2d Offset: %2d\n", temp, GET_DECIMAL (temp_low), low, GET_DECIMAL (low_low), high, GET_DECIMAL (high_low), therm, temp_byte);
break;
}
case 'l':{ /* alter local limits : low, high, therm */
case 'l': /* alter local limits : low, high, therm */
if (argc < 3) {
goto usage;
}
/* low */
if(I2CAccess(0xC, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &user_data[0], I2C_WRITE) != 0){
if (I2CAccess
(0xC, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
&user_data[0], I2C_WRITE) != 0) {
goto fail;
}
if (user_data_count > 1) {
/* high */
if(I2CAccess(0xB, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &user_data[1], I2C_WRITE) != 0){
if (I2CAccess
(0xB, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
&user_data[1], I2C_WRITE) != 0) {
goto fail;
}
}
if (user_data_count > 2) {
/* therm */
if(I2CAccess(0x20, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &user_data[2], I2C_WRITE) != 0){
if (I2CAccess
(0x20, I2C_SENSOR_DEV,
I2C_SENSOR_CHIP_SEL, &user_data[2],
I2C_WRITE) != 0) {
goto fail;
}
}
break;
}
case 'e':{ /* alter external limits: low, high, therm, offset */
case 'e': /* alter external limits: low, high, therm, offset */
if (argc < 3) {
goto usage;
}
/* low */
if(I2CAccess(0xE, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &user_data[0], I2C_WRITE) != 0){
if (I2CAccess
(0xE, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
&user_data[0], I2C_WRITE) != 0) {
goto fail;
}
if (user_data_count > 1) {
/* high */
if(I2CAccess(0xD, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &user_data[1], I2C_WRITE) != 0){
if (I2CAccess
(0xD, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
&user_data[1], I2C_WRITE) != 0) {
goto fail;
}
}
if (user_data_count > 2) {
/* therm */
if(I2CAccess(0x19, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &user_data[2], I2C_WRITE) != 0){
if (I2CAccess
(0x19, I2C_SENSOR_DEV,
I2C_SENSOR_CHIP_SEL, &user_data[2],
I2C_WRITE) != 0) {
goto fail;
}
}
if (user_data_count > 3) {
/* offset */
if(I2CAccess(0x11, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &user_data[3], I2C_WRITE) != 0){
if (I2CAccess
(0x11, I2C_SENSOR_DEV,
I2C_SENSOR_CHIP_SEL, &user_data[3],
I2C_WRITE) != 0) {
goto fail;
}
}
break;
}
case 'c':{ /* alter config settings: config, conv, cons alert, therm hyst */
case 'c': /* alter config settings: config, conv, cons alert, therm hyst */
if (argc < 3) {
goto usage;
}
/* config */
if(I2CAccess(0x9, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &user_data[0], I2C_WRITE) != 0){
if (I2CAccess
(0x9, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
&user_data[0], I2C_WRITE) != 0) {
goto fail;
}
if (user_data_count > 1) {
/* conversion */
if(I2CAccess(0xA, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &user_data[1], I2C_WRITE) != 0){
if (I2CAccess
(0xA, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
&user_data[1], I2C_WRITE) != 0) {
goto fail;
}
}
if (user_data_count > 2) {
/* cons alert */
if(I2CAccess(0x22, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &user_data[2], I2C_WRITE) != 0){
if (I2CAccess
(0x22, I2C_SENSOR_DEV,
I2C_SENSOR_CHIP_SEL, &user_data[2],
I2C_WRITE) != 0) {
goto fail;
}
}
if (user_data_count > 3) {
/* therm hyst */
if(I2CAccess(0x21, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, &user_data[3], I2C_WRITE) != 0){
if (I2CAccess
(0x21, I2C_SENSOR_DEV,
I2C_SENSOR_CHIP_SEL, &user_data[3],
I2C_WRITE) != 0) {
goto fail;
}
}
break;
}
default:{
default:
goto usage;
}
}
goto done;
fail:
@ -617,8 +657,7 @@ int do_temp_sensor(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
return ret_val;
}
U_BOOT_CMD(
temp, 6, 0, do_temp_sensor,
U_BOOT_CMD (temp, 6, 0, do_temp_sensor,
"temp - interact with the temperature sensor\n",
"temp [s]\n"
" - Show status.\n"
@ -630,43 +669,31 @@ U_BOOT_CMD(
" - Set config options.\n"
"\n"
"All values can be decimal or hex (hex preceded with 0x).\n"
"Only whole numbers are supported for external limits.\n"
);
"Only whole numbers are supported for external limits.\n");
#if 0
U_BOOT_CMD(
loadace, 2, 0, do_loadace,
U_BOOT_CMD (loadace, 2, 0, do_loadace,
"loadace - load fpga configuration from System ACE compact flash\n",
"N\n"
" - Load configuration N (0-7) from System ACE compact flash\n"
"loadace\n"
" - loads default configuration\n"
);
"loadace\n" " - loads default configuration\n");
#endif
U_BOOT_CMD(
swconfig, 2, 0, do_swconfigbyte,
U_BOOT_CMD (swconfig, 2, 0, do_swconfigbyte,
"swconfig- display or modify the software configuration byte\n",
"N [ADDRESS]\n"
" - set software configuration byte to N, optionally use ADDRESS as\n"
" location of buffer for flash copy\n"
"swconfig\n"
" - display software configuration byte\n"
);
"swconfig\n" " - display software configuration byte\n");
U_BOOT_CMD(
pause, 2, 0, do_pause,
U_BOOT_CMD (pause, 2, 0, do_pause,
"pause - sleep processor until any key is pressed with poll time of N seconds\n",
"N\n"
" - sleep processor until any key is pressed with poll time of N seconds\n"
"pause\n"
" - sleep processor until any key is pressed with poll time of 1 second\n"
);
" - sleep processor until any key is pressed with poll time of 1 second\n");
U_BOOT_CMD(
swrecon, 1, 0, do_swreconfig,
U_BOOT_CMD (swrecon, 1, 0, do_swreconfig,
"swrecon - trigger a board reconfigure to the software selected configuration\n",
"\n"
" - trigger a board reconfigure to the software selected configuration\n"
);
" - trigger a board reconfigure to the software selected configuration\n");

24
board/amirix/ap1000/ap1000.h
View file

@ -78,20 +78,20 @@
*/
#define AP1000_SYSACE_REGBASE 0x28000000
#define SYSACE_STATREG0 0x04 // 7:0
#define SYSACE_STATREG1 0x05 // 15:8
#define SYSACE_STATREG2 0x06 // 23:16
#define SYSACE_STATREG3 0x07 // 31:24
#define SYSACE_STATREG0 0x04 /* 7:0 */
#define SYSACE_STATREG1 0x05 /* 15:8 */
#define SYSACE_STATREG2 0x06 /* 23:16 */
#define SYSACE_STATREG3 0x07 /* 31:24 */
#define SYSACE_ERRREG0 0x08 // 7:0
#define SYSACE_ERRREG1 0x09 // 15:8
#define SYSACE_ERRREG2 0x0a // 23:16
#define SYSACE_ERRREG3 0x0b // 31:24
#define SYSACE_ERRREG0 0x08 /* 7:0 */
#define SYSACE_ERRREG1 0x09 /* 15:8 */
#define SYSACE_ERRREG2 0x0a /* 23:16 */
#define SYSACE_ERRREG3 0x0b /* 31:24 */
#define SYSACE_CTRLREG0 0x18 // 7:0
#define SYSACE_CTRLREG1 0x19 // 15:8
#define SYSACE_CTRLREG2 0x1A // 23:16
#define SYSACE_CTRLREG3 0x1B // 31:24
#define SYSACE_CTRLREG0 0x18 /* 7:0 */
#define SYSACE_CTRLREG1 0x19 /* 15:8 */
#define SYSACE_CTRLREG2 0x1A /* 23:16 */
#define SYSACE_CTRLREG3 0x1B /* 31:24 */
/*
* Software reconfig thing

212
board/amirix/ap1000/flash.c
View file

@ -94,12 +94,8 @@
#define FLASH_OFFSET_USER_PROTECTION 0x85
#define FLASH_OFFSET_INTEL_PROTECTION 0x81
#define FLASH_MAN_CFI 0x01000000
typedef union {
unsigned char c;
unsigned short w;
@ -116,24 +112,27 @@ typedef union {
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
*/
static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c);
static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf);
static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
static void flash_write_cmd (flash_info_t * info, int sect, uchar offset,
uchar cmd);
static int flash_isequal (flash_info_t * info, int sect, uchar offset,
uchar cmd);
static int flash_isset (flash_info_t * info, int sect, uchar offset,
uchar cmd);
static int flash_detect_cfi (flash_info_t * info);
static ulong flash_get_size (ulong base, int banknum);
static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
static int flash_write_cfiword (flash_info_t * info, ulong dest,
cfiword_t cword);
static int flash_full_status_check (flash_info_t * info, ulong sector,
ulong tout, char *prompt);
#ifdef CFG_FLASH_USE_BUFFER_WRITE
static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
int len);
#endif
/*-----------------------------------------------------------------------
* create an address based on the offset and the port width
@ -142,6 +141,7 @@ uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
{
return ((uchar *) (info->start[sect] + (offset * info->chipwidth)));
}
/*-----------------------------------------------------------------------
* read a character at a port width address
*/
@ -150,6 +150,7 @@ uchar flash_read_uchar(flash_info_t * info, uchar offset)
if (info->portwidth == FLASH_CFI_8BIT) {
volatile uchar *cp;
uchar c;
cp = flash_make_addr (info, 0, offset);
c = *cp;
#ifdef DEBUG_FLASH
@ -162,12 +163,12 @@ uchar flash_read_uchar(flash_info_t * info, uchar offset)
volatile ushort *sp;
ushort s;
uchar c;
sp = (ushort *) flash_make_addr (info, 0, offset);
s = *sp;
c = (uchar) s;
#ifdef DEBUG_FLASH
printf("flash_read_uchar offset=%04x ptr=%08x s=%04x c=%02x\n",
offset, (unsigned int)sp, s, c);
printf ("flash_read_uchar offset=%04x ptr=%08x s=%04x c=%02x\n", offset, (unsigned int) sp, s, c);
#endif
return (c);
@ -185,13 +186,13 @@ ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
volatile uchar *cp;
uchar c0, c1;
ushort s;
cp = flash_make_addr (info, 0, offset);
c1 = cp[2];
c0 = cp[0];
s = c1 << 8 | c0;
#ifdef DEBUG_FLASH
printf("flash_read_ushort offset=%04x ptr=%08x c1=%02x c0=%02x s=%04x\n",
offset, (unsigned int)cp, c1, c0, s);
printf ("flash_read_ushort offset=%04x ptr=%08x c1=%02x c0=%02x s=%04x\n", offset, (unsigned int) cp, c1, c0, s);
#endif
return (s);
@ -199,14 +200,14 @@ ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
volatile ushort *sp;
ushort s;
uchar c0, c1;
sp = (ushort *) flash_make_addr (info, 0, offset);
s = *sp;
c1 = (uchar) sp[1];
c0 = (uchar) sp[0];
s = c1 << 8 | c0;
#ifdef DEBUG_FLASH
printf("flash_read_ushort offset=%04x ptr=%08x c1=%02x c0=%02x s=%04x\n",
offset, (unsigned int)sp, c1, c0, s);
printf ("flash_read_ushort offset=%04x ptr=%08x c1=%02x c0=%02x s=%04x\n", offset, (unsigned int) sp, c1, c0, s);
#endif
return (s);
@ -225,6 +226,7 @@ ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
volatile uchar *cp;
uchar c0, c1, c2, c3;
ulong l;
cp = flash_make_addr (info, 0, offset);
c3 = cp[6];
c2 = cp[4];
@ -232,8 +234,7 @@ ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
c0 = cp[0];
l = c3 << 24 | c2 << 16 | c1 << 8 | c0;
#ifdef DEBUG_FLASH
printf("flash_read_long offset=%04x ptr=%08x c3=%02x c2=%02x c1=%02x c0=%02x l=%08x\n",
offset, (unsigned int)cp, c3, c2, c1, c0, l);
printf ("flash_read_long offset=%04x ptr=%08x c3=%02x c2=%02x c1=%02x c0=%02x l=%08x\n", offset, (unsigned int) cp, c3, c2, c1, c0, l);
#endif
return (l);
@ -241,6 +242,7 @@ ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
volatile ushort *sp;
uchar c0, c1, c2, c3;
ulong l;
sp = (ushort *) flash_make_addr (info, 0, offset);
c3 = (uchar) sp[3];
c2 = (uchar) sp[2];
@ -248,8 +250,7 @@ ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
c0 = (uchar) sp[0];
l = c3 << 24 | c2 << 16 | c1 << 8 | c0;
#ifdef DEBUG_FLASH
printf("flash_read_long offset=%04x ptr=%08x c3=%02x c2=%02x c1=%02x c0=%02x l=%08x\n",
offset, (unsigned int)sp, c3, c2, c1, c0, l);
printf ("flash_read_long offset=%04x ptr=%08x c3=%02x c2=%02x c1=%02x c0=%02x l=%08x\n", offset, (unsigned int) sp, c3, c2, c1, c0, l);
#endif
return (l);
@ -271,8 +272,7 @@ unsigned long flash_init (void)
flash_info[0].chipwidth = FLASH_CFI_16BIT;
size += flash_info[0].size = flash_get_size (CFG_PROGFLASH_BASE, 0);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 1,
flash_info[0].size, flash_info[0].size<<20);
printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 1, flash_info[0].size, flash_info[0].size << 20);
};
flash_info[1].flash_id = FLASH_UNKNOWN;
@ -280,8 +280,7 @@ unsigned long flash_init (void)
flash_info[1].chipwidth = FLASH_CFI_16BIT;
size += flash_info[1].size = flash_get_size (CFG_CONFFLASH_BASE, 1);
if (flash_info[1].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 2,
flash_info[1].size, flash_info[1].size<<20);
printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 2, flash_info[1].size, flash_info[1].size << 20);
};
return (size);
@ -311,20 +310,22 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
printf ("- Warning: %d protected sectors will not be erased!\n", prot);
} else {
printf ("\n");
}
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
flash_write_cmd (info, sect, 0,
FLASH_CMD_CLEAR_STATUS);
flash_write_cmd (info, sect, 0,
FLASH_CMD_BLOCK_ERASE);
flash_write_cmd (info, sect, 0,
FLASH_CMD_ERASE_CONFIRM);
if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
if (flash_full_status_check
(info, sect, info->erase_blk_tout, "erase")) {
rcode = 1;
} else
printf (".");
@ -349,17 +350,14 @@ void flash_print_info (flash_info_t *info)
(info->chipwidth << 3), (info->portwidth << 3));
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n");
printf (" %08lX%5s",
info->start[i],
info->protect[i] ? " (RO)" : " "
);
info->start[i], info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
return;
@ -400,7 +398,6 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
return rc;
wp = cp;
}
#ifdef CFG_FLASH_USE_BUFFER_WRITE
while (cnt >= info->portwidth) {
i = info->buffer_size > cnt ? cnt : info->buffer_size;
@ -455,13 +452,15 @@ int flash_real_protect(flash_info_t *info, long sector, int prot)
else
flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
if ((retcode =
flash_full_status_check (info, sector, info->erase_blk_tout,
prot ? "protect" : "unprotect")) == 0) {
info->protect[sector] = prot;
/* Intel's unprotect unprotects all locking */
if (prot == 0) {
int i;
for (i = 0; i < info->sector_count; i++) {
if (info->protect[i])
flash_real_protect (info, i, 1);
@ -471,11 +470,13 @@ int flash_real_protect(flash_info_t *info, long sector, int prot)
return retcode;
}
/*-----------------------------------------------------------------------
* wait for XSR.7 to be set. Time out with an error if it does not.
* This routine does not set the flash to read-array mode.
*/
static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
static int flash_status_check (flash_info_t * info, ulong sector, ulong tout,
char *prompt)
{
ulong start;
@ -483,25 +484,33 @@ static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, cha
start = get_timer (0);
while (!flash_isset (info, sector, 0, FLASH_STATUS_DONE)) {
if (get_timer (start) > info->erase_blk_tout) {
printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
printf ("Flash %s timeout at address %lx\n", prompt,
info->start[sector]);
flash_write_cmd (info, sector, 0, FLASH_CMD_RESET);
return ERR_TIMOUT;
}
}
return ERR_OK;
}
/*-----------------------------------------------------------------------
* Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
* This routine sets the flash to read-array mode.
*/
static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
static int flash_full_status_check (flash_info_t * info, ulong sector,
ulong tout, char *prompt)
{
int retcode;
retcode = flash_status_check (info, sector, tout, prompt);
if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
if ((retcode == ERR_OK)
&& !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
retcode = ERR_INVAL;
printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
printf ("Flash %s error at address %lx\n", prompt,
info->start[sector]);
if (flash_isset
(info, sector, 0,
FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
printf ("Command Sequence Error.\n");
} else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) {
printf ("Block Erase Error.\n");
@ -519,6 +528,7 @@ static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout
flash_write_cmd (info, sector, 0, FLASH_CMD_RESET);
return retcode;
}
/*-----------------------------------------------------------------------
*/
static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
@ -535,19 +545,21 @@ static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
}
}
/*-----------------------------------------------------------------------
* make a proper sized command based on the port and chip widths
*/
static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
{
//int i;
/*int i; */
uchar *cp = (uchar *) cmdbuf;
// for(i=0; i< info->portwidth; i++)
// *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
if (info->portwidth == FLASH_CFI_8BIT && info->chipwidth == FLASH_CFI_16BIT) {
/* for(i=0; i< info->portwidth; i++) */
/* *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; */
if (info->portwidth == FLASH_CFI_8BIT
&& info->chipwidth == FLASH_CFI_16BIT) {
cp[0] = cmd;
} else if (info->portwidth == FLASH_CFI_16BIT && info->chipwidth == FLASH_CFI_16BIT) {
} else if (info->portwidth == FLASH_CFI_16BIT
&& info->chipwidth == FLASH_CFI_16BIT) {
cp[0] = '\0';
cp[1] = cmd;
};
@ -556,11 +568,13 @@ static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
/*
* Write a proper sized command to the correct address
*/
static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
static void flash_write_cmd (flash_info_t * info, int sect, uchar offset,
uchar cmd)
{
volatile cfiptr_t addr;
cfiword_t cword;
addr.cp = flash_make_addr (info, sect, offset);
flash_make_cmd (info, cmd, &cword);
switch (info->portwidth) {
@ -578,11 +592,13 @@ static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar c
/*-----------------------------------------------------------------------
*/
static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
static int flash_isequal (flash_info_t * info, int sect, uchar offset,
uchar cmd)
{
cfiptr_t cptr;
cfiword_t cword;
int retval;
cptr.cp = flash_make_addr (info, sect, offset);
flash_make_cmd (info, cmd, &cword);
switch (info->portwidth) {
@ -601,13 +617,16 @@ static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
}
return retval;
}
/*-----------------------------------------------------------------------
*/
static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
static int flash_isset (flash_info_t * info, int sect, uchar offset,
uchar cmd)
{
cfiptr_t cptr;
cfiword_t cword;
int retval;
cptr.cp = flash_make_addr (info, sect, offset);
flash_make_cmd (info, cmd, &cword);
switch (info->portwidth) {
@ -636,16 +655,20 @@ static int flash_detect_cfi(flash_info_t * info)
{
#if 0
for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
info->portwidth <<= 1) {
for (info->portwidth = FLASH_CFI_8BIT;
info->portwidth <= FLASH_CFI_32BIT; info->portwidth <<= 1) {
for (info->chipwidth = FLASH_CFI_BY8;
info->chipwidth <= info->portwidth;
info->chipwidth <<= 1) {
flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
flash_write_cmd (info, 0, FLASH_OFFSET_CFI,
FLASH_CMD_CFI);
if (flash_isequal
(info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
&& flash_isequal (info, 0,
FLASH_OFFSET_CFI_RESP + 1, 'R')
&& flash_isequal (info, 0,
FLASH_OFFSET_CFI_RESP + 2, 'Y'))
return 1;
}
}
@ -660,6 +683,7 @@ static int flash_detect_cfi(flash_info_t * info)
return 0;
};
}
/*
* The following code cannot be run from FLASH!
*
@ -682,8 +706,10 @@ static ulong flash_get_size (ulong base, int banknum)
#ifdef DEBUG_FLASH
printf ("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
#endif
size_ratio = 1; // info->portwidth / info->chipwidth;
num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
size_ratio = 1; /* info->portwidth / info->chipwidth; */
num_erase_regions =
flash_read_uchar (info,
FLASH_OFFSET_NUM_ERASE_REGIONS);
#ifdef DEBUG_FLASH
printf ("found %d erase regions\n", num_erase_regions);
#endif
@ -691,32 +717,51 @@ static ulong flash_get_size (ulong base, int banknum)
sector = base;
for (i = 0; i < num_erase_regions; i++) {
if (i > NUM_ERASE_REGIONS) {
printf("%d erase regions found, only %d used\n",
num_erase_regions, NUM_ERASE_REGIONS);
printf ("%d erase regions found, only %d used\n", num_erase_regions, NUM_ERASE_REGIONS);
break;
}
tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
tmp = flash_read_long (info, 0,
FLASH_OFFSET_ERASE_REGIONS);
erase_region_count = (tmp & 0xffff) + 1;
tmp >>= 16;
erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
erase_region_size =
(tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
for (j = 0; j < erase_region_count; j++) {
info->start[sect_cnt] = sector;
sector += (erase_region_size * size_ratio);
info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
info->protect[sect_cnt] =
flash_isset (info, sect_cnt,
FLASH_OFFSET_PROTECT,
FLASH_STATUS_PROTECT);
sect_cnt++;
}
}
info->sector_count = sect_cnt;
/* multiply the size by the number of chips */
info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
info->size =
(1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) *
size_ratio;
info->buffer_size =
(1 <<
flash_read_ushort (info, 0,
FLASH_OFFSET_BUFFER_SIZE));
tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT);
info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
info->erase_blk_tout =
(tmp *
(1 <<
flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT)));
tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT);
info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
info->buffer_write_tout =
(tmp *
(1 <<
flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT)));
tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT);
info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
info->write_tout =
(tmp *
(1 <<
flash_read_uchar (info,
FLASH_OFFSET_WMAX_TOUT))) / 1000;
info->flash_id = FLASH_MAN_CFI;
}
@ -724,10 +769,10 @@ static ulong flash_get_size (ulong base, int banknum)
return (info->size);
}
/*-----------------------------------------------------------------------
*/
static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
static int flash_write_cfiword (flash_info_t * info, ulong dest,
cfiword_t cword)
{
cfiptr_t ctladdr;
@ -737,7 +782,6 @@ static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
ctladdr.cp = flash_make_addr (info, 0, 0);
cptr.cp = (uchar *) dest;
/* Check if Flash is (sufficiently) erased */
switch (info->portwidth) {
case FLASH_CFI_8BIT:
@ -789,6 +833,7 @@ static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
static int find_sector (flash_info_t * info, ulong addr)
{
int sector;
for (sector = info->sector_count - 1; sector >= 0; sector--) {
if (addr >= info->start[sector])
break;
@ -796,7 +841,8 @@ static int find_sector(flash_info_t *info, ulong addr)
return sector;
}
static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
int len)
{
int sector;
@ -810,7 +856,8 @@ static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, in
sector = find_sector (info, dest);
flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
if ((retcode =
flash_status_check (info, sector, info->buffer_write_tout,
"write to buffer")) == ERR_OK) {
switch (info->portwidth) {
case FLASH_CFI_8BIT:
@ -843,8 +890,11 @@ static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, in
break;
}
}
flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
flash_write_cmd (info, sector, 0,
FLASH_CMD_WRITE_BUFFER_CONFIRM);
retcode =
flash_full_status_check (info, sector,
info->buffer_write_tout,
"buffer write");
}
flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);

156
board/amirix/ap1000/pci.c
View file

@ -42,16 +42,19 @@
/* static int G_verbosity_level = 1; */
#define G_verbosity_level 1
void write1(unsigned long addr, unsigned char val) {
void write1 (unsigned long addr, unsigned char val)
{
volatile unsigned char *p = (volatile unsigned char *) addr;
if (G_verbosity_level > 1)
printf("write1: addr=%08x val=%02x\n", (unsigned int)addr, val);
printf ("write1: addr=%08x val=%02x\n", (unsigned int) addr,
val);
*p = val;
asm ("eieio");
}
unsigned char read1(unsigned long addr) {
unsigned char read1 (unsigned long addr)
{
unsigned char val;
volatile unsigned char *p = (volatile unsigned char *) addr;
@ -64,18 +67,21 @@ unsigned char read1(unsigned long addr) {
return val;
}
void write2(unsigned long addr, unsigned short val) {
void write2 (unsigned long addr, unsigned short val)
{
volatile unsigned short *p = (volatile unsigned short *) addr;
if (G_verbosity_level > 1)
printf("write2: addr=%08x val=%04x -> *p=%04x\n", (unsigned int)addr, val,
printf ("write2: addr=%08x val=%04x -> *p=%04x\n",
(unsigned int) addr, val,
((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8));
*p = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
asm ("eieio");
}
unsigned short read2(unsigned long addr) {
unsigned short read2 (unsigned long addr)
{
unsigned short val;
volatile unsigned short *p = (volatile unsigned short *) addr;
@ -90,20 +96,25 @@ unsigned short read2(unsigned long addr) {
return val;
}
void write4(unsigned long addr, unsigned long val) {
void write4 (unsigned long addr, unsigned long val)
{
volatile unsigned long *p = (volatile unsigned long *) addr;
if (G_verbosity_level > 1)
printf("write4: addr=%08x val=%08x -> *p=%08x\n", (unsigned int)addr, (unsigned int)val,
(unsigned int)(((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8)));
printf ("write4: addr=%08x val=%08x -> *p=%08x\n",
(unsigned int) addr, (unsigned int) val,
(unsigned int) (((val & 0xFF000000) >> 24) |
((val & 0x000000FF) << 24) |
((val & 0x00FF0000) >> 8) |
((val & 0x0000FF00) << 8)));
*p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
asm ("eieio");
}
unsigned long read4(unsigned long addr) {
unsigned long read4 (unsigned long addr)
{
unsigned long val;
volatile unsigned long *p = (volatile unsigned long *) addr;
@ -117,16 +128,21 @@ unsigned long read4(unsigned long addr) {
if (G_verbosity_level > 1)
printf ("*p=%04x -> val=%04x\n",
(unsigned int)(((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8)), (unsigned int)val);
(unsigned int) (((val & 0xFF000000) >> 24) |
((val & 0x000000FF) << 24) |
((val & 0x00FF0000) >> 8) |
((val & 0x0000FF00) << 8)),
(unsigned int) val);
return val;
}
void write4be(unsigned long addr, unsigned long val) {
void write4be (unsigned long addr, unsigned long val)
{
volatile unsigned long *p = (volatile unsigned long *) addr;
if (G_verbosity_level > 1)
printf("write4: addr=%08x val=%08x\n", (unsigned int)addr, (unsigned int)val);
printf ("write4: addr=%08x val=%08x\n", (unsigned int) addr,
(unsigned int) val);
*p = val;
asm ("eieio");
}
@ -140,18 +156,11 @@ void write4be(unsigned long addr, unsigned long val) {
* @param val Address of location for received byte.
* @return Always Zero.
*/
static int psII_read_config_byte(
struct pci_controller *hose,
pci_dev_t dev,
int reg,
u8 *val)
static int psII_read_config_byte (struct pci_controller *hose,
pci_dev_t dev, int reg, u8 * val)
{
write4be(PSII_CONFIG_ADDR,
PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS(dev) << 16) |
(PCI_DEV(dev) << 11) |
(PCI_FUNC(dev) << 8) |
((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
*val = read1 (PSII_CONFIG_DATA + (reg & 0x03));
return (0);
@ -166,18 +175,11 @@ static int psII_read_config_byte(
* @param val Output byte.
* @return Always Zero.
*/
static int psII_write_config_byte(
struct pci_controller *hose,
pci_dev_t dev,
int reg,
u8 val)
static int psII_write_config_byte (struct pci_controller *hose,
pci_dev_t dev, int reg, u8 val)
{
write4be(PSII_CONFIG_ADDR,
PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS(dev) << 16) |
(PCI_DEV(dev) << 11) |
(PCI_FUNC(dev) << 8) |
((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
write1 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned char) val);
@ -193,18 +195,11 @@ static int psII_write_config_byte(
* @param val Address of location for received word.
* @return Always Zero.
*/
static int psII_read_config_word(
struct pci_controller *hose,
pci_dev_t dev,
int reg,
u16 *val)
static int psII_read_config_word (struct pci_controller *hose,
pci_dev_t dev, int reg, u16 * val)
{
write4be(PSII_CONFIG_ADDR,
PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS(dev) << 16) |
(PCI_DEV(dev) << 11) |
(PCI_FUNC(dev) << 8) |
((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
*val = read2 (PSII_CONFIG_DATA + (reg & 0x03));
return (0);
@ -219,18 +214,11 @@ static int psII_read_config_word(
* @param val Output word.
* @return Always Zero.
*/
static int psII_write_config_word(
struct pci_controller *hose,
pci_dev_t dev,
int reg,
u16 val)
static int psII_write_config_word (struct pci_controller *hose,
pci_dev_t dev, int reg, u16 val)
{
write4be(PSII_CONFIG_ADDR,
PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS(dev) << 16) |
(PCI_DEV(dev) << 11) |
(PCI_FUNC(dev) << 8) |
((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
write2 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned short) val);
@ -246,18 +234,11 @@ static int psII_write_config_word(
* @param val Address of location for received byte.
* @return Always Zero.
*/
static int psII_read_config_dword(
struct pci_controller *hose,
pci_dev_t dev,
int reg,
u32 *val)
static int psII_read_config_dword (struct pci_controller *hose,
pci_dev_t dev, int reg, u32 * val)
{
write4be(PSII_CONFIG_ADDR,
PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS(dev) << 16) |
(PCI_DEV(dev) << 11) |
(PCI_FUNC(dev) << 8) |
((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
*val = read4 (PSII_CONFIG_DATA);
return (0);
@ -272,37 +253,29 @@ static int psII_read_config_dword(
* @param val Output Dword.
* @return Always Zero.
*/
static int psII_write_config_dword(
struct pci_controller *hose,
pci_dev_t dev,
int reg,
u32 val)
static int psII_write_config_dword (struct pci_controller *hose,
pci_dev_t dev, int reg, u32 val)
{
write4be(PSII_CONFIG_ADDR,
PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS(dev) << 16) |
(PCI_DEV(dev) << 11) |
(PCI_FUNC(dev) << 8) |
((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
write4 (PSII_CONFIG_DATA, (unsigned long) val);
return (0);
}
static struct pci_config_table ap1000_config_table[] = {
#ifdef CONFIG_AP1000
{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_BUS(CFG_ETH_DEV_FN), PCI_DEV(CFG_ETH_DEV_FN), PCI_FUNC(CFG_ETH_DEV_FN),
PCI_BUS (CFG_ETH_DEV_FN), PCI_DEV (CFG_ETH_DEV_FN),
PCI_FUNC (CFG_ETH_DEV_FN),
pci_cfgfunc_config_device,
{CFG_ETH_IOBASE, CFG_ETH_MEMBASE, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
{CFG_ETH_IOBASE, CFG_ETH_MEMBASE,
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
#endif
{}
};
static struct pci_controller psII_hose = {
config_table:ap1000_config_table,
};
@ -317,16 +290,16 @@ void pci_init_board(void)
hose->first_busno = 0;
hose->last_busno = 0xff;
/* System memory space */
pci_set_region (hose->regions + 0,
AP1000_SYS_MEM_START, AP1000_SYS_MEM_START, AP1000_SYS_MEM_SIZE,
AP1000_SYS_MEM_START, AP1000_SYS_MEM_START,
AP1000_SYS_MEM_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* PCI Memory space */
pci_set_region (hose->regions + 1,
PSII_PCI_MEM_BASE, PSII_PCI_MEM_BASE, PSII_PCI_MEM_SIZE,
PCI_REGION_MEM);
PSII_PCI_MEM_BASE, PSII_PCI_MEM_BASE,
PSII_PCI_MEM_SIZE, PCI_REGION_MEM);
/* No IO Memory space - for now */
@ -335,8 +308,7 @@ void pci_init_board(void)
psII_read_config_word,
psII_read_config_dword,
psII_write_config_byte,
psII_write_config_word,
psII_write_config_dword);
psII_write_config_word, psII_write_config_dword);
hose->region_count = 2;

260
board/amirix/ap1000/powerspan.c
View file

@ -38,8 +38,10 @@
* @param addr [IN] the address to write to
* @param val [IN] the value to write
*/
void write1(unsigned long addr, unsigned char val) {
void write1 (unsigned long addr, unsigned char val)
{
volatile unsigned char *p = (volatile unsigned char *) addr;
#ifdef VERBOSITY
if (gVerbosityLevel > 1) {
printf ("write1: addr=%08x val=%02x\n", addr, val);
@ -53,7 +55,8 @@ void write1(unsigned long addr, unsigned char val) {
* @param addr [IN] the address to read from
* @return the value at addr
*/
unsigned char read1(unsigned long addr) {
unsigned char read1 (unsigned long addr)
{
unsigned char val;
volatile unsigned char *p = (volatile unsigned char *) addr;
@ -71,7 +74,8 @@ unsigned char read1(unsigned long addr) {
* @param addr [IN] the address to write to
* @param val [IN] the value to write
*/
void write2(unsigned long addr, unsigned short val) {
void write2 (unsigned long addr, unsigned short val)
{
volatile unsigned short *p = (volatile unsigned short *) addr;
#ifdef VERBOSITY
@ -88,7 +92,8 @@ void write2(unsigned long addr, unsigned short val) {
* @param addr [IN] the address to read from
* @return the value at addr
*/
unsigned short read2(unsigned long addr) {
unsigned short read2 (unsigned long addr)
{
unsigned short val;
volatile unsigned short *p = (volatile unsigned short *) addr;
@ -97,7 +102,8 @@ unsigned short read2(unsigned long addr) {
PSII_SYNC ();
#ifdef VERBOSITY
if (gVerbosityLevel > 1) {
printf("read2: addr=%08x *p=%04x -> val=%04x\n", addr, *p, val);
printf ("read2: addr=%08x *p=%04x -> val=%04x\n", addr, *p,
val);
}
#endif
return val;
@ -107,13 +113,17 @@ unsigned short read2(unsigned long addr) {
* @param addr [IN] the address to write to
* @param val [IN] the value to write
*/
void write4(unsigned long addr, unsigned long val) {
void write4 (unsigned long addr, unsigned long val)
{
volatile unsigned long *p = (volatile unsigned long *) addr;
#ifdef VERBOSITY
if (gVerbosityLevel > 1) {
printf ("write4: addr=%08x val=%08x -> *p=%08x\n", addr, val,
((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8));
((val & 0xFF000000) >> 24) |
((val & 0x000000FF) << 24) |
((val & 0x00FF0000) >> 8) |
((val & 0x0000FF00) << 8));
}
#endif
*p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
@ -125,7 +135,8 @@ void write4(unsigned long addr, unsigned long val) {
* @param addr [IN] the address to read from
* @return the value at addr
*/
unsigned long read4(unsigned long addr) {
unsigned long read4 (unsigned long addr)
{
unsigned long val;
volatile unsigned long *p = (volatile unsigned long *) addr;
@ -135,13 +146,16 @@ unsigned long read4(unsigned long addr) {
PSII_SYNC ();
#ifdef VERBOSITY
if (gVerbosityLevel > 1) {
printf("read4: addr=%08x *p=%08x -> val=%08x\n", addr, *p, val);
printf ("read4: addr=%08x *p=%08x -> val=%08x\n", addr, *p,
val);
}
#endif
return val;
}
int PCIReadConfig(int bus, int dev, int fn, int reg, int width, unsigned long* val){
int PCIReadConfig (int bus, int dev, int fn, int reg, int width,
unsigned long *val)
{
unsigned int conAdrVal;
unsigned int conDataReg = REG_CONFIG_DATA;
unsigned int status;
@ -167,23 +181,19 @@ int PCIReadConfig(int bus, int dev, int fn, int reg, int width, unsigned long* v
/* Note: documentation does not match the pspan library code */
/* Note: *pData comes back as -1 if device is not present */
switch (width) {
case 4:{
case 4:
*(unsigned int *) val = read4 (conDataReg);
break;
}
case 2:{
case 2:
*(unsigned short *) val = read2 (conDataReg);
break;
}
case 1:{
case 1:
*(unsigned char *) val = read1 (conDataReg);
break;
}
default:{
default:
ret_val = ILLEGAL_REG_OFFSET;
break;
}
}
PSII_SYNC ();
/* clear any pending master aborts */
@ -197,7 +207,9 @@ int PCIReadConfig(int bus, int dev, int fn, int reg, int width, unsigned long* v
}
int PCIWriteConfig(int bus, int dev, int fn, int reg, int width, unsigned long val){
int PCIWriteConfig (int bus, int dev, int fn, int reg, int width,
unsigned long val)
{
unsigned int conAdrVal;
unsigned int conDataReg = REG_CONFIG_DATA;
unsigned int status;
@ -223,23 +235,19 @@ int PCIWriteConfig(int bus, int dev, int fn, int reg, int width, unsigned long v
/* Note: documentation does not match the pspan library code */
/* Note: *pData comes back as -1 if device is not present */
switch (width) {
case 4:{
case 4:
write4 (conDataReg, val);
break;
}
case 2:{
case 2:
write2 (conDataReg, val);
break;
}
case 1:{
case 1:
write1 (conDataReg, val);
break;
}
default:{
default:
ret_val = ILLEGAL_REG_OFFSET;
break;
}
}
PSII_SYNC ();
/* clear any pending master aborts */
@ -253,7 +261,9 @@ int PCIWriteConfig(int bus, int dev, int fn, int reg, int width, unsigned long v
}
int pci_read_config_byte(int bus, int dev, int fn, int reg, unsigned char* val){
int pci_read_config_byte (int bus, int dev, int fn, int reg,
unsigned char *val)
{
unsigned long read_val;
int ret_val;
@ -263,11 +273,15 @@ int pci_read_config_byte(int bus, int dev, int fn, int reg, unsigned char* val){
return ret_val;
}
int pci_write_config_byte(int bus, int dev, int fn, int reg, unsigned char val){
int pci_write_config_byte (int bus, int dev, int fn, int reg,
unsigned char val)
{
return PCIWriteConfig (bus, dev, fn, reg, 1, val);
}
int pci_read_config_word(int bus, int dev, int fn, int reg, unsigned short* val){
int pci_read_config_word (int bus, int dev, int fn, int reg,
unsigned short *val)
{
unsigned long read_val;
int ret_val;
@ -277,21 +291,29 @@ int pci_read_config_word(int bus, int dev, int fn, int reg, unsigned short* val)
return ret_val;
}
int pci_write_config_word(int bus, int dev, int fn, int reg, unsigned short val){
int pci_write_config_word (int bus, int dev, int fn, int reg,
unsigned short val)
{
return PCIWriteConfig (bus, dev, fn, reg, 2, val);
}
int pci_read_config_dword(int bus, int dev, int fn, int reg, unsigned long* val){
int pci_read_config_dword (int bus, int dev, int fn, int reg,
unsigned long *val)
{
return PCIReadConfig (bus, dev, fn, reg, 4, val);
}
int pci_write_config_dword(int bus, int dev, int fn, int reg, unsigned long val){
int pci_write_config_dword (int bus, int dev, int fn, int reg,
unsigned long val)
{
return PCIWriteConfig (bus, dev, fn, reg, 4, val);
}
#endif /* INCLUDE_PCI */
int I2CAccess(unsigned char theI2CAddress, unsigned char theDevCode, unsigned char theChipSel, unsigned char* theValue, int RWFlag){
int I2CAccess (unsigned char theI2CAddress, unsigned char theDevCode,
unsigned char theChipSel, unsigned char *theValue, int RWFlag)
{
int ret_val = 0;
unsigned int reg_value;
@ -300,8 +322,7 @@ int I2CAccess(unsigned char theI2CAddress, unsigned char theDevCode, unsigned ch
if (reg_value & I2C_CSR_ACT) {
printf ("Error: I2C busy\n");
ret_val = I2C_BUSY;
}
else{
} else {
reg_value = ((theI2CAddress & 0xFF) << 24)
| ((theDevCode & 0x0F) << 12)
| ((theChipSel & 0x07) << 9)
@ -319,9 +340,10 @@ int I2CAccess(unsigned char theI2CAddress, unsigned char theDevCode, unsigned ch
if ((reg_value & I2C_CSR_ACT) == 0) {
if (reg_value & I2C_CSR_ERR) {
ret_val = I2C_ERR;
}
else{
*theValue = (reg_value & I2C_CSR_DATA) >> 16;
} else {
*theValue =
(reg_value & I2C_CSR_DATA) >>
16;
}
}
} while (reg_value & I2C_CSR_ACT);
@ -330,15 +352,20 @@ int I2CAccess(unsigned char theI2CAddress, unsigned char theDevCode, unsigned ch
return ret_val;
}
int EEPROMRead(unsigned char theI2CAddress, unsigned char* theValue){
return I2CAccess(theI2CAddress, I2C_EEPROM_DEV, I2C_EEPROM_CHIP_SEL, theValue, I2C_READ);
int EEPROMRead (unsigned char theI2CAddress, unsigned char *theValue)
{
return I2CAccess (theI2CAddress, I2C_EEPROM_DEV, I2C_EEPROM_CHIP_SEL,
theValue, I2C_READ);
}
int EEPROMWrite(unsigned char theI2CAddress, unsigned char theValue){
return I2CAccess(theI2CAddress, I2C_EEPROM_DEV, I2C_EEPROM_CHIP_SEL, &theValue, I2C_WRITE);
int EEPROMWrite (unsigned char theI2CAddress, unsigned char theValue)
{
return I2CAccess (theI2CAddress, I2C_EEPROM_DEV, I2C_EEPROM_CHIP_SEL,
&theValue, I2C_WRITE);
}
int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
int do_eeprom (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
char cmd;
int ret_val = 0;
unsigned int address = 0;
@ -362,17 +389,17 @@ int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
}
switch (cmd) {
case 'r':{
case 'r':
if (address > 256) {
printf ("Illegal Address\n");
goto usage;
}
printf ("@0x%x: ", address);
for (ii = 0; ii < value; ii++) {
if(EEPROMRead(address + ii, &read_value) != 0){
if (EEPROMRead (address + ii, &read_value) !=
0) {
printf ("Read Error\n");
}
else{
} else {
printf ("0x%02x ", read_value);
}
@ -382,8 +409,7 @@ int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
}
printf ("\n");
break;
}
case 'w':{
case 'w':
if (address > 256) {
printf ("Illegal Address\n");
goto usage;
@ -395,30 +421,29 @@ int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
printf ("Write Error\n");
}
break;
}
case 'g':{
case 'g':
if (argc != 3) {
goto usage;
}
mem_ptr = (unsigned char *) address;
for(ii = 0;((ii < EEPROM_LENGTH) && (error == 0));ii++){
for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0));
ii++) {
if (EEPROMRead (ii, &read_value) != 0) {
printf ("Read Error\n");
error = 1;
}
else{
} else {
*mem_ptr = read_value;
mem_ptr++;
}
}
break;
}
case 'p':{
case 'p':
if (argc != 3) {
goto usage;
}
mem_ptr = (unsigned char *) address;
for(ii = 0;((ii < EEPROM_LENGTH) && (error == 0));ii++){
for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0));
ii++) {
if (EEPROMWrite (ii, *mem_ptr) != 0) {
printf ("Write Error\n");
error = 1;
@ -427,23 +452,21 @@ int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
mem_ptr++;
}
break;
}
case 'd':{
case 'd':
if (argc != 2) {
goto usage;
}
for(ii = 0;((ii < EEPROM_LENGTH) && (error == 0));ii++){
for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0));
ii++) {
if (EEPROMWrite (ii, default_eeprom[ii]) != 0) {
printf ("Write Error\n");
error = 1;
}
}
break;
}
default:{
default:
goto usage;
}
}
goto done;
usage:
@ -454,8 +477,7 @@ int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
}
U_BOOT_CMD(
eeprom, 4, 0, do_eeprom,
U_BOOT_CMD (eeprom, 4, 0, do_eeprom,
"eeprom - read/write/copy to/from the PowerSpan II eeprom\n",
"eeprom r OFF [NUM]\n"
" - read NUM words starting at OFF\n"
@ -465,12 +487,12 @@ U_BOOT_CMD(
" - store contents of eeprom at address ADD\n"
"eeprom p ADD\n"
" - put data stored at address ADD into the eeprom\n"
"eeprom d\n"
" - return eeprom to default contents\n"
);
"eeprom d\n" " - return eeprom to default contents\n");
unsigned int PowerSpanRead(unsigned int theOffset){
volatile unsigned int* ptr = (volatile unsigned int*)(PSPAN_BASEADDR + theOffset);
unsigned int PowerSpanRead (unsigned int theOffset)
{
volatile unsigned int *ptr =
(volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
unsigned int ret_val;
#ifdef VERBOSITY
@ -490,11 +512,14 @@ unsigned int PowerSpanRead(unsigned int theOffset){
return ret_val;
}
void PowerSpanWrite(unsigned int theOffset, unsigned int theValue){
volatile unsigned int* ptr = (volatile unsigned int*)(PSPAN_BASEADDR + theOffset);
void PowerSpanWrite (unsigned int theOffset, unsigned int theValue)
{
volatile unsigned int *ptr =
(volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
#ifdef VERBOSITY
if (gVerbosityLevel > 1) {
printf("PowerSpanWrite: offset=%08x val=%02x\n", theOffset, theValue);
printf ("PowerSpanWrite: offset=%08x val=%02x\n", theOffset,
theValue);
}
#endif
*ptr = theValue;
@ -506,13 +531,16 @@ void PowerSpanWrite(unsigned int theOffset, unsigned int theValue){
* @param theOffset [IN] the register to access.
* @param theMask [IN] bits set in theMask will be set in the register.
*/
void PowerSpanSetBits(unsigned int theOffset, unsigned int theMask){
volatile unsigned int* ptr = (volatile unsigned int*)(PSPAN_BASEADDR + theOffset);
void PowerSpanSetBits (unsigned int theOffset, unsigned int theMask)
{
volatile unsigned int *ptr =
(volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
unsigned int register_value;
#ifdef VERBOSITY
if (gVerbosityLevel > 1) {
printf("PowerSpanSetBits: offset=%08x mask=%02x\n", theOffset, theMask);
printf ("PowerSpanSetBits: offset=%08x mask=%02x\n",
theOffset, theMask);
}
#endif
register_value = *ptr;
@ -528,13 +556,16 @@ void PowerSpanSetBits(unsigned int theOffset, unsigned int theMask){
* @param theOffset [IN] the register to access.
* @param theMask [IN] bits set in theMask will be cleared in the register.
*/
void PowerSpanClearBits(unsigned int theOffset, unsigned int theMask){
volatile unsigned int* ptr = (volatile unsigned int*)(PSPAN_BASEADDR + theOffset);
void PowerSpanClearBits (unsigned int theOffset, unsigned int theMask)
{
volatile unsigned int *ptr =
(volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
unsigned int register_value;
#ifdef VERBOSITY
if (gVerbosityLevel > 1) {
printf("PowerSpanClearBits: offset=%08x mask=%02x\n", theOffset, theMask);
printf ("PowerSpanClearBits: offset=%08x mask=%02x\n",
theOffset, theMask);
}
#endif
register_value = *ptr;
@ -556,12 +587,16 @@ void PowerSpanClearBits(unsigned int theOffset, unsigned int theMask){
* @param theLocalBaseAddr [IN] the Local address for the image (assumed to be valid with provided block size).
* @param thePCIBaseAddr [IN] the PCI address for the image (assumed to be valid with provided block size).
*/
int SetSlaveImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag, int theEndianness, unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr){
int SetSlaveImage (int theImageIndex, unsigned int theBlockSize,
int theMemIOFlag, int theEndianness,
unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr)
{
unsigned int reg_offset = theImageIndex * PB_SLAVE_IMAGE_OFF;
unsigned int reg_value = 0;
/* Make sure that the Slave Image is disabled */
PowerSpanClearBits((REGS_PB_SLAVE_CSR + reg_offset), PB_SLAVE_CSR_IMG_EN);
PowerSpanClearBits ((REGS_PB_SLAVE_CSR + reg_offset),
PB_SLAVE_CSR_IMG_EN);
/* Setup the mask required for requested PB Slave Image configuration */
reg_value = PB_SLAVE_CSR_TA_EN | theEndianness | (theBlockSize << 24);
@ -583,7 +618,8 @@ int SetSlaveImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag
PowerSpanWrite ((REGS_PB_SLAVE_TADDR + reg_offset), thePCIBaseAddr);
/* Enable the Slave Image */
PowerSpanSetBits((REGS_PB_SLAVE_CSR + reg_offset), PB_SLAVE_CSR_IMG_EN);
PowerSpanSetBits ((REGS_PB_SLAVE_CSR + reg_offset),
PB_SLAVE_CSR_IMG_EN);
return 0;
}
@ -602,16 +638,23 @@ int SetSlaveImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag
* @param theLocalBaseAddr [IN] the Local address for the image (assumed to be valid with provided block size).
* @param thePCIBaseAddr [IN] the PCI address for the image (assumed to be valid with provided block size).
*/
int SetTargetImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag, int theEndianness, unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr){
int SetTargetImage (int theImageIndex, unsigned int theBlockSize,
int theMemIOFlag, int theEndianness,
unsigned int theLocalBaseAddr,
unsigned int thePCIBaseAddr)
{
unsigned int csr_reg_offset = theImageIndex * P1_TGT_IMAGE_OFF;
unsigned int pci_reg_offset = theImageIndex * P1_BST_OFF;
unsigned int reg_value = 0;
/* Make sure that the Slave Image is disabled */
PowerSpanClearBits((REGS_P1_TGT_CSR + csr_reg_offset), PB_SLAVE_CSR_IMG_EN);
PowerSpanClearBits ((REGS_P1_TGT_CSR + csr_reg_offset),
PB_SLAVE_CSR_IMG_EN);
/* Setup the mask required for requested PB Slave Image configuration */
reg_value = PX_TGT_CSR_TA_EN | PX_TGT_CSR_BAR_EN | (theBlockSize << 24) | PX_TGT_CSR_RTT_READ | PX_TGT_CSR_WTT_WFLUSH | theEndianness;
reg_value =
PX_TGT_CSR_TA_EN | PX_TGT_CSR_BAR_EN | (theBlockSize << 24) |
PX_TGT_CSR_RTT_READ | PX_TGT_CSR_WTT_WFLUSH | theEndianness;
if (theMemIOFlag == PX_TGT_USE_MEM_IO) {
reg_value |= PX_TGT_MEM_IO;
}
@ -632,19 +675,23 @@ int SetTargetImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFla
*/
PowerSpanWrite ((REGS_P1_TGT_CSR + csr_reg_offset), reg_value);
PowerSpanWrite((REGS_P1_TGT_TADDR + csr_reg_offset), theLocalBaseAddr);
PowerSpanWrite ((REGS_P1_TGT_TADDR + csr_reg_offset),
theLocalBaseAddr);
if (thePCIBaseAddr != (unsigned int) NULL) {
PowerSpanWrite((REGS_P1_BST + pci_reg_offset), thePCIBaseAddr);
PowerSpanWrite ((REGS_P1_BST + pci_reg_offset),
thePCIBaseAddr);
}
/* Enable the Slave Image */
PowerSpanSetBits((REGS_P1_TGT_CSR + csr_reg_offset), PB_SLAVE_CSR_IMG_EN);
PowerSpanSetBits ((REGS_P1_TGT_CSR + csr_reg_offset),
PB_SLAVE_CSR_IMG_EN);
return 0;
}
int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
int do_bridge (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
char cmd;
int ret_val = 1;
unsigned int image_index;
@ -668,36 +715,31 @@ int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
switch (cmd) {
case 'i':{
case 'i':
if (tolower (endianness) == 'b') {
endianness = PX_TGT_CSR_BIG_END;
}
else if(tolower(endianness) == 'l'){
} else if (tolower (endianness) == 'l') {
endianness = PX_TGT_CSR_TRUE_LEND;
}
else{
} else {
goto usage;
}
SetTargetImage(image_index, block_size, mem_io, endianness, local_addr, pci_addr);
SetTargetImage (image_index, block_size, mem_io,
endianness, local_addr, pci_addr);
break;
}
case 'o':{
case 'o':
if (tolower (endianness) == 'b') {
endianness = PB_SLAVE_CSR_BIG_END;
}
else if(tolower(endianness) == 'l'){
} else if (tolower (endianness) == 'l') {
endianness = PB_SLAVE_CSR_TRUE_LEND;
}
else{
} else {
goto usage;
}
SetSlaveImage(image_index, block_size, mem_io, endianness, local_addr, pci_addr);
SetSlaveImage (image_index, block_size, mem_io,
endianness, local_addr, pci_addr);
break;
}
default:{
default:
goto usage;
}
}
goto done;
usage:
@ -705,8 +747,4 @@ int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){
done:
return ret_val;
}

37
board/amirix/ap1000/serial.c
View file

@ -31,14 +31,14 @@
#include "serial.h"
#endif
const NS16550_t COM_PORTS[] = { (NS16550_t) CFG_NS16550_COM1, (NS16550_t) CFG_NS16550_COM2 };
const NS16550_t COM_PORTS[] =
{ (NS16550_t) CFG_NS16550_COM1, (NS16550_t) CFG_NS16550_COM2 };
#undef CFG_DUART_CHAN
#define CFG_DUART_CHAN gComPort
static int gComPort = 0;
int
serial_init (void)
int serial_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
@ -48,11 +48,9 @@ serial_init (void)
gComPort = 0;
return 0;
}
void
serial_putc(const char c)
void serial_putc (const char c)
{
if (c == '\n') {
NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r');
@ -61,20 +59,17 @@ serial_putc(const char c)
NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c);
}
int
serial_getc(void)
int serial_getc (void)
{
return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]);
}
int
serial_tstc(void)
int serial_tstc (void)
{
return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]);
}
void
serial_setbrg (void)
void serial_setbrg (void)
{
DECLARE_GLOBAL_DATA_PTR;
@ -88,8 +83,7 @@ serial_setbrg (void)
#endif
}
void
serial_puts (const char *s)
void serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
@ -97,31 +91,26 @@ serial_puts (const char *s)
}
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
void
kgdb_serial_init(void)
void kgdb_serial_init (void)
{
}
void
putDebugChar (int c)
void putDebugChar (int c)
{
serial_putc (c);
}
void
putDebugStr (const char *str)
void putDebugStr (const char *str)
{
serial_puts (str);
}
int
getDebugChar (void)
int getDebugChar (void)
{
return serial_getc ();
}
void
kgdb_interruptible (int yes)
void kgdb_interruptible (int yes)
{
return;
}

14
cpu/arm720t/serial_netarm.c
View file

@ -35,7 +35,11 @@
#include <asm/hardware.h>
#define PORTA (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTA))
#if !defined(CONFIG_NETARM_NS7520)
#define PORTB (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTB))
#else
#define PORTC (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTC))
#endif
/* wait until transmitter is ready for another character */
#define TXWAITRDY(registers) \
@ -48,8 +52,13 @@
}
#ifndef CONFIG_UART1_CONSOLE
volatile netarm_serial_channel_t *serial_reg_ch1 = get_serial_channel(0);
volatile netarm_serial_channel_t *serial_reg_ch2 = get_serial_channel(1);
#else
volatile netarm_serial_channel_t *serial_reg_ch1 = get_serial_channel(1);
volatile netarm_serial_channel_t *serial_reg_ch2 = get_serial_channel(0);
#endif
extern void _netarm_led_FAIL1(void);
@ -62,8 +71,13 @@ void serial_setbrg (void)
DECLARE_GLOBAL_DATA_PTR;
/* set 0 ... make sure pins are configured for serial */
#if !defined(CONFIG_NETARM_NS7520)
PORTA = PORTB =
NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0);
#else
PORTA = NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0);
PORTC = NETARM_GEN_PORT_CSF (0xef) | NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0);
#endif
/* first turn em off */
serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a = 0;

3
cpu/arm720t/start.S
View file

@ -272,12 +272,15 @@ cpu_init_crit:
str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
#ifndef CONFIG_NETARM_PLL_BYPASS
ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
NETARM_GEN_PLL_CTL_POLTST_DEF | \
NETARM_GEN_PLL_CTL_INDIV(1) | \
NETARM_GEN_PLL_CTL_ICP_DEF | \
NETARM_GEN_PLL_CTL_OUTDIV(2) )
str r1, [r0, #+NETARM_GEN_PLL_CONTROL]
#endif
/*
* mask all IRQs by clearing all bits in the INTMRs
*/

2
drivers/Makefile
View file

@ -34,7 +34,7 @@ OBJS = 3c589.o 5701rls.o ali512x.o \
i8042.o i82365.o inca-ip_sw.o keyboard.o \
lan91c96.o \
natsemi.o ne2000.o netarm_eth.o netconsole.o \
ns16550.o ns8382x.o ns87308.o omap1510_i2c.o \
ns16550.o ns8382x.o ns87308.o ns7520_eth.o omap1510_i2c.o \
omap24xx_i2c.o pci.o pci_auto.o pci_indirect.o \
pcnet.o plb2800_eth.o \
ps2ser.o ps2mult.o pc_keyb.o \

849
drivers/ns7520_eth.c Normal file
View file

@ -0,0 +1,849 @@
/***********************************************************************
*
* Copyright (C) 2005 by Videon Central, Inc.
*
* $Id$
* @Author: Arthur Shipkowski
* @Descr: Ethernet driver for the NS7520. Uses polled Ethernet, like
* the older netarmeth driver. Note that attempting to filter
* broadcast and multicast out in the SAFR register will cause
* bad things due to released errata.
* @References: [1] NS7520 Hardware Reference, December 2003
* [2] Intel LXT971 Datasheet #249414 Rev. 02
*
***********************************************************************/
#include <common.h>
#if defined(CONFIG_DRIVER_NS7520_ETHERNET)
#include <net.h> /* NetSendPacket */
#include <asm/arch/netarm_registers.h>
#include <asm/arch/netarm_dma_module.h>
#include "ns7520_eth.h" /* for Ethernet and PHY */
/**
* Send an error message to the terminal.
*/
#define ERROR(x) \
do { \
char *__foo = strrchr(__FILE__, '/'); \
\
printf("%s: %d: %s(): ", (__foo == NULL ? __FILE__ : (__foo + 1)), \
__LINE__, __FUNCTION__); \
printf x; printf("\n"); \
} while (0);
/* some definition to make transistion to linux easier */
#define NS7520_DRIVER_NAME "eth"
#define KERN_WARNING "Warning:"
#define KERN_ERR "Error:"
#define KERN_INFO "Info:"
#if 1
# define DEBUG
#endif
#ifdef DEBUG
# define printk printf
# define DEBUG_INIT 0x0001
# define DEBUG_MINOR 0x0002
# define DEBUG_RX 0x0004
# define DEBUG_TX 0x0008
# define DEBUG_INT 0x0010
# define DEBUG_POLL 0x0020
# define DEBUG_LINK 0x0040
# define DEBUG_MII 0x0100
# define DEBUG_MII_LOW 0x0200
# define DEBUG_MEM 0x0400
# define DEBUG_ERROR 0x4000
# define DEBUG_ERROR_CRIT 0x8000
static int nDebugLvl = DEBUG_ERROR_CRIT;
# define DEBUG_ARGS0( FLG, a0 ) if( ( nDebugLvl & (FLG) ) == (FLG) ) \
printf("%s: " a0, __FUNCTION__, 0, 0, 0, 0, 0, 0 )
# define DEBUG_ARGS1( FLG, a0, a1 ) if( ( nDebugLvl & (FLG) ) == (FLG)) \
printf("%s: " a0, __FUNCTION__, (int)(a1), 0, 0, 0, 0, 0 )
# define DEBUG_ARGS2( FLG, a0, a1, a2 ) if( (nDebugLvl & (FLG)) ==(FLG))\
printf("%s: " a0, __FUNCTION__, (int)(a1), (int)(a2), 0, 0,0,0 )
# define DEBUG_ARGS3( FLG, a0, a1, a2, a3 ) if((nDebugLvl &(FLG))==(FLG))\
printf("%s: "a0,__FUNCTION__,(int)(a1),(int)(a2),(int)(a3),0,0,0)
# define DEBUG_FN( FLG ) if( (nDebugLvl & (FLG)) == (FLG) ) \
printf("\r%s:line %d\n", (int)__FUNCTION__, __LINE__, 0,0,0,0);
# define ASSERT( expr, func ) if( !( expr ) ) { \
printf( "Assertion failed! %s:line %d %s\n", \
(int)__FUNCTION__,__LINE__,(int)(#expr),0,0,0); \
func }
#else /* DEBUG */
# define printk(...)
# define DEBUG_ARGS0( FLG, a0 )
# define DEBUG_ARGS1( FLG, a0, a1 )
# define DEBUG_ARGS2( FLG, a0, a1, a2 )
# define DEBUG_ARGS3( FLG, a0, a1, a2, a3 )
# define DEBUG_FN( n )
# define ASSERT(expr, func)
#endif /* DEBUG */
#define NS7520_MII_NEG_DELAY (5*CFG_HZ) /* in s */
#define TX_TIMEOUT (5*CFG_HZ) /* in s */
#define RX_STALL_WORKAROUND_CNT 100
static int ns7520_eth_reset(void);
static void ns7520_link_auto_negotiate(void);
static void ns7520_link_update_egcr(void);
static void ns7520_link_print_changed(void);
/* the PHY stuff */
static char ns7520_mii_identify_phy(void);
static unsigned short ns7520_mii_read(unsigned short uiRegister);
static void ns7520_mii_write(unsigned short uiRegister,
unsigned short uiData);
static unsigned int ns7520_mii_get_clock_divisor(unsigned int
unMaxMDIOClk);
static unsigned int ns7520_mii_poll_busy(void);
static unsigned int nPhyMaxMdioClock = PHY_MDIO_MAX_CLK;
static unsigned int uiLastLinkStatus;
static PhyType phyDetected = PHY_NONE;
/***********************************************************************
* @Function: eth_init
* @Return: -1 on failure otherwise 0
* @Descr: Initializes the ethernet engine and uses either FS Forth's default
* MAC addr or the one in environment
***********************************************************************/
int eth_init(bd_t * pbis)
{
unsigned char aucMACAddr[6];
char *pcTmp = getenv("ethaddr");
char *pcEnd;
int i;
DEBUG_FN(DEBUG_INIT);
/* no need to check for hardware */
if (!ns7520_eth_reset())
return -1;
if (NULL == pcTmp)
return -1;
for (i = 0; i < 6; i++) {
aucMACAddr[i] =
pcTmp ? simple_strtoul(pcTmp, &pcEnd, 16) : 0;
pcTmp = (*pcTmp) ? pcEnd + 1 : pcEnd;
}
/* configure ethernet address */
*get_eth_reg_addr(NS7520_ETH_SA1) =
aucMACAddr[5] << 8 | aucMACAddr[4];
*get_eth_reg_addr(NS7520_ETH_SA2) =
aucMACAddr[3] << 8 | aucMACAddr[2];
*get_eth_reg_addr(NS7520_ETH_SA3) =
aucMACAddr[1] << 8 | aucMACAddr[0];
/* enable hardware */
*get_eth_reg_addr(NS7520_ETH_MAC1) = NS7520_ETH_MAC1_RXEN;
*get_eth_reg_addr(NS7520_ETH_SUPP) = NS7520_ETH_SUPP_JABBER;
*get_eth_reg_addr(NS7520_ETH_MAC1) = NS7520_ETH_MAC1_RXEN;
/* the linux kernel may give packets < 60 bytes, for example arp */
*get_eth_reg_addr(NS7520_ETH_MAC2) = NS7520_ETH_MAC2_CRCEN |
NS7520_ETH_MAC2_PADEN | NS7520_ETH_MAC2_HUGE;
/* Broadcast/multicast allowed; if you don't set this even unicast chokes */
/* Based on NS7520 errata documentation */
*get_eth_reg_addr(NS7520_ETH_SAFR) =
NS7520_ETH_SAFR_BROAD | NS7520_ETH_SAFR_PRM;
/* enable receive and transmit FIFO, use 10/100 Mbps MII */
*get_eth_reg_addr(NS7520_ETH_EGCR) |=
NS7520_ETH_EGCR_ETXWM_75 |
NS7520_ETH_EGCR_ERX |
NS7520_ETH_EGCR_ERXREG |
NS7520_ETH_EGCR_ERXBR | NS7520_ETH_EGCR_ETX;
return 0;
}
/***********************************************************************
* @Function: eth_send
* @Return: -1 on timeout otherwise 1
* @Descr: sends one frame by DMA
***********************************************************************/
int eth_send(volatile void *pPacket, int nLen)
{
int i, length32, retval = 1;
char *pa;
unsigned int *pa32, lastp = 0, rest;
unsigned int status;
pa = (char *) pPacket;
pa32 = (unsigned int *) pPacket;
length32 = nLen / 4;
rest = nLen % 4;
/* make sure there's no garbage in the last word */
switch (rest) {
case 0:
lastp = pa32[length32 - 1];
length32--;
break;
case 1:
lastp = pa32[length32] & 0x000000ff;
break;
case 2:
lastp = pa32[length32] & 0x0000ffff;
break;
case 3:
lastp = pa32[length32] & 0x00ffffff;
break;
}
while (((*get_eth_reg_addr(NS7520_ETH_EGSR)) &
NS7520_ETH_EGSR_TXREGE)
== 0) {
}
/* write to the fifo */
for (i = 0; i < length32; i++)
*get_eth_reg_addr(NS7520_ETH_FIFO) = pa32[i];
/* the last word is written to an extra register, this
starts the transmission */
*get_eth_reg_addr(NS7520_ETH_FIFOL) = lastp;
/* Wait for it to be done */
while ((*get_eth_reg_addr(NS7520_ETH_EGSR) & NS7520_ETH_EGSR_TXBC)
== 0) {
}
status = (*get_eth_reg_addr(NS7520_ETH_ETSR));
*get_eth_reg_addr(NS7520_ETH_EGSR) = NS7520_ETH_EGSR_TXBC; /* Clear it now */
if (status & NS7520_ETH_ETSR_TXOK) {
retval = 0; /* We're OK! */
} else if (status & NS7520_ETH_ETSR_TXDEF) {
printf("Deferred, we'll see.\n");
retval = 0;
} else if (status & NS7520_ETH_ETSR_TXAL) {
printf("Late collision error, %d collisions.\n",
(*get_eth_reg_addr(NS7520_ETH_ETSR)) &
NS7520_ETH_ETSR_TXCOLC);
} else if (status & NS7520_ETH_ETSR_TXAEC) {
printf("Excessive collisions: %d\n",
(*get_eth_reg_addr(NS7520_ETH_ETSR)) &
NS7520_ETH_ETSR_TXCOLC);
} else if (status & NS7520_ETH_ETSR_TXAED) {
printf("Excessive deferral on xmit.\n");
} else if (status & NS7520_ETH_ETSR_TXAUR) {
printf("Packet underrun.\n");
} else if (status & NS7520_ETH_ETSR_TXAJ) {
printf("Jumbo packet error.\n");
} else {
printf("Error: Should never get here.\n");
}
return (retval);
}
/***********************************************************************
* @Function: eth_rx
* @Return: size of last frame in bytes or 0 if no frame available
* @Descr: gives one frame to U-Boot which has been copied by DMA engine already
* to NetRxPackets[ 0 ].
***********************************************************************/
int eth_rx(void)
{
int i;
unsigned short rxlen;
unsigned short totrxlen = 0;
unsigned int *addr;
unsigned int rxstatus, lastrxlen;
char *pa;
/* If RXBR is 1, data block was received */
while (((*get_eth_reg_addr(NS7520_ETH_EGSR)) &
NS7520_ETH_EGSR_RXBR) == NS7520_ETH_EGSR_RXBR) {
/* get status register and the length of received block */
rxstatus = *get_eth_reg_addr(NS7520_ETH_ERSR);
rxlen = (rxstatus & NS7520_ETH_ERSR_RXSIZE) >> 16;
/* clear RXBR to make fifo available */
*get_eth_reg_addr(NS7520_ETH_EGSR) = NS7520_ETH_EGSR_RXBR;
if (rxstatus & NS7520_ETH_ERSR_ROVER) {
printf("Receive overrun, resetting FIFO.\n");
*get_eth_reg_addr(NS7520_ETH_EGCR) &=
~NS7520_ETH_EGCR_ERX;
udelay(20);
*get_eth_reg_addr(NS7520_ETH_EGCR) |=
NS7520_ETH_EGCR_ERX;
}
if (rxlen == 0) {
printf("Nothing.\n");
return 0;
}
addr = (unsigned int *) NetRxPackets[0];
pa = (char *) NetRxPackets[0];
/* read the fifo */
for (i = 0; i < rxlen / 4; i++) {
*addr = *get_eth_reg_addr(NS7520_ETH_FIFO);
addr++;
}
if ((*get_eth_reg_addr(NS7520_ETH_EGSR)) &
NS7520_ETH_EGSR_RXREGR) {
/* RXFDB indicates wether the last word is 1,2,3 or 4 bytes long */
lastrxlen =
((*get_eth_reg_addr(NS7520_ETH_EGSR)) &
NS7520_ETH_EGSR_RXFDB_MA) >> 28;
*addr = *get_eth_reg_addr(NS7520_ETH_FIFO);
switch (lastrxlen) {
case 1:
*addr &= 0xff000000;
break;
case 2:
*addr &= 0xffff0000;
break;
case 3:
*addr &= 0xffffff00;
break;
}
}
/* Pass the packet up to the protocol layers. */
NetReceive(NetRxPackets[0], rxlen - 4);
totrxlen += rxlen - 4;
}
return totrxlen;
}
/***********************************************************************
* @Function: eth_halt
* @Return: n/a
* @Descr: stops the ethernet engine
***********************************************************************/
void eth_halt(void)
{
DEBUG_FN(DEBUG_INIT);
*get_eth_reg_addr(NS7520_ETH_MAC1) &= ~NS7520_ETH_MAC1_RXEN;
*get_eth_reg_addr(NS7520_ETH_EGCR) &= ~(NS7520_ETH_EGCR_ERX |
NS7520_ETH_EGCR_ERXDMA |
NS7520_ETH_EGCR_ERXREG |
NS7520_ETH_EGCR_ERXBR |
NS7520_ETH_EGCR_ETX |
NS7520_ETH_EGCR_ETXDMA);
}
/***********************************************************************
* @Function: ns7520_eth_reset
* @Return: 0 on failure otherwise 1
* @Descr: resets the ethernet interface and the PHY,
* performs auto negotiation or fixed modes
***********************************************************************/
static int ns7520_eth_reset(void)
{
DEBUG_FN(DEBUG_MINOR);
/* Reset important registers */
*get_eth_reg_addr(NS7520_ETH_EGCR) = 0; /* Null it out! */
*get_eth_reg_addr(NS7520_ETH_MAC1) &= NS7520_ETH_MAC1_SRST;
*get_eth_reg_addr(NS7520_ETH_MAC2) = 0;
/* Reset MAC */
*get_eth_reg_addr(NS7520_ETH_EGCR) |= NS7520_ETH_EGCR_MAC_RES;
udelay(5);
*get_eth_reg_addr(NS7520_ETH_EGCR) &= ~NS7520_ETH_EGCR_MAC_RES;
/* reset and initialize PHY */
*get_eth_reg_addr(NS7520_ETH_MAC1) &= ~NS7520_ETH_MAC1_SRST;
/* we don't support hot plugging of PHY, therefore we don't reset
phyDetected and nPhyMaxMdioClock here. The risk is if the setting is
incorrect the first open
may detect the PHY correctly but succeding will fail
For reseting the PHY and identifying we have to use the standard
MDIO CLOCK value 2.5 MHz only after hardware reset
After having identified the PHY we will do faster */
*get_eth_reg_addr(NS7520_ETH_MCFG) =
ns7520_mii_get_clock_divisor(nPhyMaxMdioClock);
/* reset PHY */
ns7520_mii_write(PHY_COMMON_CTRL, PHY_COMMON_CTRL_RESET);
ns7520_mii_write(PHY_COMMON_CTRL, 0);
udelay(3000); /* [2] p.70 says at least 300us reset recovery time. */
/* MII clock has been setup to default, ns7520_mii_identify_phy should
work for all */
if (!ns7520_mii_identify_phy()) {
printk(KERN_ERR NS7520_DRIVER_NAME
": Unsupported PHY, aborting\n");
return 0;
}
/* now take the highest MDIO clock possible after detection */
*get_eth_reg_addr(NS7520_ETH_MCFG) =
ns7520_mii_get_clock_divisor(nPhyMaxMdioClock);
/* PHY has been detected, so there can be no abort reason and we can
finish initializing ethernet */
uiLastLinkStatus = 0xff; /* undefined */
ns7520_link_auto_negotiate();
if (phyDetected == PHY_LXT971A)
/* set LED2 to link mode */
ns7520_mii_write(PHY_LXT971_LED_CFG,
(PHY_LXT971_LED_CFG_LINK_ACT <<
PHY_LXT971_LED_CFG_SHIFT_LED2) |
(PHY_LXT971_LED_CFG_TRANSMIT <<
PHY_LXT971_LED_CFG_SHIFT_LED1));
return 1;
}
/***********************************************************************
* @Function: ns7520_link_auto_negotiate
* @Return: void
* @Descr: performs auto-negotation of link.
***********************************************************************/
static void ns7520_link_auto_negotiate(void)
{
unsigned long ulStartJiffies;
unsigned short uiStatus;
DEBUG_FN(DEBUG_LINK);
/* run auto-negotation */
/* define what we are capable of */
ns7520_mii_write(PHY_COMMON_AUTO_ADV,
PHY_COMMON_AUTO_ADV_100BTXFD |
PHY_COMMON_AUTO_ADV_100BTX |
PHY_COMMON_AUTO_ADV_10BTFD |
PHY_COMMON_AUTO_ADV_10BT |
PHY_COMMON_AUTO_ADV_802_3);
/* start auto-negotiation */
ns7520_mii_write(PHY_COMMON_CTRL,
PHY_COMMON_CTRL_AUTO_NEG |
PHY_COMMON_CTRL_RES_AUTO);
/* wait for completion */
ulStartJiffies = get_timer(0);
while (get_timer(0) < ulStartJiffies + NS7520_MII_NEG_DELAY) {
uiStatus = ns7520_mii_read(PHY_COMMON_STAT);
if ((uiStatus &
(PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT))
==
(PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) {
/* lucky we are, auto-negotiation succeeded */
ns7520_link_print_changed();
ns7520_link_update_egcr();
return;
}
}
DEBUG_ARGS0(DEBUG_LINK, "auto-negotiation timed out\n");
/* ignore invalid link settings */
}
/***********************************************************************
* @Function: ns7520_link_update_egcr
* @Return: void
* @Descr: updates the EGCR and MAC2 link status after mode change or
* auto-negotation
***********************************************************************/
static void ns7520_link_update_egcr(void)
{
unsigned int unEGCR;
unsigned int unMAC2;
unsigned int unIPGT;
DEBUG_FN(DEBUG_LINK);
unEGCR = *get_eth_reg_addr(NS7520_ETH_EGCR);
unMAC2 = *get_eth_reg_addr(NS7520_ETH_MAC2);
unIPGT =
*get_eth_reg_addr(NS7520_ETH_IPGT) & ~NS7520_ETH_IPGT_IPGT;
unEGCR &= ~NS7520_ETH_EGCR_EFULLD;
unMAC2 &= ~NS7520_ETH_MAC2_FULLD;
if ((uiLastLinkStatus & PHY_LXT971_STAT2_DUPLEX_MODE)
== PHY_LXT971_STAT2_DUPLEX_MODE) {
unEGCR |= NS7520_ETH_EGCR_EFULLD;
unMAC2 |= NS7520_ETH_MAC2_FULLD;
unIPGT |= 0x15; /* see [1] p. 167 */
} else
unIPGT |= 0x12; /* see [1] p. 167 */
*get_eth_reg_addr(NS7520_ETH_MAC2) = unMAC2;
*get_eth_reg_addr(NS7520_ETH_EGCR) = unEGCR;
*get_eth_reg_addr(NS7520_ETH_IPGT) = unIPGT;
}
/***********************************************************************
* @Function: ns7520_link_print_changed
* @Return: void
* @Descr: checks whether the link status has changed and if so prints
* the new mode
***********************************************************************/
static void ns7520_link_print_changed(void)
{
unsigned short uiStatus;
unsigned short uiControl;
DEBUG_FN(DEBUG_LINK);
uiControl = ns7520_mii_read(PHY_COMMON_CTRL);
if ((uiControl & PHY_COMMON_CTRL_AUTO_NEG) ==
PHY_COMMON_CTRL_AUTO_NEG) {
/* PHY_COMMON_STAT_LNK_STAT is only set on autonegotiation */
uiStatus = ns7520_mii_read(PHY_COMMON_STAT);
if (!(uiStatus & PHY_COMMON_STAT_LNK_STAT)) {
printk(KERN_WARNING NS7520_DRIVER_NAME
": link down\n");
/* @TODO Linux: carrier_off */
} else {
/* @TODO Linux: carrier_on */
if (phyDetected == PHY_LXT971A) {
uiStatus =
ns7520_mii_read(PHY_LXT971_STAT2);
uiStatus &=
(PHY_LXT971_STAT2_100BTX |
PHY_LXT971_STAT2_DUPLEX_MODE |
PHY_LXT971_STAT2_AUTO_NEG);
/* mask out all uninteresting parts */
}
/* other PHYs must store there link information in
uiStatus as PHY_LXT971 */
}
} else {
/* mode has been forced, so uiStatus should be the same as the
last link status, enforce printing */
uiStatus = uiLastLinkStatus;
uiLastLinkStatus = 0xff;
}
if (uiStatus != uiLastLinkStatus) {
/* save current link status */
uiLastLinkStatus = uiStatus;
/* print new link status */
printk(KERN_INFO NS7520_DRIVER_NAME
": link mode %i Mbps %s duplex %s\n",
(uiStatus & PHY_LXT971_STAT2_100BTX) ? 100 : 10,
(uiStatus & PHY_LXT971_STAT2_DUPLEX_MODE) ? "full" :
"half",
(uiStatus & PHY_LXT971_STAT2_AUTO_NEG) ? "(auto)" :
"");
}
}
/***********************************************************************
* the MII low level stuff
***********************************************************************/
/***********************************************************************
* @Function: ns7520_mii_identify_phy
* @Return: 1 if supported PHY has been detected otherwise 0
* @Descr: checks for supported PHY and prints the IDs.
***********************************************************************/
static char ns7520_mii_identify_phy(void)
{
unsigned short uiID1;
unsigned short uiID2;
unsigned char *szName;
char cRes = 0;
DEBUG_FN(DEBUG_MII);
phyDetected = (PhyType) uiID1 = ns7520_mii_read(PHY_COMMON_ID1);
switch (phyDetected) {
case PHY_LXT971A:
szName = "LXT971A";
uiID2 = ns7520_mii_read(PHY_COMMON_ID2);
nPhyMaxMdioClock = PHY_LXT971_MDIO_MAX_CLK;
cRes = 1;
break;
case PHY_NONE:
default:
/* in case uiID1 == 0 && uiID2 == 0 we may have the wrong
address or reset sets the wrong NS7520_ETH_MCFG_CLKS */
uiID2 = 0;
szName = "unknown";
nPhyMaxMdioClock = PHY_MDIO_MAX_CLK;
phyDetected = PHY_NONE;
}
printk(KERN_INFO NS7520_DRIVER_NAME
": PHY (0x%x, 0x%x) = %s detected\n", uiID1, uiID2, szName);
return cRes;
}
/***********************************************************************
* @Function: ns7520_mii_read
* @Return: the data read from PHY register uiRegister
* @Descr: the data read may be invalid if timed out. If so, a message
* is printed but the invalid data is returned.
* The fixed device address is being used.
***********************************************************************/
static unsigned short ns7520_mii_read(unsigned short uiRegister)
{
DEBUG_FN(DEBUG_MII_LOW);
/* write MII register to be read */
*get_eth_reg_addr(NS7520_ETH_MADR) =
CONFIG_PHY_ADDR << 8 | uiRegister;
*get_eth_reg_addr(NS7520_ETH_MCMD) = NS7520_ETH_MCMD_READ;
if (!ns7520_mii_poll_busy())
printk(KERN_WARNING NS7520_DRIVER_NAME
": MII still busy in read\n");
/* continue to read */
*get_eth_reg_addr(NS7520_ETH_MCMD) = 0;
return (unsigned short) (*get_eth_reg_addr(NS7520_ETH_MRDD));
}
/***********************************************************************
* @Function: ns7520_mii_write
* @Return: nothing
* @Descr: writes the data to the PHY register. In case of a timeout,
* no special handling is performed but a message printed
* The fixed device address is being used.
***********************************************************************/
static void ns7520_mii_write(unsigned short uiRegister,
unsigned short uiData)
{
DEBUG_FN(DEBUG_MII_LOW);
/* write MII register to be written */
*get_eth_reg_addr(NS7520_ETH_MADR) =
CONFIG_PHY_ADDR << 8 | uiRegister;
*get_eth_reg_addr(NS7520_ETH_MWTD) = uiData;
if (!ns7520_mii_poll_busy()) {
printf(KERN_WARNING NS7520_DRIVER_NAME
": MII still busy in write\n");
}
}
/***********************************************************************
* @Function: ns7520_mii_get_clock_divisor
* @Return: the clock divisor that should be used in NS7520_ETH_MCFG_CLKS
* @Descr: if no clock divisor can be calculated for the
* current SYSCLK and the maximum MDIO Clock, a warning is printed
* and the greatest divisor is taken
***********************************************************************/
static unsigned int ns7520_mii_get_clock_divisor(unsigned int unMaxMDIOClk)
{
struct {
unsigned int unSysClkDivisor;
unsigned int unClks; /* field for NS7520_ETH_MCFG_CLKS */
} PHYClockDivisors[] = {
{
4, NS7520_ETH_MCFG_CLKS_4}, {
6, NS7520_ETH_MCFG_CLKS_6}, {
8, NS7520_ETH_MCFG_CLKS_8}, {
10, NS7520_ETH_MCFG_CLKS_10}, {
14, NS7520_ETH_MCFG_CLKS_14}, {
20, NS7520_ETH_MCFG_CLKS_20}, {
28, NS7520_ETH_MCFG_CLKS_28}
};
int nIndexSysClkDiv;
int nArraySize =
sizeof(PHYClockDivisors) / sizeof(PHYClockDivisors[0]);
unsigned int unClks = NS7520_ETH_MCFG_CLKS_28; /* defaults to
greatest div */
DEBUG_FN(DEBUG_INIT);
for (nIndexSysClkDiv = 0; nIndexSysClkDiv < nArraySize;
nIndexSysClkDiv++) {
/* find first sysclock divisor that isn't higher than 2.5 MHz
clock */
if (NETARM_XTAL_FREQ /
PHYClockDivisors[nIndexSysClkDiv].unSysClkDivisor <=
unMaxMDIOClk) {
unClks = PHYClockDivisors[nIndexSysClkDiv].unClks;
break;
}
}
DEBUG_ARGS2(DEBUG_INIT,
"Taking MDIO Clock bit mask 0x%0x for max clock %i\n",
unClks, unMaxMDIOClk);
/* return greatest divisor */
return unClks;
}
/***********************************************************************
* @Function: ns7520_mii_poll_busy
* @Return: 0 if timed out otherwise the remaing timeout
* @Descr: waits until the MII has completed a command or it times out
* code may be interrupted by hard interrupts.
* It is not checked what happens on multiple actions when
* the first is still being busy and we timeout.
***********************************************************************/
static unsigned int ns7520_mii_poll_busy(void)
{
unsigned int unTimeout = 1000;
DEBUG_FN(DEBUG_MII_LOW);
while (((*get_eth_reg_addr(NS7520_ETH_MIND) & NS7520_ETH_MIND_BUSY)
== NS7520_ETH_MIND_BUSY) && unTimeout)
unTimeout--;
return unTimeout;
}
/* ----------------------------------------------------------------------------
* Net+ARM ethernet MII functionality.
*/
#if defined(CONFIG_MII)
/**
* Maximum MII address we support
*/
#define MII_ADDRESS_MAX (31)
/**
* Maximum MII register address we support
*/
#define MII_REGISTER_MAX (31)
/**
* Ethernet MII interface return values for public functions.
*/
enum mii_status {
MII_STATUS_SUCCESS = 0,
MII_STATUS_FAILURE = 1,
};
/**
* Read a 16-bit value from an MII register.
*/
extern int miiphy_read(unsigned char const addr, unsigned char const reg,
unsigned short *const value)
{
int ret = MII_STATUS_FAILURE;
/* Parameter checks */
if (addr > MII_ADDRESS_MAX) {
ERROR(("invalid addr, 0x%02X", addr));
goto miiphy_read_failed_0;
}
if (reg > MII_REGISTER_MAX) {
ERROR(("invalid reg, 0x%02X", reg));
goto miiphy_read_failed_0;
}
if (value == NULL) {
ERROR(("NULL value"));
goto miiphy_read_failed_0;
}
DEBUG_FN(DEBUG_MII_LOW);
/* write MII register to be read */
*get_eth_reg_addr(NS7520_ETH_MADR) = (addr << 8) | reg;
*get_eth_reg_addr(NS7520_ETH_MCMD) = NS7520_ETH_MCMD_READ;
if (!ns7520_mii_poll_busy())
printk(KERN_WARNING NS7520_DRIVER_NAME
": MII still busy in read\n");
/* continue to read */
*get_eth_reg_addr(NS7520_ETH_MCMD) = 0;
*value = (*get_eth_reg_addr(NS7520_ETH_MRDD));
ret = MII_STATUS_SUCCESS;
/* Fall through */
miiphy_read_failed_0:
return (ret);
}
/**
* Write a 16-bit value to an MII register.
*/
extern int miiphy_write(unsigned char const addr, unsigned char const reg,
unsigned short const value)
{
int ret = MII_STATUS_FAILURE;
/* Parameter checks */
if (addr > MII_ADDRESS_MAX) {
ERROR(("invalid addr, 0x%02X", addr));
goto miiphy_write_failed_0;
}
if (reg > MII_REGISTER_MAX) {
ERROR(("invalid reg, 0x%02X", reg));
goto miiphy_write_failed_0;
}
/* write MII register to be written */
*get_eth_reg_addr(NS7520_ETH_MADR) = (addr << 8) | reg;
*get_eth_reg_addr(NS7520_ETH_MWTD) = value;
if (!ns7520_mii_poll_busy()) {
printf(KERN_WARNING NS7520_DRIVER_NAME
": MII still busy in write\n");
}
ret = MII_STATUS_SUCCESS;
/* Fall through */
miiphy_write_failed_0:
return (ret);
}
#endif /* defined(CONFIG_MII) */
#endif /* CONFIG_DRIVER_NS7520_ETHERNET */

22
include/asm-arm/arch-arm720t/netarm_gen_module.h
View file

@ -1,6 +1,9 @@
/*
* include/asm-armnommu/arch-netarm/netarm_gen_module.h
*
* Copyright (C) 2005
* Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
*
* Copyright (C) 2000, 2001 NETsilicon, Inc.
* Copyright (C) 2000, 2001 Red Hat, Inc.
*
@ -27,6 +30,8 @@
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* author(s) : Joe deBlaquiere
*
* Modified to support NS7520 by Art Shipkowski.
*/
#ifndef __NETARM_GEN_MODULE_REGISTERS_H
@ -49,7 +54,9 @@
#define NETARM_GEN_TIMER2_STATUS (0x1c)
#define NETARM_GEN_PORTA (0x20)
#ifndef CONFIG_NETARM_NS7520
#define NETARM_GEN_PORTB (0x24)
#endif
#define NETARM_GEN_PORTC (0x28)
#define NETARM_GEN_INTR_ENABLE (0x30)
@ -128,8 +135,14 @@
/* PORT C Register ( 0xFFB0_0028 ) */
#ifndef CONFIG_NETARM_NS7520
#define NETARM_GEN_PORT_MODE(x) (((x)<<24) + (0xFF00))
#define NETARM_GEN_PORT_DIR(x) (((x)<<16) + (0xFF00))
#else
#define NETARM_GEN_PORT_MODE(x) ((x)<<24)
#define NETARM_GEN_PORT_DIR(x) ((x)<<16)
#define NETARM_GEN_PORT_CSF(x) ((x)<<8)
#endif
/* Timer Registers ( 0xFFB0_0010 0xFFB0_0018 ) */
@ -143,10 +156,15 @@
#define NETARM_GEN_TCTL_INIT_COUNT(x) ((x) & 0x1FF)
#define NETARM_GEN_TSTAT_INTPEN (0x40000000)
#if ~defined(CONFIG_NETARM_NS7520)
#define NETARM_GEN_TSTAT_CTC_MASK (0x000001FF)
#else
#define NETARM_GEN_TSTAT_CTC_MASK (0x0FFFFFFF)
#endif
/* prescale to msecs conversion */
#if !defined(CONFIG_NETARM_PLL_BYPASS)
#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 20480 ) * ( 0x1FF - ( (x) & \
NETARM_GEN_TSTAT_CTC_MASK ) + \
1 ) ) / (NETARM_XTAL_FREQ/1000) )
@ -155,9 +173,7 @@
NETARM_GEN_TSTAT_CTC_MASK ) | \
NETARM_GEN_TCTL_USE_PRESCALE )
#if 0
/* ifdef CONFIG_NETARM_PLL_BYPASS else */
#error test
#else
#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 4096 ) * ( 0x1FF - ( (x) & \
NETARM_GEN_TSTAT_CTC_MASK ) + \
1 ) ) / (NETARM_XTAL_FREQ/1000) )

27
include/asm-arm/arch-arm720t/netarm_mem_module.h
View file

@ -1,6 +1,9 @@
/*
* include/asm-armnommu/arch-netarm/netarm_mem_module.h
*
* Copyright (C) 2005
* Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
*
* Copyright (C) 2000, 2001 NETsilicon, Inc.
* Copyright (C) 2000, 2001 Red Hat, Inc.
*
@ -27,6 +30,8 @@
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* author(s) : Joe deBlaquiere
*
* Modified to support NS7520 by Art Shipkowski.
*/
#ifndef __NETARM_MEM_MODULE_REGISTERS_H
@ -154,4 +159,26 @@
#define NETARM_MEM_OPT_WRITE_ASYNC (0x00000000)
#define NETARM_MEM_OPT_WRITE_SYNC (0x00000001)
#ifdef CONFIG_NETARM_NS7520
/* The NS7520 has a second options register for each chip select */
#define NETARM_MEM_CS0_OPTIONS_B (0x18)
#define NETARM_MEM_CS1_OPTIONS_B (0x28)
#define NETARM_MEM_CS2_OPTIONS_B (0x38)
#define NETARM_MEM_CS3_OPTIONS_B (0x48)
#define NETARM_MEM_CS4_OPTIONS_B (0x58)
/* Option B Registers (0xFFC0_00x8) */
#define NETARM_MEM_OPTB_SYNC_1_STAGE (0x00000001)
#define NETARM_MEM_OPTB_SYNC_2_STAGE (0x00000002)
#define NETARM_MEM_OPTB_BCYC_PLUS0 (0x00000000)
#define NETARM_MEM_OPTB_BCYC_PLUS4 (0x00000004)
#define NETARM_MEM_OPTB_BCYC_PLUS8 (0x00000008)
#define NETARM_MEM_OPTB_BCYC_PLUS12 (0x0000000C)
#define NETARM_MEM_OPTB_WAIT_PLUS0 (0x00000000)
#define NETARM_MEM_OPTB_WAIT_PLUS16 (0x00000010)
#define NETARM_MEM_OPTB_WAIT_PLUS32 (0x00000020)
#define NETARM_MEM_OPTB_WAIT_PLUS48 (0x00000030)
#endif
#endif

19
include/asm-arm/arch-arm720t/netarm_registers.h
View file

@ -1,6 +1,9 @@
/*
* linux/include/asm-arm/arch-netarm/netarm_registers.h
*
* Copyright (C) 2005
* Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
*
* Copyright (C) 2000, 2001 NETsilicon, Inc.
* Copyright (C) 2000, 2001 WireSpeed Communications Corporation
*
@ -27,6 +30,8 @@
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* author(s) : Joe deBlaquiere
*
* Modified to support NS7520 by Art Shipkowski.
*/
#ifndef __NET_ARM_REGISTERS_H
@ -38,6 +43,8 @@
/* the input crystal/clock frequency ( in Hz ) */
#define NETARM_XTAL_FREQ_25MHz (18432000)
#define NETARM_XTAL_FREQ_33MHz (23698000)
#define NETARM_XTAL_FREQ_48MHz (48000000)
#define NETARM_XTAL_FREQ_55MHz (55000000)
#define NETARM_XTAL_FREQ_EMLIN1 (20000000)
/* the frequency of SYS_CLK */
@ -60,12 +67,22 @@
#define NETARM_PLL_COUNT_VAL 4
#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz
#else /* CONFIG_NETARM_NET50 */
#elif defined(CONFIG_NETARM_NET50)
/* NET+50 boards: 40 MHz (with NETARM_XTAL_FREQ_25MHz) */
#define NETARM_PLL_COUNT_VAL 8
#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz
#else /* CONFIG_NETARM_NS7520 */
#define NETARM_PLL_COUNT_VAL 0
#if defined(CONFIG_BOARD_UNC20)
#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_48MHz
#else
#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_55MHz
#endif
#endif
/* #include "arm_registers.h" */

5
include/configs/AP1000.h
View file

@ -66,8 +66,6 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & \
(~CFG_CMD_RTC) & ~(CFG_CMD_I2C)) | \
CFG_CMD_IRQ | \
@ -136,8 +134,6 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
@ -206,7 +202,6 @@
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
/* Configuration Port location */
#define CONFIG_PORT_ADDR 0xF0000500

335
include/ns7520_eth.h Normal file
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@ -0,0 +1,335 @@
/***********************************************************************
*
* Copyright 2003 by FS Forth-Systeme GmbH.
* All rights reserved.
*
* $Id$
* @Author: Markus Pietrek
* @Descr: Defines the NS7520 ethernet registers.
* Stick with the old ETH prefix names instead going to the
* new EFE names in the manual.
* NS7520_ETH_* refer to NS7520 Hardware
* Reference/January 2003 [1]
* PHY_LXT971_* refer to Intel LXT971 Datasheet
* #249414 Rev. 02 [2]
* Partly derived from netarm_eth_module.h
*
* Modified by Arthur Shipkowski <art@videon-central.com> from the
* Linux version to be properly formatted for U-Boot (i.e. no C++ comments)
*
***********************************************************************/
#ifndef FS_NS7520_ETH_H
#define FS_NS7520_ETH_H
#ifdef CONFIG_DRIVER_NS7520_ETHERNET
#include "lxt971a.h"
/* The port addresses */
#define NS7520_ETH_MODULE_BASE (0xFF800000)
#define get_eth_reg_addr(c) \
((volatile unsigned int*) ( NS7520_ETH_MODULE_BASE+(unsigned int) (c)))
#define NS7520_ETH_EGCR (0x0000) /* Ethernet Gen Control */
#define NS7520_ETH_EGSR (0x0004) /* Ethernet Gen Status */
#define NS7520_ETH_FIFO (0x0008) /* FIFO Data */
#define NS7520_ETH_FIFOL (0x000C) /* FIFO Data Last */
#define NS7520_ETH_ETSR (0x0010) /* Ethernet Transmit Status */
#define NS7520_ETH_ERSR (0x0014) /* Ethernet Receive Status */
#define NS7520_ETH_MAC1 (0x0400) /* MAC Config 1 */
#define NS7520_ETH_MAC2 (0x0404) /* MAC Config 2 */
#define NS7520_ETH_IPGT (0x0408) /* Back2Back InterPacket Gap */
#define NS7520_ETH_IPGR (0x040C) /* non back2back InterPacket Gap */
#define NS7520_ETH_CLRT (0x0410) /* Collision Window/Retry */
#define NS7520_ETH_MAXF (0x0414) /* Maximum Frame Register */
#define NS7520_ETH_SUPP (0x0418) /* PHY Support */
#define NS7520_ETH_TEST (0x041C) /* Test Register */
#define NS7520_ETH_MCFG (0x0420) /* MII Management Configuration */
#define NS7520_ETH_MCMD (0x0424) /* MII Management Command */
#define NS7520_ETH_MADR (0x0428) /* MII Management Address */
#define NS7520_ETH_MWTD (0x042C) /* MII Management Write Data */
#define NS7520_ETH_MRDD (0x0430) /* MII Management Read Data */
#define NS7520_ETH_MIND (0x0434) /* MII Management Indicators */
#define NS7520_ETH_SMII (0x0438) /* SMII Status Register */
#define NS7520_ETH_SA1 (0x0440) /* Station Address 1 */
#define NS7520_ETH_SA2 (0x0444) /* Station Address 2 */
#define NS7520_ETH_SA3 (0x0448) /* Station Address 3 */
#define NS7520_ETH_SAFR (0x05C0) /* Station Address Filter */
#define NS7520_ETH_HT1 (0x05D0) /* Hash Table 1 */
#define NS7520_ETH_HT2 (0x05D4) /* Hash Table 2 */
#define NS7520_ETH_HT3 (0x05D8) /* Hash Table 3 */
#define NS7520_ETH_HT4 (0x05DC) /* Hash Table 4 */
/* EGCR Ethernet General Control Register Bit Fields*/
#define NS7520_ETH_EGCR_ERX (0x80000000) /* Enable Receive FIFO */
#define NS7520_ETH_EGCR_ERXDMA (0x40000000) /* Enable Receive DMA */
#define NS7520_ETH_EGCR_ERXLNG (0x20000000) /* Accept Long packets */
#define NS7520_ETH_EGCR_ERXSHT (0x10000000) /* Accept Short packets */
#define NS7520_ETH_EGCR_ERXREG (0x08000000) /* Enable Receive Data Interrupt */
#define NS7520_ETH_EGCR_ERFIFOH (0x04000000) /* Enable Receive Half-Full Int */
#define NS7520_ETH_EGCR_ERXBR (0x02000000) /* Enable Receive buffer ready */
#define NS7520_ETH_EGCR_ERXBAD (0x01000000) /* Accept bad receive packets */
#define NS7520_ETH_EGCR_ETX (0x00800000) /* Enable Transmit FIFO */
#define NS7520_ETH_EGCR_ETXDMA (0x00400000) /* Enable Transmit DMA */
#define NS7520_ETH_EGCR_ETXWM_R (0x00300000) /* Enable Transmit FIFO mark Reserv */
#define NS7520_ETH_EGCR_ETXWM_75 (0x00200000) /* Enable Transmit FIFO mark 75% */
#define NS7520_ETH_EGCR_ETXWM_50 (0x00100000) /* Enable Transmit FIFO mark 50% */
#define NS7520_ETH_EGCR_ETXWM_25 (0x00000000) /* Enable Transmit FIFO mark 25% */
#define NS7520_ETH_EGCR_ETXREG (0x00080000) /* Enable Transmit Data Read Int */
#define NS7520_ETH_EGCR_ETFIFOH (0x00040000) /* Enable Transmit Fifo Half Int */
#define NS7520_ETH_EGCR_ETXBC (0x00020000) /* Enable Transmit Buffer Compl Int */
#define NS7520_ETH_EGCR_EFULLD (0x00010000) /* Enable Full Duplex Operation */
#define NS7520_ETH_EGCR_MODE_MA (0x0000C000) /* Mask */
#define NS7520_ETH_EGCR_MODE_SEE (0x0000C000) /* 10 Mbps SEEQ ENDEC PHY */
#define NS7520_ETH_EGCR_MODE_LEV (0x00008000) /* 10 Mbps Level1 ENDEC PHY */
#define NS7520_ETH_EGCR_RES1 (0x00002000) /* Reserved */
#define NS7520_ETH_EGCR_RXCINV (0x00001000) /* Invert the receive clock input */
#define NS7520_ETH_EGCR_TXCINV (0x00000800) /* Invert the transmit clock input */
#define NS7520_ETH_EGCR_PNA (0x00000400) /* pSOS pNA buffer */
#define NS7520_ETH_EGCR_MAC_RES (0x00000200) /* MAC Software reset */
#define NS7520_ETH_EGCR_ITXA (0x00000100) /* Insert Transmit Source Address */
#define NS7520_ETH_EGCR_ENDEC_MA (0x000000FC) /* ENDEC media control bits */
#define NS7520_ETH_EGCR_EXINT_MA (0x00000003) /* Mask */
#define NS7520_ETH_EGCR_EXINT_RE (0x00000003) /* Reserved */
#define NS7520_ETH_EGCR_EXINT_TP (0x00000002) /* TP-PMD Mode */
#define NS7520_ETH_EGCR_EXINT_10 (0x00000001) /* 10-MBit Mode */
#define NS7520_ETH_EGCR_EXINT_NO (0x00000000) /* MII normal operation */
/* EGSR Ethernet General Status Register Bit Fields*/
#define NS7520_ETH_EGSR_RES1 (0xC0000000) /* Reserved */
#define NS7520_ETH_EGSR_RXFDB_MA (0x30000000) /* Receive FIFO mask */
#define NS7520_ETH_EGSR_RXFDB_3 (0x30000000) /* Receive FIFO 3 bytes available */
#define NS7520_ETH_EGSR_RXFDB_2 (0x20000000) /* Receive FIFO 2 bytes available */
#define NS7520_ETH_EGCR_RXFDB_1 (0x10000000) /* Receive FIFO 1 Bytes available */
#define NS7520_ETH_EGCR_RXFDB_4 (0x00000000) /* Receive FIFO 4 Bytes available */
#define NS7520_ETH_EGSR_RXREGR (0x08000000) /* Receive Register Ready */
#define NS7520_ETH_EGSR_RXFIFOH (0x04000000) /* Receive FIFO Half Full */
#define NS7520_ETH_EGSR_RXBR (0x02000000) /* Receive Buffer Ready */
#define NS7520_ETH_EGSR_RXSKIP (0x01000000) /* Receive Buffer Skip */
#define NS7520_ETH_EGSR_RES2 (0x00F00000) /* Reserved */
#define NS7520_ETH_EGSR_TXREGE (0x00080000) /* Transmit Register Empty */
#define NS7520_ETH_EGSR_TXFIFOH (0x00040000) /* Transmit FIFO half empty */
#define NS7520_ETH_EGSR_TXBC (0x00020000) /* Transmit buffer complete */
#define NS7520_ETH_EGSR_TXFIFOE (0x00010000) /* Transmit FIFO empty */
#define NS7520_ETH_EGSR_RXPINS (0x0000FC00) /* ENDEC Phy Status */
#define NS7520_ETH_EGSR_RES3 (0x000003FF) /* Reserved */
/* ETSR Ethernet Transmit Status Register Bit Fields*/
#define NS7520_ETH_ETSR_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_ETSR_TXOK (0x00008000) /* Packet transmitted OK */
#define NS7520_ETH_ETSR_TXBR (0x00004000) /* Broadcast packet transmitted */
#define NS7520_ETH_ETSR_TXMC (0x00002000) /* Multicast packet transmitted */
#define NS7520_ETH_ETSR_TXAL (0x00001000) /* Transmit abort - late collision */
#define NS7520_ETH_ETSR_TXAED (0x00000800) /* Transmit abort - deferral */
#define NS7520_ETH_ETSR_TXAEC (0x00000400) /* Transmit abort - exc collisions */
#define NS7520_ETH_ETSR_TXAUR (0x00000200) /* Transmit abort - underrun */
#define NS7520_ETH_ETSR_TXAJ (0x00000100) /* Transmit abort - jumbo */
#define NS7520_ETH_ETSR_RES2 (0x00000080) /* Reserved */
#define NS7520_ETH_ETSR_TXDEF (0x00000040) /* Transmit Packet Deferred */
#define NS7520_ETH_ETSR_TXCRC (0x00000020) /* Transmit CRC error */
#define NS7520_ETH_ETSR_RES3 (0x00000010) /* Reserved */
#define NS7520_ETH_ETSR_TXCOLC (0x0000000F) /* Transmit Collision Count */
/* ERSR Ethernet Receive Status Register Bit Fields*/
#define NS7520_ETH_ERSR_RXSIZE (0xFFFF0000) /* Receive Buffer Size */
#define NS7520_ETH_ERSR_RXCE (0x00008000) /* Receive Carrier Event */
#define NS7520_ETH_ERSR_RXDV (0x00004000) /* Receive Data Violation Event */
#define NS7520_ETH_ERSR_RXOK (0x00002000) /* Receive Packet OK */
#define NS7520_ETH_ERSR_RXBR (0x00001000) /* Receive Broadcast Packet */
#define NS7520_ETH_ERSR_RXMC (0x00000800) /* Receive Multicast Packet */
#define NS7520_ETH_ERSR_RXCRC (0x00000400) /* Receive Packet has CRC error */
#define NS7520_ETH_ERSR_RXDR (0x00000200) /* Receive Packet has dribble error */
#define NS7520_ETH_ERSR_RXCV (0x00000100) /* Receive Packet code violation */
#define NS7520_ETH_ERSR_RXLNG (0x00000080) /* Receive Packet too long */
#define NS7520_ETH_ERSR_RXSHT (0x00000040) /* Receive Packet too short */
#define NS7520_ETH_ERSR_ROVER (0x00000020) /* Recive overflow */
#define NS7520_ETH_ERSR_RES (0x0000001F) /* Reserved */
/* MAC1 MAC Configuration Register 1 Bit Fields*/
#define NS7520_ETH_MAC1_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_MAC1_SRST (0x00008000) /* Soft Reset */
#define NS7520_ETH_MAC1_SIMMRST (0x00004000) /* Simulation Reset */
#define NS7520_ETH_MAC1_RES2 (0x00003000) /* Reserved */
#define NS7520_ETH_MAC1_RPEMCSR (0x00000800) /* Reset PEMCS/RX */
#define NS7520_ETH_MAC1_RPERFUN (0x00000400) /* Reset PERFUN */
#define NS7520_ETH_MAC1_RPEMCST (0x00000200) /* Reset PEMCS/TX */
#define NS7520_ETH_MAC1_RPETFUN (0x00000100) /* Reset PETFUN */
#define NS7520_ETH_MAC1_RES3 (0x000000E0) /* Reserved */
#define NS7520_ETH_MAC1_LOOPBK (0x00000010) /* Internal Loopback */
#define NS7520_ETH_MAC1_TXFLOW (0x00000008) /* TX flow control */
#define NS7520_ETH_MAC1_RXFLOW (0x00000004) /* RX flow control */
#define NS7520_ETH_MAC1_PALLRX (0x00000002) /* Pass ALL receive frames */
#define NS7520_ETH_MAC1_RXEN (0x00000001) /* Receive enable */
/* MAC Configuration Register 2 Bit Fields*/
#define NS7520_ETH_MAC2_RES1 (0xFFFF8000) /* Reserved */
#define NS7520_ETH_MAC2_EDEFER (0x00004000) /* Excess Deferral */
#define NS7520_ETH_MAC2_BACKP (0x00002000) /* Backpressure/NO back off */
#define NS7520_ETH_MAC2_NOBO (0x00001000) /* No back off */
#define NS7520_ETH_MAC2_RES2 (0x00000C00) /* Reserved */
#define NS7520_ETH_MAC2_LONGP (0x00000200) /* Long Preable enforcement */
#define NS7520_ETH_MAC2_PUREP (0x00000100) /* Pure preamble enforcement */
#define NS7520_ETH_MAC2_AUTOP (0x00000080) /* Auto detect PAD enable */
#define NS7520_ETH_MAC2_VLANP (0x00000040) /* VLAN pad enable */
#define NS7520_ETH_MAC2_PADEN (0x00000020) /* PAD/CRC enable */
#define NS7520_ETH_MAC2_CRCEN (0x00000010) /* CRC enable */
#define NS7520_ETH_MAC2_DELCRC (0x00000008) /* Delayed CRC */
#define NS7520_ETH_MAC2_HUGE (0x00000004) /* Huge frame enable */
#define NS7520_ETH_MAC2_FLENC (0x00000002) /* Frame length checking */
#define NS7520_ETH_MAC2_FULLD (0x00000001) /* Full duplex */
/* IPGT Back-to-Back Inter-Packet-Gap Register Bit Fields*/
#define NS7520_ETH_IPGT_RES (0xFFFFFF80) /* Reserved */
#define NS7520_ETH_IPGT_IPGT (0x0000007F) /* Back-to-Back Interpacket Gap */
/* IPGR Non Back-to-Back Inter-Packet-Gap Register Bit Fields*/
#define NS7520_ETH_IPGR_RES1 (0xFFFF8000) /* Reserved */
#define NS7520_ETH_IPGR_IPGR1 (0x00007F00) /* Non Back-to-back Interpacket Gap */
#define NS7520_ETH_IPGR_RES2 (0x00000080) /* Reserved */
#define NS7520_ETH_IPGR_IPGR2 (0x0000007F) /* Non back-to-back Interpacket Gap */
/* CLRT Collision Windows/Collision Retry Register Bit Fields*/
#define NS7520_ETH_CLRT_RES1 (0xFFFFC000) /* Reserved */
#define NS7520_ETH_CLRT_CWIN (0x00003F00) /* Collision Windows */
#define NS7520_ETH_CLRT_RES2 (0x000000F0) /* Reserved */
#define NS7520_ETH_CLRT_RETX (0x0000000F) /* Retransmission maximum */
/* MAXF Maximum Frame Register Bit Fields*/
#define NS7520_ETH_MAXF_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_MAXF_MAXF (0x0000FFFF) /* Maximum frame length */
/* SUPP PHY Support Register Bit Fields*/
#define NS7520_ETH_SUPP_RES1 (0xFFFFFF00) /* Reserved */
#define NS7520_ETH_SUPP_RPE100X (0x00000080) /* Reset PE100X module */
#define NS7520_ETH_SUPP_FORCEQ (0x00000040) /* Force Quit */
#define NS7520_ETH_SUPP_NOCIPH (0x00000020) /* No Cipher */
#define NS7520_ETH_SUPP_DLINKF (0x00000010) /* Disable link fail */
#define NS7520_ETH_SUPP_RPE10T (0x00000008) /* Reset PE10T module */
#define NS7520_ETH_SUPP_RES2 (0x00000004) /* Reserved */
#define NS7520_ETH_SUPP_JABBER (0x00000002) /* Enable Jabber protection */
#define NS7520_ETH_SUPP_BITMODE (0x00000001) /* Bit Mode */
/* TEST Register Bit Fields*/
#define NS7520_ETH_TEST_RES1 (0xFFFFFFF8) /* Reserved */
#define NS7520_ETH_TEST_TBACK (0x00000004) /* Test backpressure */
#define NS7520_ETH_TEST_TPAUSE (0x00000002) /* Test Pause */
#define NS7520_ETH_TEST_SPQ (0x00000001) /* Shortcut pause quanta */
/* MCFG MII Management Configuration Register Bit Fields*/
#define NS7520_ETH_MCFG_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_MCFG_RMIIM (0x00008000) /* Reset MII management */
#define NS7520_ETH_MCFG_RES2 (0x00007FE0) /* Reserved */
#define NS7520_ETH_MCFG_CLKS_MA (0x0000001C) /* Clock Select */
#define NS7520_ETH_MCFG_CLKS_4 (0x00000004) /* Sysclk / 4 */
#define NS7520_ETH_MCFG_CLKS_6 (0x00000008) /* Sysclk / 6 */
#define NS7520_ETH_MCFG_CLKS_8 (0x0000000C) /* Sysclk / 8 */
#define NS7520_ETH_MCFG_CLKS_10 (0x00000010) /* Sysclk / 10 */
#define NS7520_ETH_MCFG_CLKS_14 (0x00000014) /* Sysclk / 14 */
#define NS7520_ETH_MCFG_CLKS_20 (0x00000018) /* Sysclk / 20 */
#define NS7520_ETH_MCFG_CLKS_28 (0x0000001C) /* Sysclk / 28 */
#define NS7520_ETH_MCFG_SPRE (0x00000002) /* Suppress preamble */
#define NS7520_ETH_MCFG_SCANI (0x00000001) /* Scan increment */
/* MCMD MII Management Command Register Bit Fields*/
#define NS7520_ETH_MCMD_RES1 (0xFFFFFFFC) /* Reserved */
#define NS7520_ETH_MCMD_SCAN (0x00000002) /* Automatically Scan for Read Data */
#define NS7520_ETH_MCMD_READ (0x00000001) /* Single scan for Read Data */
/* MCMD MII Management Address Register Bit Fields*/
#define NS7520_ETH_MADR_RES1 (0xFFFFE000) /* Reserved */
#define NS7520_ETH_MADR_DADR (0x00001F00) /* MII PHY device address */
#define NS7520_ETH_MADR_RES2 (0x000000E0) /* Reserved */
#define NS7520_ETH_MADR_RADR (0x0000001F) /* MII PHY register address */
/* MWTD MII Management Write Data Register Bit Fields*/
#define NS7520_ETH_MWTD_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_MWTD_MWTD (0x0000FFFF) /* MII Write Data */
/* MRRD MII Management Read Data Register Bit Fields*/
#define NS7520_ETH_MRRD_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_MRRD_MRDD (0x0000FFFF) /* MII Read Data */
/* MIND MII Management Indicators Register Bit Fields*/
#define NS7520_ETH_MIND_RES1 (0xFFFFFFF8) /* Reserved */
#define NS7520_ETH_MIND_NVALID (0x00000004) /* Read Data not valid */
#define NS7520_ETH_MIND_SCAN (0x00000002) /* Automatically scan for read data */
#define NS7520_ETH_MIND_BUSY (0x00000001) /* MII interface busy */
/* SMII Status Register Bit Fields*/
#define NS7520_ETH_SMII_RES1 (0xFFFFFFE0) /* Reserved */
#define NS7520_ETH_SMII_CLASH (0x00000010) /* MAC-to-MAC with PHY */
#define NS7520_ETH_SMII_JABBER (0x00000008) /* Jabber condition present */
#define NS7520_ETH_SMII_LINK (0x00000004) /* Link OK */
#define NS7520_ETH_SMII_DUPLEX (0x00000002) /* Full-duplex operation */
#define NS7520_ETH_SMII_SPEED (0x00000001) /* 100 Mbps */
/* SA1 Station Address 1 Register Bit Fields*/
#define NS7520_ETH_SA1_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_SA1_OCTET1 (0x0000FF00) /* Station Address octet 1 */
#define NS7520_ETH_SA1_OCTET2 (0x000000FF) /* Station Address octet 2 */
/* SA2 Station Address 2 Register Bit Fields*/
#define NS7520_ETH_SA2_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_SA2_OCTET3 (0x0000FF00) /* Station Address octet 3 */
#define NS7520_ETH_SA2_OCTET4 (0x000000FF) /* Station Address octet 4 */
/* SA3 Station Address 3 Register Bit Fields*/
#define NS7520_ETH_SA3_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_SA3_OCTET5 (0x0000FF00) /* Station Address octet 5 */
#define NS7520_ETH_SA3_OCTET6 (0x000000FF) /* Station Address octet 6 */
/* SAFR Station Address Filter Register Bit Fields*/
#define NS7520_ETH_SAFR_RES1 (0xFFFFFFF0) /* Reserved */
#define NS7520_ETH_SAFR_PRO (0x00000008) /* Enable Promiscuous mode */
#define NS7520_ETH_SAFR_PRM (0x00000004) /* Accept ALL multicast packets */
#define NS7520_ETH_SAFR_PRA (0x00000002) /* Accept multicast packets table */
#define NS7520_ETH_SAFR_BROAD (0x00000001) /* Accept ALL Broadcast packets */
/* HT1 Hash Table 1 Register Bit Fields*/
#define NS7520_ETH_HT1_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_HT1_HT1 (0x0000FFFF) /* CRC value 15-0 */
/* HT2 Hash Table 2 Register Bit Fields*/
#define NS7520_ETH_HT2_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_HT2_HT2 (0x0000FFFF) /* CRC value 31-16 */
/* HT3 Hash Table 3 Register Bit Fields*/
#define NS7520_ETH_HT3_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_HT3_HT3 (0x0000FFFF) /* CRC value 47-32 */
/* HT4 Hash Table 4 Register Bit Fields*/
#define NS7520_ETH_HT4_RES1 (0xFFFF0000) /* Reserved */
#define NS7520_ETH_HT4_HT4 (0x0000FFFF) /* CRC value 63-48 */
#endif /* CONFIG_DRIVER_NS7520_ETHERNET */
#endif /* FS_NS7520_ETH_H */