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mv_i2c: use structure to replace the direclty define
Add i2c_clk_enable in the cpu specific code, since previous platform it, while new platform don't need. In the pantheon and armada100 platform, this function is defined as NULL one. Acked-by: Heiko Schocher <hs@denx.de> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Lei Wen <leiwen@marvell.com>
This commit is contained in:
Lei Wen
Albert ARIBAUD
parent
879de1275a
commit
3df619ec2c
7 changed files with 164 additions and 137 deletions
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@ -318,3 +318,13 @@ int arch_cpu_init(void)
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pxa_clock_setup();
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return 0;
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}
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void i2c_clk_enable(void)
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{
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/* set the global I2C clock on */
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#ifdef CONFIG_CPU_MONAHANS
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writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
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#else
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writel(readl(CKEN) | CKEN14_I2C, CKEN);
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#endif
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}
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@ -455,62 +455,6 @@ typedef void (*ExcpHndlr) (void) ;
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IrSR_RCVEIR_UART_MODE | \
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IrSR_XMITIR_IR_MODE)
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/*
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* I2C registers
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*/
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#define IBMR 0x40301680 /* I2C Bus Monitor Register - IBMR */
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#define IDBR 0x40301688 /* I2C Data Buffer Register - IDBR */
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#define ICR 0x40301690 /* I2C Control Register - ICR */
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#define ISR 0x40301698 /* I2C Status Register - ISR */
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#define ISAR 0x403016A0 /* I2C Slave Address Register - ISAR */
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#ifdef CONFIG_CPU_MONAHANS
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#define PWRIBMR 0x40f500C0 /* Power I2C Bus Monitor Register-IBMR */
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#define PWRIDBR 0x40f500C4 /* Power I2C Data Buffer Register-IDBR */
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#define PWRICR 0x40f500C8 /* Power I2C Control Register - ICR */
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#define PWRISR 0x40f500CC /* Power I2C Status Register - ISR */
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#define PWRISAR 0x40f500D0 /* Power I2C Slave Address Register-ISAR */
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#else
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#define PWRIBMR 0x40f00180 /* Power I2C Bus Monitor Register-IBMR */
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#define PWRIDBR 0x40f00188 /* Power I2C Data Buffer Register-IDBR */
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#define PWRICR 0x40f00190 /* Power I2C Control Register - ICR */
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#define PWRISR 0x40f00198 /* Power I2C Status Register - ISR */
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#define PWRISAR 0x40f001A0 /* Power I2C Slave Address Register-ISAR */
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#endif
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/* ----- Control register bits ---------------------------------------- */
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#define ICR_START 0x1 /* start bit */
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#define ICR_STOP 0x2 /* stop bit */
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#define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */
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#define ICR_TB 0x8 /* transfer byte bit */
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#define ICR_MA 0x10 /* master abort */
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#define ICR_SCLE 0x20 /* master clock enable, mona SCLEA */
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#define ICR_IUE 0x40 /* unit enable */
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#define ICR_GCD 0x80 /* general call disable */
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#define ICR_ITEIE 0x100 /* enable tx interrupts */
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#define ICR_IRFIE 0x200 /* enable rx interrupts, mona: DRFIE */
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#define ICR_BEIE 0x400 /* enable bus error ints */
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#define ICR_SSDIE 0x800 /* slave STOP detected int enable */
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#define ICR_ALDIE 0x1000 /* enable arbitration interrupt */
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#define ICR_SADIE 0x2000 /* slave address detected int enable */
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#define ICR_UR 0x4000 /* unit reset */
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#define ICR_FM 0x8000 /* Fast Mode */
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/* ----- Status register bits ----------------------------------------- */
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#define ISR_RWM 0x1 /* read/write mode */
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#define ISR_ACKNAK 0x2 /* ack/nak status */
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#define ISR_UB 0x4 /* unit busy */
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#define ISR_IBB 0x8 /* bus busy */
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#define ISR_SSD 0x10 /* slave stop detected */
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#define ISR_ALD 0x20 /* arbitration loss detected */
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#define ISR_ITE 0x40 /* tx buffer empty */
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#define ISR_IRF 0x80 /* rx buffer full */
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#define ISR_GCAD 0x100 /* general call address detected */
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#define ISR_SAD 0x200 /* slave address detected */
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#define ISR_BED 0x400 /* bus error no ACK/NAK */
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/*
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* Serial Audio Controller
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*/
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@ -45,12 +45,7 @@ DECLARE_GLOBAL_DATA_PTR;
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*/
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int i2c_init_board(void)
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{
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int i, icr;
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/* disable I2C controller first, otherwhise it thinks we want to */
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/* talk to the slave port... */
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icr = readl(ICR);
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writel(readl(ICR) & ~(ICR_SCLE | ICR_IUE), ICR);
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int i;
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/* set gpio pin low _before_ we change direction to output */
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writel(GPIO_bit(70), GPCR(70));
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@ -63,8 +58,6 @@ int i2c_init_board(void)
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udelay(10);
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}
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writel(icr, ICR);
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return 0;
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}
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@ -8,6 +8,9 @@
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* (C) Copyright 2003 Pengutronix e.K.
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* Robert Schwebel <r.schwebel@pengutronix.de>
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*
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* (C) Copyright 2011 Marvell Inc.
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* Lei Wen <leiwen@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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@ -34,24 +37,8 @@
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#include <asm/io.h>
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#ifdef CONFIG_HARD_I2C
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/*
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* - CONFIG_SYS_I2C_SPEED
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* - I2C_PXA_SLAVE_ADDR
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*/
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#include <asm/arch/hardware.h>
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#include <asm/arch/pxa-regs.h>
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#include <i2c.h>
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#if (CONFIG_SYS_I2C_SPEED == 400000)
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#define I2C_ICR_INIT (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD \
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| ICR_SCLE)
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#else
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#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
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#endif
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#define I2C_ISR_INIT 0x7FF
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#include "mv_i2c.h"
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#ifdef DEBUG_I2C
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#define PRINTD(x) printf x
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@ -59,20 +46,6 @@
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#define PRINTD(x)
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#endif
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/* Shall the current transfer have a start/stop condition? */
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#define I2C_COND_NORMAL 0
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#define I2C_COND_START 1
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#define I2C_COND_STOP 2
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/* Shall the current transfer be ack/nacked or being waited for it? */
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#define I2C_ACKNAK_WAITACK 1
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#define I2C_ACKNAK_SENDACK 2
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#define I2C_ACKNAK_SENDNAK 4
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/* Specify who shall transfer the data (master or slave) */
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#define I2C_READ 0
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#define I2C_WRITE 1
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/* All transfers are described by this data structure */
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struct i2c_msg {
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u8 condition;
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@ -81,27 +54,37 @@ struct i2c_msg {
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u8 data;
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};
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struct mv_i2c {
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u32 ibmr;
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u32 pad0;
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u32 idbr;
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u32 pad1;
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u32 icr;
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u32 pad2;
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u32 isr;
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u32 pad3;
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u32 isar;
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};
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static struct mv_i2c *base = (struct mv_i2c *)CONFIG_MV_I2C_REG;
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/*
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* i2c_pxa_reset: - reset the host controller
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* i2c_reset: - reset the host controller
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*
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*/
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static void i2c_reset(void)
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{
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writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */
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writel(readl(ICR) | ICR_UR, ICR); /* reset the unit */
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writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
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writel(readl(&base->icr) | ICR_UR, &base->icr); /* reset the unit */
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udelay(100);
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writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */
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#ifdef CONFIG_CPU_MONAHANS
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/* | CKENB_1_PWM1 | CKENB_0_PWM0); */
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writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
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#else /* CONFIG_CPU_MONAHANS */
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/* set the global I2C clock on */
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writel(readl(CKEN) | CKEN14_I2C, CKEN);
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#endif
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writel(I2C_PXA_SLAVE_ADDR, ISAR); /* set our slave address */
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writel(I2C_ICR_INIT, ICR); /* set control reg values */
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writel(I2C_ISR_INIT, ISR); /* set clear interrupt bits */
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writel(readl(ICR) | ICR_IUE, ICR); /* enable unit */
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writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
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i2c_clk_enable();
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writel(CONFIG_SYS_I2C_SLAVE, &base->isar); /* set our slave address */
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writel(I2C_ICR_INIT, &base->icr); /* set control reg values */
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writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */
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writel(readl(&base->icr) | ICR_IUE, &base->icr); /* enable unit */
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udelay(100);
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}
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@ -114,13 +97,15 @@ static void i2c_reset(void)
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static int i2c_isr_set_cleared(unsigned long set_mask,
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unsigned long cleared_mask)
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{
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int timeout = 1000;
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int timeout = 1000, isr;
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while (((ISR & set_mask) != set_mask) || ((ISR & cleared_mask) != 0)) {
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do {
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isr = readl(&base->isr);
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udelay(10);
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if (timeout-- < 0)
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return 0;
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}
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} while (((isr & set_mask) != set_mask)
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|| ((isr & cleared_mask) != 0));
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return 1;
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}
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@ -153,26 +138,26 @@ int i2c_transfer(struct i2c_msg *msg)
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goto transfer_error_bus_busy;
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/* start transmission */
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writel(readl(ICR) & ~ICR_START, ICR);
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writel(readl(ICR) & ~ICR_STOP, ICR);
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writel(msg->data, IDBR);
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writel(readl(&base->icr) & ~ICR_START, &base->icr);
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writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
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writel(msg->data, &base->idbr);
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if (msg->condition == I2C_COND_START)
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writel(readl(ICR) | ICR_START, ICR);
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writel(readl(&base->icr) | ICR_START, &base->icr);
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if (msg->condition == I2C_COND_STOP)
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writel(readl(ICR) | ICR_STOP, ICR);
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writel(readl(&base->icr) | ICR_STOP, &base->icr);
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if (msg->acknack == I2C_ACKNAK_SENDNAK)
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writel(readl(ICR) | ICR_ACKNAK, ICR);
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writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
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if (msg->acknack == I2C_ACKNAK_SENDACK)
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writel(readl(ICR) & ~ICR_ACKNAK, ICR);
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writel(readl(ICR) & ~ICR_ALDIE, ICR);
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writel(readl(ICR) | ICR_TB, ICR);
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writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
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writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
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writel(readl(&base->icr) | ICR_TB, &base->icr);
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/* transmit register empty? */
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if (!i2c_isr_set_cleared(ISR_ITE, 0))
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goto transfer_error_transmit_timeout;
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/* clear 'transmit empty' state */
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writel(readl(ISR) | ISR_ITE, ISR);
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writel(readl(&base->isr) | ISR_ITE, &base->isr);
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/* wait for ACK from slave */
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if (msg->acknack == I2C_ACKNAK_WAITACK)
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@ -187,28 +172,27 @@ int i2c_transfer(struct i2c_msg *msg)
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goto transfer_error_bus_busy;
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/* start receive */
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writel(readl(ICR) & ~ICR_START, ICR);
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writel(readl(ICR) & ~ICR_STOP, ICR);
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writel(readl(&base->icr) & ~ICR_START, &base->icr);
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writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
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if (msg->condition == I2C_COND_START)
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writel(readl(ICR) | ICR_START, ICR);
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writel(readl(&base->icr) | ICR_START, &base->icr);
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if (msg->condition == I2C_COND_STOP)
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writel(readl(ICR) | ICR_STOP, ICR);
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writel(readl(&base->icr) | ICR_STOP, &base->icr);
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if (msg->acknack == I2C_ACKNAK_SENDNAK)
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writel(readl(ICR) | ICR_ACKNAK, ICR);
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writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
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if (msg->acknack == I2C_ACKNAK_SENDACK)
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writel(readl(ICR) & ~ICR_ACKNAK, ICR);
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writel(readl(ICR) & ~ICR_ALDIE, ICR);
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writel(readl(ICR) | ICR_TB, ICR);
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writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
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writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
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writel(readl(&base->icr) | ICR_TB, &base->icr);
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/* receive register full? */
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if (!i2c_isr_set_cleared(ISR_IRF, 0))
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goto transfer_error_receive_timeout;
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msg->data = readl(IDBR);
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msg->data = readl(&base->idbr);
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/* clear 'receive empty' state */
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writel(readl(ISR) | ISR_IRF, ISR);
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writel(readl(&base->isr) | ISR_IRF, &base->isr);
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break;
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default:
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goto transfer_error_illegal_param;
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@ -252,10 +236,21 @@ i2c_transfer_finish:
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void i2c_init(int speed, int slaveaddr)
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{
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#ifdef CONFIG_SYS_I2C_INIT_BOARD
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/* call board specific i2c bus reset routine before accessing the */
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/* environment, which might be in a chip on that bus. For details */
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/* about this problem see doc/I2C_Edge_Conditions. */
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u32 icr;
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/*
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* call board specific i2c bus reset routine before accessing the
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* environment, which might be in a chip on that bus. For details
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* about this problem see doc/I2C_Edge_Conditions.
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*
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* disable I2C controller first, otherwhise it thinks we want to
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* talk to the slave port...
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*/
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icr = readl(&base->icr);
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writel(readl(&base->icr) & ~(ICR_SCLE | ICR_IUE), &base->icr);
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i2c_init_board();
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writel(icr, &base->icr);
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#endif
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}
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83
drivers/i2c/mv_i2c.h
Normal file
83
drivers/i2c/mv_i2c.h
Normal file
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@ -0,0 +1,83 @@
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/*
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* (C) Copyright 2011
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* Marvell Inc, <www.marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
|
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
|
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*
|
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* You should have received a copy of the GNU General Public License
|
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _MV_I2C_H_
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#define _MV_I2C_H_
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extern void i2c_clk_enable(void);
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/* Shall the current transfer have a start/stop condition? */
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#define I2C_COND_NORMAL 0
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#define I2C_COND_START 1
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#define I2C_COND_STOP 2
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/* Shall the current transfer be ack/nacked or being waited for it? */
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#define I2C_ACKNAK_WAITACK 1
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#define I2C_ACKNAK_SENDACK 2
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#define I2C_ACKNAK_SENDNAK 4
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/* Specify who shall transfer the data (master or slave) */
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#define I2C_READ 0
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#define I2C_WRITE 1
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#if (CONFIG_SYS_I2C_SPEED == 400000)
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#define I2C_ICR_INIT (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD \
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| ICR_SCLE)
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#else
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#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
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#endif
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#define I2C_ISR_INIT 0x7FF
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/* ----- Control register bits ---------------------------------------- */
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#define ICR_START 0x1 /* start bit */
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#define ICR_STOP 0x2 /* stop bit */
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#define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */
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#define ICR_TB 0x8 /* transfer byte bit */
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#define ICR_MA 0x10 /* master abort */
|
||||
#define ICR_SCLE 0x20 /* master clock enable, mona SCLEA */
|
||||
#define ICR_IUE 0x40 /* unit enable */
|
||||
#define ICR_GCD 0x80 /* general call disable */
|
||||
#define ICR_ITEIE 0x100 /* enable tx interrupts */
|
||||
#define ICR_IRFIE 0x200 /* enable rx interrupts, mona: DRFIE */
|
||||
#define ICR_BEIE 0x400 /* enable bus error ints */
|
||||
#define ICR_SSDIE 0x800 /* slave STOP detected int enable */
|
||||
#define ICR_ALDIE 0x1000 /* enable arbitration interrupt */
|
||||
#define ICR_SADIE 0x2000 /* slave address detected int enable */
|
||||
#define ICR_UR 0x4000 /* unit reset */
|
||||
#define ICR_FM 0x8000 /* Fast Mode */
|
||||
|
||||
/* ----- Status register bits ----------------------------------------- */
|
||||
|
||||
#define ISR_RWM 0x1 /* read/write mode */
|
||||
#define ISR_ACKNAK 0x2 /* ack/nak status */
|
||||
#define ISR_UB 0x4 /* unit busy */
|
||||
#define ISR_IBB 0x8 /* bus busy */
|
||||
#define ISR_SSD 0x10 /* slave stop detected */
|
||||
#define ISR_ALD 0x20 /* arbitration loss detected */
|
||||
#define ISR_ITE 0x40 /* tx buffer empty */
|
||||
#define ISR_IRF 0x80 /* rx buffer full */
|
||||
#define ISR_GCAD 0x100 /* general call address detected */
|
||||
#define ISR_SAD 0x200 /* slave address detected */
|
||||
#define ISR_BED 0x400 /* bus error no ACK/NAK */
|
||||
|
||||
#endif
|
||||
|
|
@ -141,6 +141,7 @@
|
|||
* I2C bus
|
||||
*/
|
||||
#define CONFIG_I2C_MV 1
|
||||
#define CONFIG_MV_I2C_REG 0x40301680
|
||||
#define CONFIG_HARD_I2C 1
|
||||
#define CONFIG_SYS_I2C_SPEED 50000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0xfe
|
||||
|
|
|
|||
|
|
@ -62,6 +62,7 @@
|
|||
* I2C bus
|
||||
*/
|
||||
#define CONFIG_I2C_MV 1
|
||||
#define CONFIG_MV_I2C_REG 0x40301680
|
||||
#define CONFIG_HARD_I2C 1
|
||||
#define CONFIG_SYS_I2C_SPEED 50000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0xfe
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue