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Blackfin: cache core/system clock values

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Calculating the clocks requires a bit of calls to gcc math functions, so
cache the values after the first run since they'll most likely never
change once U-Boot is up and running.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger 2008-10-24 22:48:47 -04:00
parent 6957a6209b
commit 40599239e7
4 changed files with 80 additions and 44 deletions
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2
include/asm-blackfin/blackfin_local.h
View file

@ -52,6 +52,8 @@
# include <linux/types.h>
extern u_long get_vco(void);
extern u_long get_cclk(void);
extern u_long get_sclk(void);
# define bfin_revid() (*pCHIPID >> 28)

1
lib_blackfin/Makefile
View file

@ -39,6 +39,7 @@ SOBJS-y += memset.o
COBJS-y += board.o
COBJS-y += boot.o
COBJS-y += cache.o
COBJS-y += clocks.o
COBJS-y += muldi3.o
COBJS-$(CONFIG_POST) += post.o tests.o
COBJS-y += string.o

44
lib_blackfin/board.c
View file

@ -44,50 +44,6 @@ static inline void serial_early_puts(const char *s)
#endif
}
/* Get the input voltage */
static u_long get_vco(void)
{
u_long msel;
u_long vco;
msel = (*pPLL_CTL >> 9) & 0x3F;
if (0 == msel)
msel = 64;
vco = CONFIG_CLKIN_HZ;
vco >>= (1 & *pPLL_CTL); /* DF bit */
vco = msel * vco;
return vco;
}
/* Get the Core clock */
u_long get_cclk(void)
{
u_long csel, ssel;
if (*pPLL_STAT & 0x1)
return CONFIG_CLKIN_HZ;
ssel = *pPLL_DIV;
csel = ((ssel >> 4) & 0x03);
ssel &= 0xf;
if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
return get_vco() / ssel;
return get_vco() >> csel;
}
/* Get the System clock */
u_long get_sclk(void)
{
u_long ssel;
if (*pPLL_STAT & 0x1)
return CONFIG_CLKIN_HZ;
ssel = (*pPLL_DIV & 0xf);
return get_vco() / ssel;
}
static void *mem_malloc_start, *mem_malloc_end, *mem_malloc_brk;
static void mem_malloc_init(void)

77
lib_blackfin/clocks.c Normal file
View file

@ -0,0 +1,77 @@
/*
* clocks.c - figure out sclk/cclk/vco and such
*
* Copyright (c) 2005-2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#include <common.h>
#include <asm/blackfin.h>
/* Get the voltage input multiplier */
static u_long cached_vco_pll_ctl, cached_vco;
u_long get_vco(void)
{
u_long msel;
u_long pll_ctl = bfin_read_PLL_CTL();
if (pll_ctl == cached_vco_pll_ctl)
return cached_vco;
else
cached_vco_pll_ctl = pll_ctl;
msel = (pll_ctl >> 9) & 0x3F;
if (0 == msel)
msel = 64;
cached_vco = CONFIG_CLKIN_HZ;
cached_vco >>= (1 & pll_ctl); /* DF bit */
cached_vco *= msel;
return cached_vco;
}
/* Get the Core clock */
static u_long cached_cclk_pll_div, cached_cclk;
u_long get_cclk(void)
{
u_long csel, ssel;
if (bfin_read_PLL_STAT() & 0x1)
return CONFIG_CLKIN_HZ;
ssel = bfin_read_PLL_DIV();
if (ssel == cached_cclk_pll_div)
return cached_cclk;
else
cached_cclk_pll_div = ssel;
csel = ((ssel >> 4) & 0x03);
ssel &= 0xf;
if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
cached_cclk = get_vco() / ssel;
else
cached_cclk = get_vco() >> csel;
return cached_cclk;
}
/* Get the System clock */
static u_long cached_sclk_pll_div, cached_sclk;
u_long get_sclk(void)
{
u_long ssel;
if (bfin_read_PLL_STAT() & 0x1)
return CONFIG_CLKIN_HZ;
ssel = bfin_read_PLL_DIV();
if (ssel == cached_sclk_pll_div)
return cached_sclk;
else
cached_sclk_pll_div = ssel;
ssel &= 0xf;
cached_sclk = get_vco() / ssel;
return cached_sclk;
}