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mv_ddr: ddr3: Use correct bitmask for read sample delay

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In the Armada 385 functional spec (MV-S109094-00 Rev. C) the read sample
delay fields are 5 bits wide. Use the correct bitmask of 0x1f when
extracting the value.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>

[upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22]
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Chris Packham 2020-05-27 13:31:29 +12:00 • committed by Stefan Roese
parent 61608f395e
commit 40ed88529c
1 changed files with 1 additions and 1 deletions

2
drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
View file

@ -11,7 +11,7 @@
#define VREF_MAX_INDEX 7
#define MAX_VALUE (1024 - 1)
#define MIN_VALUE (-MAX_VALUE)
#define GET_RD_SAMPLE_DELAY(data, cs) ((data >> rd_sample_mask[cs]) & 0xf)
#define GET_RD_SAMPLE_DELAY(data, cs) ((data >> rd_sample_mask[cs]) & 0x1f)
u32 ca_delay;
int ddr3_tip_centr_skip_min_win_check = 0;