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eNET: Define MMCR values in config.h
This commit is contained in:
Graeme Russ
parent
218310018a
commit
420c7c054b
3 changed files with 443 additions and 44 deletions
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@ -53,36 +53,57 @@ static void enet_toggle_run_led(void);
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*/
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int board_early_init_f(void)
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{
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writeb(0x01, &sc520_mmcr->gpcsrt); /* GP Chip Select Recovery Time */
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writeb(0x07, &sc520_mmcr->gpcspw); /* GP Chip Select Pulse Width */
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writeb(0x00, &sc520_mmcr->gpcsoff); /* GP Chip Select Offset */
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writeb(0x05, &sc520_mmcr->gprdw); /* GP Read pulse width */
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writeb(0x01, &sc520_mmcr->gprdoff); /* GP Read offset */
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writeb(0x05, &sc520_mmcr->gpwrw); /* GP Write pulse width */
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writeb(0x01, &sc520_mmcr->gpwroff); /* GP Write offset */
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u16 pio_out_cfg = 0x0000;
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writew(0x0630, &sc520_mmcr->piodata15_0); /* PIO15_PIO0 Data */
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writew(0x2000, &sc520_mmcr->piodata31_16); /* PIO31_PIO16 Data */
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writew(0x2000, &sc520_mmcr->piodir31_16); /* GPIO Direction */
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writew(0x87b5, &sc520_mmcr->piodir15_0); /* GPIO Direction */
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writew(0x0dfe, &sc520_mmcr->piopfs31_16); /* GPIO pin function 31-16 reg */
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writew(0x200a, &sc520_mmcr->piopfs15_0); /* GPIO pin function 15-0 reg */
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writeb(0xf8, &sc520_mmcr->cspfs); /* Chip Select Pin Function Select */
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/* Configure General Purpose Bus timing */
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writeb(CONFIG_SYS_SC520_GPCSRT, &sc520_mmcr->gpcsrt);
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writeb(CONFIG_SYS_SC520_GPCSPW, &sc520_mmcr->gpcspw);
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writeb(CONFIG_SYS_SC520_GPCSOFF, &sc520_mmcr->gpcsoff);
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writeb(CONFIG_SYS_SC520_GPRDW, &sc520_mmcr->gprdw);
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writeb(CONFIG_SYS_SC520_GPRDOFF, &sc520_mmcr->gprdoff);
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writeb(CONFIG_SYS_SC520_GPWRW, &sc520_mmcr->gpwrw);
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writeb(CONFIG_SYS_SC520_GPWROFF, &sc520_mmcr->gpwroff);
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writel(0x200713f8, &sc520_mmcr->par[2]); /* Uart A (GPCS0, 0x013f8, 8 Bytes) */
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writel(0x2c0712f8, &sc520_mmcr->par[3]); /* Uart B (GPCS3, 0x012f8, 8 Bytes) */
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writel(0x300711f8, &sc520_mmcr->par[4]); /* Uart C (GPCS4, 0x011f8, 8 Bytes) */
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writel(0x340710f8, &sc520_mmcr->par[5]); /* Uart D (GPCS5, 0x010f8, 8 Bytes) */
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writel(0xe3ffc000, &sc520_mmcr->par[6]); /* SDRAM (0x00000000, 128MB) */
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writel(0xaa3fd000, &sc520_mmcr->par[7]); /* StrataFlash (ROMCS1, 0x10000000, 16MB) */
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writel(0xca3fd100, &sc520_mmcr->par[8]); /* StrataFlash (ROMCS2, 0x11000000, 16MB) */
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writel(0x4203d900, &sc520_mmcr->par[9]); /* SRAM (GPCS0, 0x19000000, 1MB) */
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writel(0x4e03d910, &sc520_mmcr->par[10]); /* SRAM (GPCS3, 0x19100000, 1MB) */
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writel(0x50018100, &sc520_mmcr->par[11]); /* DP-RAM (GPCS4, 0x18100000, 4kB) */
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writel(0x54020000, &sc520_mmcr->par[12]); /* CFLASH1 (0x200000000, 4kB) */
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writel(0x5c020001, &sc520_mmcr->par[13]); /* CFLASH2 (0x200010000, 4kB) */
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/* writel(0x8bfff800, &sc520_mmcr->par14); */ /* BOOTCS at 0x18000000 */
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/* writel(0x38201000, &sc520_mmcr->par15); */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */
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/* Configure Programmable Input/Output Pins */
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writew(CONFIG_SYS_SC520_PIODIR15_0, &sc520_mmcr->piodir15_0);
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writew(CONFIG_SYS_SC520_PIODIR31_16, &sc520_mmcr->piodir31_16);
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writew(CONFIG_SYS_SC520_PIOPFS31_16, &sc520_mmcr->piopfs31_16);
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writew(CONFIG_SYS_SC520_PIOPFS15_0, &sc520_mmcr->piopfs15_0);
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writeb(CONFIG_SYS_SC520_CSPFS, &sc520_mmcr->cspfs);
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writeb(CONFIG_SYS_SC520_CLKSEL, &sc520_mmcr->clksel);
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/*
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* Turn off top board
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* Set StrataFlash chips to 16-bit width
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* Set StrataFlash chips to normal (non reset/power down) mode
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*/
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pio_out_cfg |= CONFIG_SYS_ENET_TOP_BRD_PWR;
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pio_out_cfg |= CONFIG_SYS_ENET_SF_WIDTH;
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pio_out_cfg |= CONFIG_SYS_ENET_SF1_MODE;
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pio_out_cfg |= CONFIG_SYS_ENET_SF2_MODE;
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writew(pio_out_cfg, &sc520_mmcr->pioset15_0);
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/* Turn off auxiliary power output */
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writew(CONFIG_SYS_ENET_AUX_PWR, &sc520_mmcr->pioclr15_0);
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/* Clear FPGA program mode */
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writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16);
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/* Configure Programmable Address Regions */
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writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[2]);
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writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[3]);
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writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[4]);
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writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[5]);
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writel(CONFIG_SYS_SC520_SDRAM_PAR, &sc520_mmcr->par[6]);
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writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[7]);
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writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[8]);
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writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[9]);
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writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[10]);
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writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[11]);
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writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[12]);
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writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[13]);
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/* writel(CONFIG_SYS_SC520_BOOTCS_PAR, &sc520_mmcr->par14); */
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/* writel(CONFIG_SYS_SC520_LLIO_PAR, &sc520_mmcr->par15); */
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/* Disable Watchdog */
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writew(0x3333, &sc520_mmcr->wdtmrctl);
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@ -90,24 +111,19 @@ int board_early_init_f(void)
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writew(0x0000, &sc520_mmcr->wdtmrctl);
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/* Chip Select Configuration */
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writew(0x0033, &sc520_mmcr->bootcsctl);
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writew(0x0615, &sc520_mmcr->romcs1ctl);
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writew(0x0615, &sc520_mmcr->romcs2ctl);
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writew(CONFIG_SYS_SC520_BOOTCS_CTRL, &sc520_mmcr->bootcsctl);
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writew(CONFIG_SYS_SC520_ROMCS1_CTRL, &sc520_mmcr->romcs1ctl);
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writew(CONFIG_SYS_SC520_ROMCS2_CTRL, &sc520_mmcr->romcs2ctl);
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/*
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* Set the timer pin mapping
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* no clock frequency selected, use 1.1892MHz
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*/
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writeb(0x72, &sc520_mmcr->clksel);
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writeb(CONFIG_SYS_SC520_ADDDECCTL, &sc520_mmcr->adddecctl);
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writeb(CONFIG_SYS_SC520_UART1CTL, &sc520_mmcr->uart1ctl);
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writeb(CONFIG_SYS_SC520_UART2CTL, &sc520_mmcr->uart2ctl);
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writeb(0x00, &sc520_mmcr->adddecctl);
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writeb(0x07, &sc520_mmcr->uart1ctl);
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writeb(0x07, &sc520_mmcr->uart2ctl);
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writeb(0x06, &sc520_mmcr->sysarbctl);
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writew(0x0003, &sc520_mmcr->sysarbmenb);
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writeb(CONFIG_SYS_SC520_SYSARBCTL, &sc520_mmcr->sysarbctl);
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writew(CONFIG_SYS_SC520_SYSARBMENB, &sc520_mmcr->sysarbmenb);
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/* enable posted-writes */
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writeb(0x04, &sc520_mmcr->hbctl);
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writeb(CONFIG_SYS_SC520_HBCTL, &sc520_mmcr->hbctl);
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return 0;
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}
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@ -29,6 +29,7 @@
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/* #include <asm/ic/sc520_defs.h> */
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#include "config.h"
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#include "hardware.h"
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#include <asm/ic/sc520.h>
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@ -48,12 +49,12 @@ board_init16:
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/* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */
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movl $(SC520_PAR14 - SC520_MMCR_BASE), %edi
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movl $0x8bfff800, %eax /* TODO: Check this */
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movl $CONFIG_SYS_SC520_BOOTCS_PAR, %eax
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movl %eax, (%di)
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/* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */
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movl $(SC520_PAR15 - SC520_MMCR_BASE), %edi
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movl $0x38201000, %eax
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movl $CONFIG_SYS_SC520_LLIO_PAR, %eax
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movl %eax, (%di)
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/* Disable SDRAM write buffer */
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@ -247,6 +247,388 @@
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#define CONFIG_SYS_FPGA_MAX_FINALISE_TIME 10 /* milliseconds */
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#define CONFIG_SYS_FPGA_SSI_DATA_RATE 8333 /* kHz (33.3333MHz xtal) */
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/*-----------------------------------------------------------------------
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* BOOTCS Control (for AM29LV040B-120JC)
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*
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* 000 0 00 0 000 11 0 011 }- 0x0033
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* \ / | \| | \ / \| | \ /
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* | | | | | | | |
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* | | | | | | | +---- 3 Wait States (First Access)
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* | | | | | | +------- Reserved
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* | | | | | +--------- 3 Wait States (Subsequent Access)
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* | | | | +------------- Reserved
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* | | | +---------------- Non-Paged Mode
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* | | +------------------ 8 Bit Wide
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* | +--------------------- GP Bus
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* +------------------------ Reserved
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*/
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#define CONFIG_SYS_SC520_BOOTCS_CTRL 0x0033
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/*-----------------------------------------------------------------------
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* ROMCS Control (for E28F128J3A-150 StrataFlash)
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*
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* 000 0 01 1 000 01 0 101 }- 0x0615
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* \ / | \| | \ / \| | \ /
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* | | | | | | | |
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* | | | | | | | +---- 5 Wait States (First Access)
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* | | | | | | +------- Reserved
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* | | | | | +--------- 1 Wait State (Subsequent Access)
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* | | | | +------------- Reserved
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* | | | +---------------- Paged Mode
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* | | +------------------ 16 Bit Wide
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* | +--------------------- GP Bus
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* +------------------------ Reserved
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*/
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#define CONFIG_SYS_SC520_ROMCS1_CTRL 0x0615
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#define CONFIG_SYS_SC520_ROMCS2_CTRL 0x0615
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/*-----------------------------------------------------------------------
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* SC520 General Purpose Bus configuration
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*
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* Chip Select Offset 1 Clock Cycle
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* Chip Select Pulse Width 8 Clock Cycles
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* Chip Select Read Offset 2 Clock Cycles
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* Chip Select Read Width 6 Clock Cycles
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* Chip Select Write Offset 2 Clock Cycles
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* Chip Select Write Width 6 Clock Cycles
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* Chip Select Recovery Time 2 Clock Cycles
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*
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* Timing Diagram (from SC520 Register Set Manual - Order #22005B)
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*
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* |<-------------General Purpose Bus Cycle---------------->|
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* | |
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* ----------------------\__________________/------------------
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* |<--(GPCSOFF + 1)-->|<--(GPCSPW + 1)-->|<-(GPCSRT + 1)-> |
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*
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* ------------------------\_______________/-------------------
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* |<---(GPRDOFF + 1)--->|<-(GPRDW + 1)->|
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*
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* --------------------------\_______________/-----------------
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* |<----(GPWROFF + 1)---->|<-(GPWRW + 1)->|
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*
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* ________/-----------\_______________________________________
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* |<--->|<--------->|
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* ^ ^
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* (GPALEOFF + 1) |
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* |
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* (GPALEW + 1)
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*/
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#define CONFIG_SYS_SC520_GPCSOFF 0x00
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#define CONFIG_SYS_SC520_GPCSPW 0x07
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#define CONFIG_SYS_SC520_GPRDOFF 0x01
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#define CONFIG_SYS_SC520_GPRDW 0x05
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#define CONFIG_SYS_SC520_GPWROFF 0x01
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#define CONFIG_SYS_SC520_GPWRW 0x05
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#define CONFIG_SYS_SC520_GPCSRT 0x01
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/*-----------------------------------------------------------------------
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* SC520 Programmable I/O configuration
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*
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* Pin Mode Dir. Description
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* ----------------------------------------------------------------------
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* PIO0 PIO Output Unused
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* PIO1 GPBHE# Output GP Bus Byte High Enable (active low)
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* PIO2 PIO Output Auxiliary power output enable
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* PIO3 GPAEN Output GP Bus Address Enable
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* PIO4 PIO Output Top Board Enable (active low)
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* PIO5 PIO Output StrataFlash 16 bit mode (low = 8 bit mode)
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* PIO6 PIO Input Data output of Power Supply ADC
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* PIO7 PIO Output Clock input to Power Supply ADC
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* PIO8 PIO Output Chip Select input of Power Supply ADC
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* PIO9 PIO Output StrataFlash 1 Reset / Power Down (active low)
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* PIO10 PIO Output StrataFlash 2 Reset / Power Down (active low)
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* PIO11 PIO Input StrataFlash 1 Status
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* PIO12 PIO Input StrataFlash 2 Status
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* PIO13 GPIRQ10# Input Can Bus / I2C IRQ (active low)
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* PIO14 PIO Input Low Input Voltage Warning (active low)
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* PIO15 PIO Output Watchdog (must toggle at least every 1.6s)
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* PIO16 PIO Input Power Fail
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* PIO17 GPIRQ6 Input Compact Flash 1 IRQ (active low)
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* PIO18 GPIRQ5 Input Compact Flash 2 IRQ (active low)
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* PIO19 GPIRQ4# Input Dual-Port RAM IRQ (active low)
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* PIO20 GPIRQ3 Input UART D IRQ
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* PIO21 GPIRQ2 Input UART C IRQ
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* PIO22 GPIRQ1 Input UART B IRQ
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* PIO23 GPIRQ0 Input UART A IRQ
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* PIO24 GPDBUFOE# Output GP Bus Data Bus Buffer Output Enable
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* PIO25 PIO Input Battery OK Indication
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* PIO26 GPMEMCS16# Input GP Bus Memory Chip-Select 16-bit access
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* PIO27 GPCS0# Output SRAM 1 Chip Select
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* PIO28 PIO Input Top Board UART CTS
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* PIO29 PIO Output FPGA Program Mode (active low)
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* PIO30 PIO Input FPGA Initialised (active low)
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* PIO31 PIO Input FPGA Done (active low)
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*/
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#define CONFIG_SYS_SC520_PIOPFS15_0 0x200a
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#define CONFIG_SYS_SC520_PIOPFS31_16 0x0dfe
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#define CONFIG_SYS_SC520_PIODIR15_0 0x87bf
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#define CONFIG_SYS_SC520_PIODIR31_16 0x2900
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/*-----------------------------------------------------------------------
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* PIO Pin defines
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*/
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#define CONFIG_SYS_ENET_AUX_PWR 0x0004
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#define CONFIG_SYS_ENET_TOP_BRD_PWR 0x0010
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#define CONFIG_SYS_ENET_SF_WIDTH 0x0020
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#define CONFIG_SYS_ENET_PWR_ADC_DATA 0x0040
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#define CONFIG_SYS_ENET_PWR_ADC_CLK 0x0080
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#define CONFIG_SYS_ENET_PWR_ADC_CS 0x0100
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#define CONFIG_SYS_ENET_SF1_MODE 0x0200
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#define CONFIG_SYS_ENET_SF2_MODE 0x0400
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#define CONFIG_SYS_ENET_SF1_STATUS 0x0800
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#define CONFIG_SYS_ENET_SF2_STATUS 0x1000
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#define CONFIG_SYS_ENET_PWR_STATUS 0x4000
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#define CONFIG_SYS_ENET_WATCHDOG 0x8000
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#define CONFIG_SYS_ENET_PWR_FAIL 0x0001
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#define CONFIG_SYS_ENET_BAT_OK 0x0200
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#define CONFIG_SYS_ENET_TOP_BRD_CTS 0x1000
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#define CONFIG_SYS_ENET_FPGA_PROG 0x2000
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#define CONFIG_SYS_ENET_FPGA_INIT 0x4000
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#define CONFIG_SYS_ENET_FPGA_DONE 0x8000
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/*-----------------------------------------------------------------------
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* Chip Select Pin Function Select
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*
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* 1 1 1 1 1 0 0 0 }- 0xf8
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* | | | | | | | |
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* | | | | | | | +--- Reserved
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* | | | | | | +----- GPCS1_SEL = ROMCS1#
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* | | | | | +------- GPCS2_SEL = ROMCS2#
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* | | | | +--------- GPCS3_SEL = GPCS3
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* | | | +----------- GPCS4_SEL = GPCS4
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* | | +------------- GPCS5_SEL = GPCS5
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* | +--------------- GPCS6_SEL = GPCS6
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* +----------------- GPCS7_SEL = GPCS7
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*/
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#define CONFIG_SYS_SC520_CSPFS 0xf8
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/*-----------------------------------------------------------------------
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* Clock Select (CLKTIMER[CLKTEST] pin)
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*
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* 0 111 00 1 0 }- 0x72
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* | \ / \| | |
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* | | | | +--- Pin Disabled
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* | | | +----- Pin is an output
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* | | +------- Reserved
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* | +----------- Disabled (pin stays Low)
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* +-------------- Reserved
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*/
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#define CONFIG_SYS_SC520_CLKSEL 0x72
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/*-----------------------------------------------------------------------
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* Address Decode Control
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*
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* 0 00 0 0 0 0 0 }- 0x00
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* | \| | | | | |
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* | | | | | | +--- Integrated UART 1 is enabled
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* | | | | | +----- Integrated UART 2 is enabled
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* | | | | +------- Integrated RTC is enabled
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* | | | +--------- Reserved
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* | | +----------- I/O Hole accesses are forwarded to the external GP bus
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* | +------------- Reserved
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* +---------------- Write-protect violations do not generate an IRQ
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*/
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#define CONFIG_SYS_SC520_ADDDECCTL 0x00
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/*-----------------------------------------------------------------------
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* UART Control
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*
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* 00000 1 1 1 }- 0x07
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* \___/ | | |
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* | | | +--- Transmit TC interrupt enable
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* | | +----- Receive TC interrupt enable
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* | +------- 1.8432 MHz
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* +----------- Reserved
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*/
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#define CONFIG_SYS_SC520_UART1CTL 0x07
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#define CONFIG_SYS_SC520_UART2CTL 0x07
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/*-----------------------------------------------------------------------
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* System Arbiter Control
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*
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* 00000 1 1 0 }- 0x06
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* \___/ | | |
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* | | | +--- Disable PCI Bus Arbiter Grant Time-Out Interrupt
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* | | +----- The system arbiter operates in concurrent mode
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* | +------- Park the PCI bus on the last master that acquired the bus
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* +----------- Reserved
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*/
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#define CONFIG_SYS_SC520_SYSARBCTL 0x06
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* System Arbiter Master Enable
|
||||
*
|
||||
* 00000000000 0 0 0 1 1 }- 0x06
|
||||
* \_________/ | | | | |
|
||||
* | | | | | +--- PCI master REQ0 enabled (Ethernet 1)
|
||||
* | | | | +----- PCI master REQ1 enabled (Ethernet 2)
|
||||
* | | | +------- PCI master REQ2 disabled
|
||||
* | | +--------- PCI master REQ3 disabled
|
||||
* | +----------- PCI master REQ4 disabled
|
||||
* +------------------ Reserved
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_SYSARBMENB 0x0003
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* System Arbiter Master Enable
|
||||
*
|
||||
* 0 0000 0 00 0000 1 000 }- 0x06
|
||||
* | \__/ | \| \__/ | \_/
|
||||
* | | | | | | +---- Reserved
|
||||
* | | | | | +------- Enable CPU-to-PCI bus write posting
|
||||
* | | | | +---------- Reserved
|
||||
* | | | +-------------- PCI bus reads to SDRAM are not automatically
|
||||
* | | | retried
|
||||
* | | +----------------- Target read FIFOs are not snooped during write
|
||||
* | | transactions
|
||||
* | +-------------------- Reserved
|
||||
* +------------------------ Deassert the PCI bus reset signal
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_HBCTL 0x08
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PAR for Boot Flash - 512kB @ 0x38000000, BOOTCS
|
||||
* 100 0 1 0 1 00000000111 11100000000000 }- 0x8a01f800
|
||||
* \ / | | | | \----+----/ \-----+------/
|
||||
* | | | | | | +---------- Start at 0x38000000
|
||||
* | | | | | +----------------------- 512kB Region Size
|
||||
* | | | | | ((7 + 1) * 64kB)
|
||||
* | | | | +------------------------------ 64kB Page Size
|
||||
* | | | +-------------------------------- Writes Enabled (So it can be
|
||||
* | | | reprogrammed!)
|
||||
* | | +---------------------------------- Caching Disabled
|
||||
* | +------------------------------------ Execution Enabled
|
||||
* +--------------------------------------- BOOTCS
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_BOOTCS_PAR 0x8a01f800
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000, GPCS6
|
||||
*
|
||||
* 001 110 0 000100000 0001000000000000 }- 0x38201000
|
||||
* \ / \ / | \---+---/ \------+-------/
|
||||
* | | | | +----------- Start at 0x00001000
|
||||
* | | | +------------------------ 33 Bytes (0x20 + 1)
|
||||
* | | +------------------------------ Ignored
|
||||
* | +--------------------------------- GPCS6
|
||||
* +------------------------------------- GP Bus I/O
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_LLIO_PAR 0x38201000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PAR for Compact Flash Port #1 - 4kB @ 0x200000000, CS5
|
||||
* PAR for Compact Flash Port #2 - 4kB @ 0x200010000, CS7
|
||||
*
|
||||
* 010 101 0 0000000 100000000000000000 }- 0x54020000
|
||||
* 010 111 0 0000000 100000000000000001 }- 0x5c020001
|
||||
* \ / \ / | \--+--/ \-------+--------/
|
||||
* | | | | +------------ Start at 0x200000000
|
||||
* | | | | 0x200010000
|
||||
* | | | +------------------------- 4kB Region Size
|
||||
* | | | ((0 + 1) * 4kB)
|
||||
* | | +------------------------------ 4k Page Size
|
||||
* | +--------------------------------- GPCS5
|
||||
* | GPCS7
|
||||
* +------------------------------------- GP Bus Memory
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_CF1_PAR 0x54020000
|
||||
#define CONFIG_SYS_SC520_CF2_PAR 0x5c020001
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PAR for Extra 16550 UART A - 8 bytes @ 0x013f8, GPCS0
|
||||
* PAR for Extra 16550 UART B - 8 bytes @ 0x012f8, GPCS3
|
||||
* PAR for Extra 16550 UART C - 8 bytes @ 0x011f8, GPCS4
|
||||
* PAR for Extra 16550 UART D - 8 bytes @ 0x010f8, GPCS5
|
||||
*
|
||||
* 001 000 0 000000111 0001001111111000 }- 0x200713f8
|
||||
* 001 011 0 000000111 0001001011111000 }- 0x2c0712f8
|
||||
* 001 011 0 000000111 0001001011111000 }- 0x300711f8
|
||||
* 001 011 0 000000111 0001001011111000 }- 0x340710f8
|
||||
* \ / \ / | \---+---/ \------+-------/
|
||||
* | | | | +----------- Start at 0x013f8
|
||||
* | | | | 0x012f8
|
||||
* | | | | 0x011f8
|
||||
* | | | | 0x010f8
|
||||
* | | | +------------------------ 33 Bytes (32 + 1)
|
||||
* | | +------------------------------ Ignored
|
||||
* | +--------------------------------- GPCS6
|
||||
* +------------------------------------- GP Bus I/O
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_UARTA_PAR 0x200713f8
|
||||
#define CONFIG_SYS_SC520_UARTB_PAR 0x2c0712f8
|
||||
#define CONFIG_SYS_SC520_UARTC_PAR 0x300711f8
|
||||
#define CONFIG_SYS_SC520_UARTD_PAR 0x340710f8
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PAR for StrataFlash #1 - 16MB @ 0x10000000, ROMCS1
|
||||
* PAR for StrataFlash #2 - 16MB @ 0x11000000, ROMCS2
|
||||
*
|
||||
* 101 0 1 0 1 00011111111 01000000000000 }- 0xaa3fd000
|
||||
* 110 0 1 0 1 00011111111 01000100000000 }- 0xca3fd100
|
||||
* \ / | | | | \----+----/ \-----+------/
|
||||
* | | | | | | +---------- Start at 0x10000000
|
||||
* | | | | | | 0x11000000
|
||||
* | | | | | +----------------------- 16MB Region Size
|
||||
* | | | | | ((255 + 1) * 64kB)
|
||||
* | | | | +------------------------------ 64kB Page Size
|
||||
* | | | +-------------------------------- Writes Enabled
|
||||
* | | +---------------------------------- Caching Disabled
|
||||
* | +------------------------------------ Execution Enabled
|
||||
* +--------------------------------------- ROMCS1
|
||||
* ROMCS2
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_SF1_PAR 0xaa3fd000
|
||||
#define CONFIG_SYS_SC520_SF2_PAR 0xca3fd100
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PAR for SRAM #1 - 1MB @ 0x19000000, GPCS0
|
||||
* PAR for SRAM #2 - 1MB @ 0x19100000, GPCS3
|
||||
*
|
||||
* 010 000 1 00000001111 01100100000000 }- 0x4203d900
|
||||
* 010 011 1 00000001111 01100100010000 }- 0x4e03d910
|
||||
* \ / \ / | \----+----/ \-----+------/
|
||||
* | | | | +---------- Start at 0x19000000
|
||||
* | | | | 0x19100000
|
||||
* | | | +----------------------- 1MB Region Size
|
||||
* | | | ((15 + 1) * 64kB)
|
||||
* | | +------------------------------ 64kB Page Size
|
||||
* | +--------------------------------- GPCS0
|
||||
* | GPCS3
|
||||
* +------------------------------------- GP Bus Memory
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_SRAM1_PAR 0x4203d900
|
||||
#define CONFIG_SYS_SC520_SRAM2_PAR 0x4e03d910
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PAR for Dual-Port RAM - 4kB @ 0x18100000, GPCS4
|
||||
*
|
||||
* 010 100 0 00000000 11000000100000000 }- 0x50018100
|
||||
* \ / \ / | \---+--/ \-------+-------/
|
||||
* | | | | +----------- Start at 0x18100000
|
||||
* | | | +------------------------ 4kB Region Size
|
||||
* | | | ((0 + 1) * 4kB)
|
||||
* | | +------------------------------ 4kB Page Size
|
||||
* | +--------------------------------- GPCS4
|
||||
* +------------------------------------- GP Bus Memory
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_DPRAM_PAR 0x50018100
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PAR for SDRAM - 128MB @ 0x00000000
|
||||
* 111 0 0 0 1 11111111111 00000000000000 }- 0xe3ffc000
|
||||
* \ / | | | | \----+----/ \-----+------/
|
||||
* | | | | | | +---------- Start at 0x00000000
|
||||
* | | | | | +----------------------- 128MB Region Size
|
||||
* | | | | | ((2047 + 1) * 64kB)
|
||||
* | | | | +------------------------------ 64kB Page Size
|
||||
* | | | +-------------------------------- Writes Enabled
|
||||
* | | +---------------------------------- Caching Enabled
|
||||
* | +------------------------------------ Execution Enabled
|
||||
* +--------------------------------------- SDRAM
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_SDRAM_PAR 0xe3ffc000
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
extern unsigned long ip;
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue