mirror of
https://github.com/Fishwaldo/u-boot.git
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Coding Style cleanup, update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk
parent
2eb6e01049
commit
435dc8fcdb
4 changed files with 2678 additions and 135 deletions
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@ -31,16 +31,16 @@
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#include <asm/arch/clocks.h>
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#include "mem.h"
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#define APOLLON_CS0_BASE 0x00000000
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#define APOLLON_CS0_BASE 0x00000000
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#ifdef PRCM_CONFIG_I
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#define SDRC_ACTIM_CTRLA_0_VAL 0x7BA35907
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#define SDRC_ACTIM_CTRLB_0_VAL 0x00000013
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#define SDRC_RFR_CTRL_0_VAL 0x00044C01
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#define SDRC_ACTIM_CTRLA_0_VAL 0x7BA35907
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#define SDRC_ACTIM_CTRLB_0_VAL 0x00000013
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#define SDRC_RFR_CTRL_0_VAL 0x00044C01
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#elif defined(PRCM_CONFIG_II)
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#define SDRC_ACTIM_CTRLA_0_VAL 0x4A59B485
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#define SDRC_ACTIM_CTRLB_0_VAL 0x0000000C
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#define SDRC_RFR_CTRL_0_VAL 0x00030001
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#define SDRC_ACTIM_CTRLA_0_VAL 0x4A59B485
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#define SDRC_ACTIM_CTRLB_0_VAL 0x0000000C
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#define SDRC_RFR_CTRL_0_VAL 0x00030001
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#endif
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#define SDRAM_BASE_ADDRESS 0x80008000
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@ -66,100 +66,100 @@ flash_setup:
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ldr r1, =WD_UNLOCK2
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str r1, [r0, #WSPR]
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/* Pin muxing for SDRC */
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mov r1, #0x00
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ldr r0, =0x480000A1 /* ball C12, mode 0 */
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strb r1, [r0]
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/* Pin muxing for SDRC */
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mov r1, #0x00
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ldr r0, =0x480000A1 /* ball C12, mode 0 */
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strb r1, [r0]
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ldr r0, =0x48000032 /* ball D11, mode 0 */
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strb r1, [r0]
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ldr r0, =0x48000032 /* ball D11, mode 0 */
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strb r1, [r0]
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ldr r0, =0x480000A3 /* ball B13, mode 0 */
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strb r1, [r0]
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ldr r0, =0x480000A3 /* ball B13, mode 0 */
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strb r1, [r0]
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/* SDRC setting */
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ldr r0, =OMAP2420_SDRC_BASE
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ldr r1, =0x00000010
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str r1, [r0, #0x10]
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/* SDRC setting */
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ldr r0, =OMAP2420_SDRC_BASE
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ldr r1, =0x00000010
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str r1, [r0, #0x10]
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ldr r1, =0x00000100
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str r1, [r0, #0x44]
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ldr r1, =0x00000100
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str r1, [r0, #0x44]
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/* SDRC CS0 configuration */
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ldr r1, =0x00d04011
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str r1, [r0, #0x80]
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/* SDRC CS0 configuration */
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ldr r1, =0x00d04011
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str r1, [r0, #0x80]
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ldr r1, =SDRC_ACTIM_CTRLA_0_VAL
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str r1, [r0, #0x9C]
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ldr r1, =SDRC_ACTIM_CTRLA_0_VAL
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str r1, [r0, #0x9C]
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ldr r1, =SDRC_ACTIM_CTRLB_0_VAL
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str r1, [r0, #0xA0]
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ldr r1, =SDRC_ACTIM_CTRLB_0_VAL
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str r1, [r0, #0xA0]
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ldr r1, =SDRC_RFR_CTRL_0_VAL
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str r1, [r0, #0xA4]
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ldr r1, =SDRC_RFR_CTRL_0_VAL
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str r1, [r0, #0xA4]
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ldr r1, =0x00000041
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str r1, [r0, #0x70]
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ldr r1, =0x00000041
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str r1, [r0, #0x70]
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/* Manual command sequence */
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ldr r1, =0x00000007
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str r1, [r0, #0xA8]
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/* Manual command sequence */
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ldr r1, =0x00000007
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str r1, [r0, #0xA8]
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ldr r1, =0x00000000
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str r1, [r0, #0xA8]
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ldr r1, =0x00000000
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str r1, [r0, #0xA8]
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ldr r1, =0x00000001
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str r1, [r0, #0xA8]
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ldr r1, =0x00000001
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str r1, [r0, #0xA8]
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ldr r1, =0x00000002
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str r1, [r0, #0xA8]
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str r1, [r0, #0xA8]
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ldr r1, =0x00000002
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str r1, [r0, #0xA8]
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str r1, [r0, #0xA8]
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/*
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* CS0 SDRC Mode register
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* Burst length = 4 - DDR memory
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* Serial mode
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* CAS latency = 3
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*/
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ldr r1, =0x00000032
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str r1, [r0, #0x84]
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/*
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* CS0 SDRC Mode register
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* Burst length = 4 - DDR memory
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* Serial mode
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* CAS latency = 3
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*/
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ldr r1, =0x00000032
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str r1, [r0, #0x84]
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/* Note: You MUST set EMR values */
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/* EMR1 & EMR2 */
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ldr r1, =0x00000000
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str r1, [r0, #0x88]
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str r1, [r0, #0x8C]
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/* Note: You MUST set EMR values */
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/* EMR1 & EMR2 */
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ldr r1, =0x00000000
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str r1, [r0, #0x88]
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str r1, [r0, #0x8C]
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#ifdef OLD_SDRC_DLLA_CTRL
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/* SDRC_DLLA_CTRL */
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ldr r1, =0x00007306
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str r1, [r0, #0x60]
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/* SDRC_DLLA_CTRL */
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ldr r1, =0x00007306
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str r1, [r0, #0x60]
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ldr r1, =0x00007303
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str r1, [r0, #0x60]
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ldr r1, =0x00007303
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str r1, [r0, #0x60]
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#else
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/* SDRC_DLLA_CTRL */
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ldr r1, =0x00000506
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str r1, [r0, #0x60]
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/* SDRC_DLLA_CTRL */
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ldr r1, =0x00000506
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str r1, [r0, #0x60]
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ldr r1, =0x00000503
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str r1, [r0, #0x60]
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ldr r1, =0x00000503
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str r1, [r0, #0x60]
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#endif
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#ifdef __BROKEN_FEATURE__
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/* SDRC_DLLB_CTRL */
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ldr r1, =0x00000506
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str r1, [r0, #0x68]
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/* SDRC_DLLB_CTRL */
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ldr r1, =0x00000506
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str r1, [r0, #0x68]
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ldr r1, =0x00000503
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str r1, [r0, #0x68]
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ldr r1, =0x00000503
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str r1, [r0, #0x68]
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#endif
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/* little delay after init */
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mov r2, #0x1800
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/* little delay after init */
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mov r2, #0x1800
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1:
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subs r2, r2, #0x1
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bne 1b
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subs r2, r2, #0x1
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bne 1b
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/* Setup base address */
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ldr r0, =0x00000000 /* NOR address */
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@ -178,21 +178,21 @@ copy_loop:
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#endif
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prcm_setup:
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ldr r0, =OMAP2420_CM_BASE
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ldr r1, [r0, #0x544] /* CLKSEL2_PLL */
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bic r1, r1, #0x03
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orr r1, r1, #0x02
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str r1, [r0, #0x544]
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ldr r0, =OMAP2420_CM_BASE
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ldr r1, [r0, #0x544] /* CLKSEL2_PLL */
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bic r1, r1, #0x03
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orr r1, r1, #0x02
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str r1, [r0, #0x544]
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ldr r1, [r0, #0x500]
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bic r1, r1, #0x03
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orr r1, r1, #0x01
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str r1, [r0, #0x500]
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ldr r1, [r0, #0x500]
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bic r1, r1, #0x03
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orr r1, r1, #0x01
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str r1, [r0, #0x500]
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ldr r1, [r0, #0x140]
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bic r1, r1, #0x1f
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orr r1, r1, #0x02
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str r1, [r0, #0x140]
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ldr r1, [r0, #0x140]
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bic r1, r1, #0x1f
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orr r1, r1, #0x02
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str r1, [r0, #0x140]
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#ifdef PRCM_CONFIG_I
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ldr r1, =0x000003C3
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@ -204,58 +204,58 @@ prcm_setup:
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ldr r1, =0x00000002
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str r1, [r0, #0x340]
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ldr r1, =CM_CLKSEL1_CORE
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ldr r1, =CM_CLKSEL1_CORE
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#ifdef PRCM_CONFIG_I
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ldr r2, =0x08300C44
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ldr r2, =0x08300C44
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#else
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ldr r2, =0x04600C26
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ldr r2, =0x04600C26
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#endif
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str r2, [r1]
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str r2, [r1]
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ldr r0, =OMAP2420_CM_BASE
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ldr r1, [r0, #0x084]
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and r1, r1, #0x01
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cmp r1, #0x01
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bne clkvalid
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ldr r0, =OMAP2420_CM_BASE
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ldr r1, [r0, #0x084]
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and r1, r1, #0x01
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cmp r1, #0x01
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bne clkvalid
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b .
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b .
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clkvalid:
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mov r1, #0x01
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str r1, [r0, #0x080]
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mov r1, #0x01
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str r1, [r0, #0x080]
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waitvalid:
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ldr r1, [r0, #0x084]
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and r1, r1, #0x01
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cmp r1, #0x00
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bne waitvalid
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ldr r1, [r0, #0x084]
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and r1, r1, #0x01
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cmp r1, #0x00
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bne waitvalid
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ldr r0, =CM_CLKSEL1_PLL
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ldr r0, =CM_CLKSEL1_PLL
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#ifdef PRCM_CONFIG_I
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ldr r1, =0x01837100
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ldr r1, =0x01837100
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#else
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ldr r1, =0x01832100
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ldr r1, =0x01832100
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#endif
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str r1, [r0]
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str r1, [r0]
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ldr r0, =PRCM_CLKCFG_CTRL
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mov r1, #0x01
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str r1, [r0]
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mov r6, #0x50
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ldr r0, =PRCM_CLKCFG_CTRL
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mov r1, #0x01
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str r1, [r0]
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mov r6, #0x50
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loop1:
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subs r6, r6, #0x01
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cmp r6, #0x01
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bne loop1
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subs r6, r6, #0x01
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cmp r6, #0x01
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bne loop1
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ldr r0, =CM_CLKEN_PLL
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ldr r0, =CM_CLKEN_PLL
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mov r1, #0x0f
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str r1, [r0]
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str r1, [r0]
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mov r6, #0x100
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mov r6, #0x100
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loop2:
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subs r6, r6, #0x01
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cmp r6, #0x01
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bne loop2
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subs r6, r6, #0x01
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cmp r6, #0x01
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bne loop2
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ldr r0, =0x48008200
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ldr r1, =0xbfffffff
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@ -23,7 +23,6 @@
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <i2c.h>
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#include <malloc.h>
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@ -32,14 +31,12 @@
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#include "fsl_diu_fb.h"
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#ifdef DEBUG
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#define DPRINTF(fmt, args...) printf("%s: " fmt,__FUNCTION__,## args)
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#else
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#define DPRINTF(fmt, args...)
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#endif
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struct fb_videomode {
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const char *name; /* optional */
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unsigned int refresh; /* optional */
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@ -182,8 +179,6 @@ struct diu_addr {
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#define MAX_CURS 32
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static struct fb_info fsl_fb_info;
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static struct diu_addr gamma, cursor;
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static struct diu_ad fsl_diu_fb_ad __attribute__ ((aligned(32)));
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@ -206,7 +201,6 @@ static int fsl_diu_disable_panel(struct fb_info *info);
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static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align);
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static u32 get_busfreq(void);
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int fsl_diu_init(int xres,
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unsigned int pixel_format,
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int gamma_fix,
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@ -39,14 +39,14 @@
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/* Clock config to target*/
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#define PRCM_CONFIG_I 1
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//#define PRCM_CONFIG_II 1
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/* #define PRCM_CONFIG_II 1 */
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/* Boot method */
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/* uncomment if you use NOR boot */
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//#define CFG_NOR_BOOT 1
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/* #define CFG_NOR_BOOT 1 */
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/* uncomment if you use NOR on CS3 */
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//#define CFG_USE_NOR 1
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/* #define CFG_USE_NOR 1 */
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#ifdef CFG_NOR_BOOT
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#undef CFG_USE_NOR
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@ -111,13 +111,13 @@
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#define CFG_I2C_SLAVE 1
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#define CONFIG_DRIVER_OMAP24XX_I2C
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/* allow to overwrite serial and ethaddr */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 115200
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#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DHCP
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@ -180,8 +180,8 @@
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#define CFG_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */
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/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2)
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* or by 32KHz clk, or from external sig. This rate is divided by a local
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/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2)
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* or by 32KHz clk, or from external sig. This rate is divided by a local
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* divisor.
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*/
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#define V_PVT 7 /* use with 12MHz/128 */
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@ -193,7 +193,7 @@
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/*-----------------------------------------------------------------------
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE SZ_128K /* regular stack */
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#ifdef CONFIG_USE_IRQ
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@ -223,7 +223,7 @@
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*/
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# define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
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# define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
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//#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
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/* #define CFG_FLASH_USE_BUFFER_WRITE 1 */ /* Use buffered writes (~10x faster) */
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# define CFG_FLASH_PROTECTION 1 /* Use h/w sector protection*/
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#else /* !CFG_USE_NOR */
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