mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-21 14:41:31 +00:00
Added interrupt handling capabilities for mpc5xxx processors.
Also added Linux like BUG() macros.
This commit is contained in:
Detlev Zundel
parent
e8143e72e1
commit
43835aac48
3 changed files with 342 additions and 15 deletions
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@ -1,4 +1,7 @@
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/*
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* (C) Copyright 2006
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* Detlev Zundel, DENX Software Engineering, dzu@denx.de
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*
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* (C) Copyright -2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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@ -24,18 +27,212 @@
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* MA 02111-1307 USA
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*/
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/*
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* interrupts.c - just enough support for the decrementer/timer
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/* this section was ripped out of arch/ppc/syslib/mpc52xx_pic.c in the
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* Linux 2.6 source with the following copyright.
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*
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* Based on (well, mostly copied from) the code from the 2.4 kernel by
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* Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
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*
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* Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
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* Copyright (C) 2003 Montavista Software, Inc
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <command.h>
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int interrupt_init_cpu (ulong *decrementer_count)
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struct irq_action {
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interrupt_handler_t *handler;
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void *arg;
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ulong count;
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};
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static struct irq_action irq_handlers[NR_IRQS];
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static struct mpc5xxx_intr *intr;
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static struct mpc5xxx_sdma *sdma;
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static void mpc5xxx_ic_disable(unsigned int irq)
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{
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u32 val;
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if (irq == MPC5XXX_IRQ0) {
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val = in_be32(&intr->ctrl);
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val &= ~(1 << 11);
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out_be32(&intr->ctrl, val);
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} else if (irq < MPC5XXX_IRQ1) {
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BUG();
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} else if (irq <= MPC5XXX_IRQ3) {
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val = in_be32(&intr->ctrl);
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val &= ~(1 << (10 - (irq - MPC5XXX_IRQ1)));
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out_be32(&intr->ctrl, val);
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} else if (irq < MPC5XXX_SDMA_IRQ_BASE) {
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val = in_be32(&intr->main_mask);
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val |= 1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE));
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out_be32(&intr->main_mask, val);
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} else if (irq < MPC5XXX_PERP_IRQ_BASE) {
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val = in_be32(&sdma->IntMask);
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val |= 1 << (irq - MPC5XXX_SDMA_IRQ_BASE);
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out_be32(&sdma->IntMask, val);
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} else {
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val = in_be32(&intr->per_mask);
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val |= 1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE));
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out_be32(&intr->per_mask, val);
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}
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}
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static void mpc5xxx_ic_enable(unsigned int irq)
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{
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u32 val;
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if (irq == MPC5XXX_IRQ0) {
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val = in_be32(&intr->ctrl);
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val |= 1 << 11;
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out_be32(&intr->ctrl, val);
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} else if (irq < MPC5XXX_IRQ1) {
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BUG();
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} else if (irq <= MPC5XXX_IRQ3) {
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val = in_be32(&intr->ctrl);
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val |= 1 << (10 - (irq - MPC5XXX_IRQ1));
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out_be32(&intr->ctrl, val);
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} else if (irq < MPC5XXX_SDMA_IRQ_BASE) {
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val = in_be32(&intr->main_mask);
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val &= ~(1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE)));
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out_be32(&intr->main_mask, val);
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} else if (irq < MPC5XXX_PERP_IRQ_BASE) {
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val = in_be32(&sdma->IntMask);
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val &= ~(1 << (irq - MPC5XXX_SDMA_IRQ_BASE));
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out_be32(&sdma->IntMask, val);
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} else {
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val = in_be32(&intr->per_mask);
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val &= ~(1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE)));
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out_be32(&intr->per_mask, val);
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}
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}
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static void mpc5xxx_ic_ack(unsigned int irq)
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{
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u32 val;
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/*
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* Only some irqs are reset here, others in interrupting hardware.
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*/
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switch (irq) {
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case MPC5XXX_IRQ0:
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val = in_be32(&intr->ctrl);
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val |= 0x08000000;
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out_be32(&intr->ctrl, val);
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break;
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case MPC5XXX_CCS_IRQ:
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val = in_be32(&intr->enc_status);
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val |= 0x00000400;
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out_be32(&intr->enc_status, val);
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break;
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case MPC5XXX_IRQ1:
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val = in_be32(&intr->ctrl);
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val |= 0x04000000;
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out_be32(&intr->ctrl, val);
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break;
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case MPC5XXX_IRQ2:
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val = in_be32(&intr->ctrl);
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val |= 0x02000000;
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out_be32(&intr->ctrl, val);
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break;
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case MPC5XXX_IRQ3:
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val = in_be32(&intr->ctrl);
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val |= 0x01000000;
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out_be32(&intr->ctrl, val);
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break;
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default:
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if (irq >= MPC5XXX_SDMA_IRQ_BASE
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&& irq < (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)) {
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out_be32(&sdma->IntPend,
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1 << (irq - MPC5XXX_SDMA_IRQ_BASE));
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}
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break;
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}
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}
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static void mpc5xxx_ic_disable_and_ack(unsigned int irq)
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{
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mpc5xxx_ic_disable(irq);
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mpc5xxx_ic_ack(irq);
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}
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static void mpc5xxx_ic_end(unsigned int irq)
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{
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mpc5xxx_ic_enable(irq);
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}
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void mpc5xxx_init_irq(void)
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{
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u32 intr_ctrl;
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/* Remap the necessary zones */
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intr = (struct mpc5xxx_intr *)(MPC5XXX_ICTL);
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sdma = (struct mpc5xxx_sdma *)(MPC5XXX_SDMA);
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/* Disable all interrupt sources. */
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out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
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out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
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out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
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out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
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intr_ctrl = in_be32(&intr->ctrl);
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intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
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0x00ff0000 | /* IRQ 0-3 level sensitive low active */
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0x00001000 | /* MEE master external enable */
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0x00000000 | /* 0 means disable IRQ 0-3 */
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0x00000001; /* CEb route critical normally */
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out_be32(&intr->ctrl, intr_ctrl);
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/* Zero a bunch of the priority settings. */
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out_be32(&intr->per_pri1, 0);
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out_be32(&intr->per_pri2, 0);
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out_be32(&intr->per_pri3, 0);
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out_be32(&intr->main_pri1, 0);
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out_be32(&intr->main_pri2, 0);
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}
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int mpc5xxx_get_irq(struct pt_regs *regs)
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{
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u32 status;
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int irq = -1;
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status = in_be32(&intr->enc_status);
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if (status & 0x00000400) { /* critical */
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irq = (status >> 8) & 0x3;
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if (irq == 2) /* high priority peripheral */
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goto peripheral;
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irq += MPC5XXX_CRIT_IRQ_BASE;
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} else if (status & 0x00200000) { /* main */
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irq = (status >> 16) & 0x1f;
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if (irq == 4) /* low priority peripheral */
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goto peripheral;
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irq += MPC5XXX_MAIN_IRQ_BASE;
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} else if (status & 0x20000000) { /* peripheral */
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peripheral:
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irq = (status >> 24) & 0x1f;
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if (irq == 0) { /* bestcomm */
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status = in_be32(&sdma->IntPend);
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irq = ffs(status) + MPC5XXX_SDMA_IRQ_BASE - 1;
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} else
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irq += MPC5XXX_PERP_IRQ_BASE;
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}
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return irq;
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}
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/****************************************************************************/
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int interrupt_init_cpu(ulong * decrementer_count)
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{
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*decrementer_count = get_tbclk() / CFG_HZ;
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mpc5xxx_init_irq();
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return (0);
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}
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@ -44,14 +241,32 @@ int interrupt_init_cpu (ulong *decrementer_count)
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/*
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* Handle external interrupts
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*/
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void
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external_interrupt(struct pt_regs *regs)
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void external_interrupt(struct pt_regs *regs)
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{
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puts("external_interrupt (oops!)\n");
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int irq, unmask = 1;
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irq = mpc5xxx_get_irq(regs);
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mpc5xxx_ic_disable_and_ack(irq);
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enable_interrupts();
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if (irq_handlers[irq].handler != NULL)
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(*irq_handlers[irq].handler) (irq_handlers[irq].arg);
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else {
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printf("\nBogus External Interrupt IRQ %d\n", irq);
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/*
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* turn off the bogus interrupt, otherwise it
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* might repeat forever
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*/
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unmask = 0;
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}
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if (unmask)
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mpc5xxx_ic_end(irq);
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}
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void
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timer_interrupt_cpu (struct pt_regs *regs)
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void timer_interrupt_cpu(struct pt_regs *regs)
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{
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/* nothing to do here */
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return;
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@ -63,22 +278,69 @@ timer_interrupt_cpu (struct pt_regs *regs)
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* Install and free a interrupt handler.
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*/
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void
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irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
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void irq_install_handler(int irq, interrupt_handler_t * handler, void *arg)
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{
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if (irq < 0 || irq >= NR_IRQS) {
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printf("irq_install_handler: bad irq number %d\n", irq);
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return;
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}
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if (irq_handlers[irq].handler != NULL)
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printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
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(ulong) handler, (ulong) irq_handlers[irq].handler);
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irq_handlers[irq].handler = handler;
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irq_handlers[irq].arg = arg;
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mpc5xxx_ic_enable(irq);
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}
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void
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irq_free_handler(int vec)
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void irq_free_handler(int irq)
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{
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if (irq < 0 || irq >= NR_IRQS) {
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printf("irq_free_handler: bad irq number %d\n", irq);
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return;
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}
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mpc5xxx_ic_disable(irq);
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irq_handlers[irq].handler = NULL;
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irq_handlers[irq].arg = NULL;
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}
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/****************************************************************************/
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void
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do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
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#if (CONFIG_COMMANDS & CFG_CMD_IRQ)
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void do_irqinfo(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
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{
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puts("IRQ related functions are unimplemented currently.\n");
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int irq, re_enable;
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u32 intr_ctrl;
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char *irq_config[] = { "level sensitive, active high",
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"edge sensitive, rising active edge",
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"edge sensitive, falling active edge",
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"level sensitive, active low"
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};
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re_enable = disable_interrupts();
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intr_ctrl = in_be32(&intr->ctrl);
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printf("Interrupt configuration:\n");
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for (irq = 0; irq <= 3; irq++) {
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printf("IRQ%d: %s\n", irq,
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irq_config[(intr_ctrl >> (22 - 2 * irq)) & 0x3]);
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}
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puts("\nInterrupt-Information:\n" "Nr Routine Arg Count\n");
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for (irq = 0; irq < NR_IRQS; irq++)
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if (irq_handlers[irq].handler != NULL)
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printf("%02d %08lx %08lx %ld\n", irq,
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(ulong) irq_handlers[irq].handler,
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(ulong) irq_handlers[irq].arg,
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irq_handlers[irq].count);
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if (re_enable)
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enable_interrupts();
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}
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#endif
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@ -109,6 +109,12 @@ typedef volatile unsigned char vu_char;
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#define debugX(level,fmt,args...)
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#endif /* DEBUG */
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#define BUG() do { \
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printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \
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panic("BUG!"); \
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} while (0)
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#define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0)
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typedef void (interrupt_handler_t)(void *);
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#include <asm/u-boot.h> /* boot information for Linux kernel */
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@ -232,6 +232,65 @@
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#define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030)
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#define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038)
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#define NR_IRQS 64
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/* IRQ mapping - these are our logical IRQ numbers */
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#define MPC5XXX_CRIT_IRQ_NUM 4
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#define MPC5XXX_MAIN_IRQ_NUM 17
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#define MPC5XXX_SDMA_IRQ_NUM 17
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#define MPC5XXX_PERP_IRQ_NUM 23
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#define MPC5XXX_CRIT_IRQ_BASE 1
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#define MPC5XXX_MAIN_IRQ_BASE (MPC5XXX_CRIT_IRQ_BASE + MPC5XXX_CRIT_IRQ_NUM)
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#define MPC5XXX_SDMA_IRQ_BASE (MPC5XXX_MAIN_IRQ_BASE + MPC5XXX_MAIN_IRQ_NUM)
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#define MPC5XXX_PERP_IRQ_BASE (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)
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#define MPC5XXX_IRQ0 (MPC5XXX_CRIT_IRQ_BASE + 0)
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#define MPC5XXX_SLICE_TIMER_0_IRQ (MPC5XXX_CRIT_IRQ_BASE + 1)
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#define MPC5XXX_HI_INT_IRQ (MPC5XXX_CRIT_IRQ_BASE + 2)
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#define MPC5XXX_CCS_IRQ (MPC5XXX_CRIT_IRQ_BASE + 3)
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#define MPC5XXX_IRQ1 (MPC5XXX_MAIN_IRQ_BASE + 1)
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#define MPC5XXX_IRQ2 (MPC5XXX_MAIN_IRQ_BASE + 2)
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#define MPC5XXX_IRQ3 (MPC5XXX_MAIN_IRQ_BASE + 3)
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#define MPC5XXX_RTC_PINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 5)
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#define MPC5XXX_RTC_SINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 6)
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#define MPC5XXX_RTC_GPIO_STD_IRQ (MPC5XXX_MAIN_IRQ_BASE + 7)
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#define MPC5XXX_RTC_GPIO_WKUP_IRQ (MPC5XXX_MAIN_IRQ_BASE + 8)
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#define MPC5XXX_TMR0_IRQ (MPC5XXX_MAIN_IRQ_BASE + 9)
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#define MPC5XXX_TMR1_IRQ (MPC5XXX_MAIN_IRQ_BASE + 10)
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#define MPC5XXX_TMR2_IRQ (MPC5XXX_MAIN_IRQ_BASE + 11)
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#define MPC5XXX_TMR3_IRQ (MPC5XXX_MAIN_IRQ_BASE + 12)
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#define MPC5XXX_TMR4_IRQ (MPC5XXX_MAIN_IRQ_BASE + 13)
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#define MPC5XXX_TMR5_IRQ (MPC5XXX_MAIN_IRQ_BASE + 14)
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#define MPC5XXX_TMR6_IRQ (MPC5XXX_MAIN_IRQ_BASE + 15)
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#define MPC5XXX_TMR7_IRQ (MPC5XXX_MAIN_IRQ_BASE + 16)
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#define MPC5XXX_SDMA_IRQ (MPC5XXX_PERP_IRQ_BASE + 0)
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#define MPC5XXX_PSC1_IRQ (MPC5XXX_PERP_IRQ_BASE + 1)
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#define MPC5XXX_PSC2_IRQ (MPC5XXX_PERP_IRQ_BASE + 2)
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#define MPC5XXX_PSC3_IRQ (MPC5XXX_PERP_IRQ_BASE + 3)
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#define MPC5XXX_PSC6_IRQ (MPC5XXX_PERP_IRQ_BASE + 4)
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#define MPC5XXX_IRDA_IRQ (MPC5XXX_PERP_IRQ_BASE + 4)
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#define MPC5XXX_FEC_IRQ (MPC5XXX_PERP_IRQ_BASE + 5)
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#define MPC5XXX_USB_IRQ (MPC5XXX_PERP_IRQ_BASE + 6)
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#define MPC5XXX_ATA_IRQ (MPC5XXX_PERP_IRQ_BASE + 7)
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#define MPC5XXX_PCI_CNTRL_IRQ (MPC5XXX_PERP_IRQ_BASE + 8)
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#define MPC5XXX_PCI_SCIRX_IRQ (MPC5XXX_PERP_IRQ_BASE + 9)
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#define MPC5XXX_PCI_SCITX_IRQ (MPC5XXX_PERP_IRQ_BASE + 10)
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#define MPC5XXX_PSC4_IRQ (MPC5XXX_PERP_IRQ_BASE + 11)
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#define MPC5XXX_PSC5_IRQ (MPC5XXX_PERP_IRQ_BASE + 12)
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#define MPC5XXX_SPI_MODF_IRQ (MPC5XXX_PERP_IRQ_BASE + 13)
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#define MPC5XXX_SPI_SPIF_IRQ (MPC5XXX_PERP_IRQ_BASE + 14)
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#define MPC5XXX_I2C1_IRQ (MPC5XXX_PERP_IRQ_BASE + 15)
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#define MPC5XXX_I2C2_IRQ (MPC5XXX_PERP_IRQ_BASE + 16)
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#define MPC5XXX_MSCAN1_IRQ (MPC5XXX_PERP_IRQ_BASE + 17)
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#define MPC5XXX_MSCAN2_IRQ (MPC5XXX_PERP_IRQ_BASE + 18)
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#define MPC5XXX_IR_RX_IRQ (MPC5XXX_PERP_IRQ_BASE + 19)
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#define MPC5XXX_IR_TX_IRQ (MPC5XXX_PERP_IRQ_BASE + 20)
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#define MPC5XXX_XLB_ARB_IRQ (MPC5XXX_PERP_IRQ_BASE + 21)
|
||||
#define MPC5XXX_BDLC_IRQ (MPC5XXX_PERP_IRQ_BASE + 22)
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||||
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||||
/* General Purpose Timers registers */
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||||
#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
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||||
#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue