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https://github.com/Fishwaldo/u-boot.git
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MIPS: add support for Broadcom MIPS BCM6368 SoC family
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This commit is contained in:
Álvaro Fernández Rojas
Daniel Schwierzeck
parent
8c8ef2e825
commit
43b7ab99ec
5 changed files with 263 additions and 0 deletions
168
arch/mips/dts/brcm,bcm6368.dtsi
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168
arch/mips/dts/brcm,bcm6368.dtsi
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/*
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* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <dt-bindings/clock/bcm6368-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/reset/bcm6368-reset.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "brcm,bcm6368";
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aliases {
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spi0 = &spi;
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};
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cpus {
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reg = <0x10000000 0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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u-boot,dm-pre-reloc;
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cpu@0 {
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compatible = "brcm,bcm6368-cpu", "mips,mips4Kc";
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device_type = "cpu";
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reg = <0>;
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u-boot,dm-pre-reloc;
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};
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cpu@1 {
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compatible = "brcm,bcm6368-cpu", "mips,mips4Kc";
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device_type = "cpu";
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reg = <1>;
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u-boot,dm-pre-reloc;
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};
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};
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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u-boot,dm-pre-reloc;
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periph_osc: periph-osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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u-boot,dm-pre-reloc;
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};
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periph_clk: periph-clk {
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compatible = "brcm,bcm6345-clk";
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reg = <0x10000004 0x4>;
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#clock-cells = <1>;
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};
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};
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pflash: nor@18000000 {
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compatible = "cfi-flash";
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reg = <0x18000000 0x2000000>;
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bank-width = <2>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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};
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ubus {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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u-boot,dm-pre-reloc;
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pll_cntl: syscon@10000008 {
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compatible = "syscon";
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reg = <0x10000008 0x4>;
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};
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syscon-reboot {
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compatible = "syscon-reboot";
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regmap = <&pll_cntl>;
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offset = <0x0>;
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mask = <0x1>;
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};
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periph_rst: reset-controller@10000010 {
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compatible = "brcm,bcm6345-reset";
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reg = <0x10000010 0x4>;
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#reset-cells = <1>;
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};
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wdt: watchdog@1000005c {
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compatible = "brcm,bcm6345-wdt";
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reg = <0x1000005c 0xc>;
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clocks = <&periph_osc>;
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};
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdt>;
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};
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gpio1: gpio-controller@10000080 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x10000080 0x4>, <0x10000088 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <6>;
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status = "disabled";
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};
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gpio0: gpio-controller@10000084 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x10000084 0x4>, <0x1000008c 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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leds: led-controller@100000d0 {
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compatible = "brcm,bcm6358-leds";
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reg = <0x100000d0 0x8>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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uart0: serial@10000100 {
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compatible = "brcm,bcm6345-uart";
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reg = <0x10000100 0x18>;
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clocks = <&periph_osc>;
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status = "disabled";
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};
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uart1: serial@10000120 {
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compatible = "brcm,bcm6345-uart";
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reg = <0x10000120 0x18>;
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clocks = <&periph_osc>;
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status = "disabled";
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};
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spi: spi@10000800 {
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compatible = "brcm,bcm6358-spi";
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reg = <0x10000800 0x70c>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&periph_clk BCM6368_CLK_SPI>;
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resets = <&periph_rst BCM6368_RST_SPI>;
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spi-max-frequency = <20000000>;
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num-cs = <6>;
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status = "disabled";
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};
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memory-controller@10001200 {
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compatible = "brcm,bcm6358-mc";
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reg = <0x10001200 0x4c>;
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u-boot,dm-pre-reloc;
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};
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};
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};
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@ -10,6 +10,7 @@ config SYS_SOC
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default "bcm6338" if SOC_BMIPS_BCM6338
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default "bcm6348" if SOC_BMIPS_BCM6348
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default "bcm6358" if SOC_BMIPS_BCM6358
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default "bcm6368" if SOC_BMIPS_BCM6368
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default "bcm63268" if SOC_BMIPS_BCM63268
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choice
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@ -70,6 +71,17 @@ config SOC_BMIPS_BCM6358
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help
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This supports BMIPS BCM6358 family including BCM6358 and BCM6359.
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config SOC_BMIPS_BCM6368
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bool "BMIPS BCM6368 family"
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select SUPPORTS_BIG_ENDIAN
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select SUPPORTS_CPU_MIPS32_R1
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select MIPS_TUNE_4KC
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select MIPS_L1_CACHE_SHIFT_4
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select SWAP_IO_SPACE
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select SYSRESET_SYSCON
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help
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This supports BMIPS BCM6368 family including BCM6368 and BCM6369.
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config SOC_BMIPS_BCM63268
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bool "BMIPS BCM63268 family"
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select SUPPORTS_BIG_ENDIAN
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30
include/configs/bmips_bcm6368.h
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30
include/configs/bmips_bcm6368.h
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/*
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* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_BMIPS_BCM6368_H
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#define __CONFIG_BMIPS_BCM6368_H
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/* CPU */
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#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000
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/* RAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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/* U-Boot */
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#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
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#if defined(CONFIG_BMIPS_BOOT_RAM)
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_INIT_SP_OFFSET 0x2000
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#endif
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#define CONFIG_SYS_FLASH_BASE 0xb8000000
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
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#endif /* __CONFIG_BMIPS_BCM6368_H */
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31
include/dt-bindings/clock/bcm6368-clock.h
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31
include/dt-bindings/clock/bcm6368-clock.h
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/*
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* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DT_BINDINGS_CLOCK_BCM6368_H
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#define __DT_BINDINGS_CLOCK_BCM6368_H
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#define BCM6368_CLK_VDSL_QPROC 2
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#define BCM6368_CLK_VDSL_AFE 3
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#define BCM6368_CLK_VDSL_BONDING 4
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#define BCM6368_CLK_VDSL 5
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#define BCM6368_CLK_PHYMIPS 6
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#define BCM6368_CLK_SWPKT_USB 7
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#define BCM6368_CLK_SWPKT_SAR 8
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#define BCM6368_CLK_SPI 9
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#define BCM6368_CLK_USBD 10
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#define BCM6368_CLK_SAR 11
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#define BCM6368_CLK_ROBOSW 12
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#define BCM6368_CLK_UTOPIA 13
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#define BCM6368_CLK_PCM 14
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#define BCM6368_CLK_USBH 15
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#define BCM6368_CLK_GLESS 16
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#define BCM6368_CLK_NAND 17
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#define BCM6368_CLK_IPSEC 18
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#define BCM6368_CLK_USBH_IDDQ 19
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#endif /* __DT_BINDINGS_CLOCK_BCM6368_H */
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22
include/dt-bindings/reset/bcm6368-reset.h
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22
include/dt-bindings/reset/bcm6368-reset.h
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/*
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* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DT_BINDINGS_RESET_BCM6368_H
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#define __DT_BINDINGS_RESET_BCM6368_H
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#define BCM6368_RST_SPI 0
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#define BCM6368_RST_MPI 3
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#define BCM6368_RST_IPSEC 4
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#define BCM6368_RST_EPHY 6
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#define BCM6368_RST_SAR 7
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#define BCM6368_RST_SWITCH 10
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#define BCM6368_RST_USBD 11
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#define BCM6368_RST_USBH 12
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#define BCM6368_RST_PCM 13
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#endif /* __DT_BINDINGS_RESET_BCM6368_H */
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