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Merge branch 'master' of git://git.denx.de/u-boot-spi

Browse source
This commit is contained in:
Tom Rini 2015-10-28 16:56:43 -04:00
commit 446d37c1ac
40 changed files with 1100 additions and 365 deletions
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12
arch/arm/dts/zynq-7000.dtsi
View file

@ -191,6 +191,18 @@
#size-cells = <0>;
};
qspi: spi@e000d000 {
clock-names = "ref_clk", "pclk";
clocks = <&clkc 10>, <&clkc 43>;
compatible = "xlnx,zynq-qspi-1.0";
status = "disabled";
interrupt-parent = <&intc>;
interrupts = <0 19 4>;
reg = <0xe000d000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
};
gem0: ethernet@e000b000 {
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000b000 0x1000>;

5
arch/arm/dts/zynq-microzed.dts
View file

@ -14,6 +14,7 @@
aliases {
serial0 = &uart1;
spi0 = &qspi;
};
memory {
@ -21,3 +22,7 @@
reg = <0 0x40000000>;
};
};
&qspi {
status = "okay";
};

5
arch/arm/dts/zynq-zc702.dts
View file

@ -17,6 +17,7 @@
ethernet0 = &gem0;
i2c0 = &i2c0;
serial0 = &uart1;
spi0 = &qspi;
};
memory {
@ -380,6 +381,10 @@
pinctrl-0 = <&pinctrl_uart1_default>;
};
&qspi {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";

5
arch/arm/dts/zynq-zc706.dts
View file

@ -17,6 +17,7 @@
ethernet0 = &gem0;
i2c0 = &i2c0;
serial0 = &uart1;
spi0 = &qspi;
};
memory {
@ -301,6 +302,10 @@
pinctrl-0 = <&pinctrl_uart1_default>;
};
&qspi {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";

7
arch/arm/dts/zynq-zc770-xm010.dts
View file

@ -16,7 +16,8 @@
ethernet0 = &gem0;
i2c0 = &i2c0;
serial0 = &uart1;
spi0 = &spi1;
spi0 = &qspi;
spi1 = &spi1;
};
chosen {
@ -53,6 +54,10 @@
};
};
&qspi {
status = "okay";
};
&can0 {
status = "okay";
};

5
arch/arm/dts/zynq-zed.dts
View file

@ -16,6 +16,7 @@
aliases {
ethernet0 = &gem0;
serial0 = &uart1;
spi0 = &qspi;
};
memory {
@ -56,6 +57,10 @@
status = "okay";
};
&qspi {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";

2
configs/zynq_microzed_defconfig
View file

@ -11,3 +11,5 @@ CONFIG_FIT_SIGNATURE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
CONFIG_ZYNQ_QSPI=y

2
configs/zynq_zc702_defconfig
View file

@ -10,3 +10,5 @@ CONFIG_FIT_SIGNATURE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
CONFIG_ZYNQ_QSPI=y

2
configs/zynq_zc706_defconfig
View file

@ -11,3 +11,5 @@ CONFIG_FIT_SIGNATURE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
CONFIG_ZYNQ_QSPI=y

2
configs/zynq_zc70x_defconfig
View file

@ -11,3 +11,5 @@ CONFIG_FIT_SIGNATURE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
CONFIG_ZYNQ_QSPI=y

1
configs/zynq_zc770_xm010_defconfig
View file

@ -13,3 +13,4 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010"
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
CONFIG_ZYNQ_QSPI=y

2
configs/zynq_zed_defconfig
View file

@ -11,3 +11,5 @@ CONFIG_FIT_SIGNATURE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
CONFIG_ZYNQ_QSPI=y

26
doc/device-tree-bindings/spi/spi-zynq-qspi.txt Normal file
View file

@ -0,0 +1,26 @@
Xilinx Zynq QSPI controller Device Tree Bindings
-------------------------------------------------
Required properties:
- compatible : Should be "xlnx,zynq-qspi-1.0".
- reg : Physical base address and size of QSPI registers map.
- interrupts : Property with a value describing the interrupt
number.
- interrupt-parent : Must be core interrupt controller
- clock-names : List of input clock names - "ref_clk", "pclk"
(See clock bindings for details).
- clocks : Clock phandles (see clock bindings for details).
Optional properties:
- num-cs : Number of chip selects used.
Example:
qspi@e000d000 {
compatible = "xlnx,zynq-qspi-1.0";
clock-names = "ref_clk", "pclk";
clocks = <&clkc 10>, <&clkc 43>;
interrupt-parent = <&intc>;
interrupts = <0 19 4>;
num-cs = <1>;
reg = <0xe000d000 0x1000>;
} ;

5
drivers/mtd/spi/sf_internal.h
View file

@ -51,6 +51,11 @@ enum {
#define SST_WR (SST_BP | SST_WP)
enum spi_nor_option_flags {
SNOR_F_SST_WR = (1 << 0),
SNOR_F_USE_FSR = (1 << 1),
};
#define SPI_FLASH_3B_ADDR_LEN 3
#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
#define SPI_FLASH_16MB_BOUN 0x1000000

150
drivers/mtd/spi/sf_ops.c
View file

@ -41,6 +41,20 @@ int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs)
return 0;
}
static int read_fsr(struct spi_flash *flash, u8 *fsr)
{
int ret;
const u8 cmd = CMD_FLAG_STATUS;
ret = spi_flash_read_common(flash, &cmd, 1, fsr, 1);
if (ret < 0) {
debug("SF: fail to read flag status register\n");
return ret;
}
return 0;
}
int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws)
{
u8 cmd;
@ -95,15 +109,14 @@ int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc)
#endif
#ifdef CONFIG_SPI_FLASH_BAR
static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
static int spi_flash_write_bank(struct spi_flash *flash, u32 offset)
{
u8 cmd;
u8 cmd, bank_sel;
int ret;
if (flash->bank_curr == bank_sel) {
debug("SF: not require to enable bank%d\n", bank_sel);
return 0;
}
bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift);
if (bank_sel == flash->bank_curr)
goto bar_end;
cmd = flash->bank_write_cmd;
ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
@ -111,25 +124,10 @@ static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
debug("SF: fail to write bank register\n");
return ret;
}
bar_end:
flash->bank_curr = bank_sel;
return 0;
}
static int spi_flash_bank(struct spi_flash *flash, u32 offset)
{
u8 bank_sel;
int ret;
bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift);
ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
if (ret) {
debug("SF: fail to set bank%d\n", bank_sel);
return ret;
}
return bank_sel;
return flash->bank_curr;
}
#endif
@ -155,72 +153,65 @@ static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr)
}
#endif
static int spi_flash_poll_status(struct spi_slave *spi, unsigned long timeout,
u8 cmd, u8 poll_bit)
static int spi_flash_sr_ready(struct spi_flash *flash)
{
unsigned long timebase;
unsigned long flags = SPI_XFER_BEGIN;
u8 sr;
int ret;
u8 status;
u8 check_status = 0x0;
if (cmd == CMD_FLAG_STATUS)
check_status = poll_bit;
#ifdef CONFIG_SF_DUAL_FLASH
if (spi->flags & SPI_XFER_U_PAGE)
flags |= SPI_XFER_U_PAGE;
#endif
ret = spi_xfer(spi, 8, &cmd, NULL, flags);
if (ret) {
debug("SF: fail to read %s status register\n",
cmd == CMD_READ_STATUS ? "read" : "flag");
ret = spi_flash_cmd_read_status(flash, &sr);
if (ret < 0)
return ret;
return !(sr & STATUS_WIP);
}
static int spi_flash_fsr_ready(struct spi_flash *flash)
{
u8 fsr;
int ret;
ret = read_fsr(flash, &fsr);
if (ret < 0)
return ret;
return fsr & STATUS_PEC;
}
static int spi_flash_ready(struct spi_flash *flash)
{
int sr, fsr;
sr = spi_flash_sr_ready(flash);
if (sr < 0)
return sr;
fsr = 1;
if (flash->flags & SNOR_F_USE_FSR) {
fsr = spi_flash_fsr_ready(flash);
if (fsr < 0)
return fsr;
}
timebase = get_timer(0);
do {
WATCHDOG_RESET();
ret = spi_xfer(spi, 8, NULL, &status, 0);
if (ret)
return -1;
if ((status & poll_bit) == check_status)
break;
} while (get_timer(timebase) < timeout);
spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
if ((status & poll_bit) == check_status)
return 0;
/* Timed out */
debug("SF: time out!\n");
return -1;
return sr && fsr;
}
int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
{
struct spi_slave *spi = flash->spi;
int ret;
u8 poll_bit = STATUS_WIP;
u8 cmd = CMD_READ_STATUS;
int timebase, ret;
ret = spi_flash_poll_status(spi, timeout, cmd, poll_bit);
if (ret < 0)
return ret;
if (flash->poll_cmd == CMD_FLAG_STATUS) {
poll_bit = STATUS_PEC;
cmd = CMD_FLAG_STATUS;
ret = spi_flash_poll_status(spi, timeout, cmd, poll_bit);
timebase = get_timer(0);
while (get_timer(timebase) < timeout) {
ret = spi_flash_ready(flash);
if (ret < 0)
return ret;
if (ret)
return 0;
}
return 0;
printf("SF: Timeout!\n");
return -ETIMEDOUT;
}
int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
@ -285,7 +276,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
spi_flash_dual_flash(flash, &erase_addr);
#endif
#ifdef CONFIG_SPI_FLASH_BAR
ret = spi_flash_bank(flash, erase_addr);
ret = spi_flash_write_bank(flash, erase_addr);
if (ret < 0)
return ret;
#endif
@ -327,7 +318,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
spi_flash_dual_flash(flash, &write_addr);
#endif
#ifdef CONFIG_SPI_FLASH_BAR
ret = spi_flash_bank(flash, write_addr);
ret = spi_flash_write_bank(flash, write_addr);
if (ret < 0)
return ret;
#endif
@ -422,9 +413,10 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
spi_flash_dual_flash(flash, &read_addr);
#endif
#ifdef CONFIG_SPI_FLASH_BAR
bank_sel = spi_flash_bank(flash, read_addr);
if (bank_sel < 0)
ret = spi_flash_write_bank(flash, read_addr);
if (ret < 0)
return ret;
bank_sel = flash->bank_curr;
#endif
remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
(bank_sel + 1)) - offset;

5
drivers/mtd/spi/sf_params.c
View file

@ -35,6 +35,11 @@ const struct spi_flash_params spi_flash_params_table[] = {
{"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
{"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
{"IS25LP032", 0x9d6016, 0x0, 64 * 1024, 64, RD_NORM, 0},
{"IS25LP064", 0x9d6017, 0x0, 64 * 1024, 128, RD_NORM, 0},
{"IS25LP128", 0x9d6018, 0x0, 64 * 1024, 256, RD_NORM, 0},
#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
{"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, RD_NORM, 0},
{"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, RD_NORM, 0},

65
drivers/mtd/spi/sf_probe.c
View file

@ -99,6 +99,37 @@ static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
}
}
#ifdef CONFIG_SPI_FLASH_BAR
static int spi_flash_read_bank(struct spi_flash *flash, u8 idcode0)
{
u8 curr_bank = 0;
int ret;
if (flash->size <= SPI_FLASH_16MB_BOUN)
goto bank_end;
switch (idcode0) {
case SPI_FLASH_CFI_MFR_SPANSION:
flash->bank_read_cmd = CMD_BANKADDR_BRRD;
flash->bank_write_cmd = CMD_BANKADDR_BRWR;
default:
flash->bank_read_cmd = CMD_EXTNADDR_RDEAR;
flash->bank_write_cmd = CMD_EXTNADDR_WREAR;
}
ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
&curr_bank, 1);
if (ret) {
debug("SF: fail to read bank addr register\n");
return ret;
}
bank_end:
flash->bank_curr = curr_bank;
return 0;
}
#endif
static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode,
struct spi_flash *flash)
{
@ -132,15 +163,15 @@ static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode,
flash->name = params->name;
flash->memory_map = spi->memory_map;
flash->dual_flash = flash->spi->option;
#ifdef CONFIG_DM_SPI_FLASH
flash->flags = params->flags;
#endif
/* Assign spi_flash ops */
#ifndef CONFIG_DM_SPI_FLASH
flash->write = spi_flash_cmd_write_ops;
#if defined(CONFIG_SPI_FLASH_SST)
if (params->flags & SST_WR) {
if (params->flags & SST_WR)
flash->flags |= SNOR_F_SST_WR;
if (params->flags & SNOR_F_SST_WR) {
if (flash->spi->op_mode_tx & SPI_OPM_TX_BP)
flash->write = sst_write_bp;
else
@ -226,34 +257,16 @@ static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode,
flash->dummy_byte = 1;
}
/* Poll cmd selection */
flash->poll_cmd = CMD_READ_STATUS;
#ifdef CONFIG_SPI_FLASH_STMICRO
if (params->flags & E_FSR)
flash->poll_cmd = CMD_FLAG_STATUS;
flash->flags |= SNOR_F_USE_FSR;
#endif
/* Configure the BAR - discover bank cmds and read current bank */
#ifdef CONFIG_SPI_FLASH_BAR
u8 curr_bank = 0;
if (flash->size > SPI_FLASH_16MB_BOUN) {
int ret;
flash->bank_read_cmd = (idcode[0] == 0x01) ?
CMD_BANKADDR_BRRD : CMD_EXTNADDR_RDEAR;
flash->bank_write_cmd = (idcode[0] == 0x01) ?
CMD_BANKADDR_BRWR : CMD_EXTNADDR_WREAR;
ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
&curr_bank, 1);
if (ret) {
debug("SF: fail to read bank addr register\n");
int ret = spi_flash_read_bank(flash, idcode[0]);
if (ret < 0)
return ret;
}
flash->bank_curr = curr_bank;
} else {
flash->bank_curr = curr_bank;
}
#endif
/* Flash powers up read-only, so clear BP# bits */
@ -451,7 +464,7 @@ int spi_flash_std_write(struct udevice *dev, u32 offset, size_t len,
struct spi_flash *flash = dev_get_uclass_priv(dev);
#if defined(CONFIG_SPI_FLASH_SST)
if (flash->flags & SST_WR) {
if (flash->flags & SNOR_F_SST_WR) {
if (flash->spi->op_mode_tx & SPI_OPM_TX_BP)
return sst_write_bp(flash, offset, len, buf);
else

9
drivers/spi/Kconfig
View file

@ -139,6 +139,15 @@ config ZYNQ_SPI
access the SPI NOR flash on platforms embedding this Zynq
SPI IP core.
config ZYNQ_QSPI
bool "Zynq QSPI driver"
depends on ARCH_ZYNQ
help
Enable the Zynq Quad-SPI (QSPI) driver. This driver can be
used to access the SPI NOR flash on platforms embedding this
Zynq QSPI IP core. This IP is used to connect the flash in
4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel.
endif # if DM_SPI
config FSL_ESPI

1
drivers/spi/Makefile
View file

@ -49,3 +49,4 @@ obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
obj-$(CONFIG_TI_QSPI) += ti_qspi.o
obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o

8
drivers/spi/altera_spi.c
View file

@ -11,12 +11,15 @@
#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <spi.h>
#include <fdtdec.h>
#include <spi.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
#define ALTERA_SPI_STATUS_RRDY_MSK BIT(7)
#define ALTERA_SPI_CONTROL_SSO_MSK BIT(10)
#ifndef CONFIG_ALTERA_SPI_IDLE_VAL
#define CONFIG_ALTERA_SPI_IDLE_VAL 0xff
#endif
@ -38,9 +41,6 @@ struct altera_spi_priv {
struct altera_spi_regs *regs;
};
#define ALTERA_SPI_STATUS_RRDY_MSK (1 << 7)
#define ALTERA_SPI_CONTROL_SSO_MSK (1 << 10)
static void spi_cs_activate(struct udevice *dev, uint cs)
{
struct udevice *bus = dev->parent;

54
drivers/spi/atmel_spi.h
View file

@ -15,19 +15,19 @@
#define ATMEL_SPI_VERSION 0x00fc
/* Bits in CR */
#define ATMEL_SPI_CR_SPIEN (1 << 0)
#define ATMEL_SPI_CR_SPIDIS (1 << 1)
#define ATMEL_SPI_CR_SWRST (1 << 7)
#define ATMEL_SPI_CR_LASTXFER (1 << 24)
#define ATMEL_SPI_CR_SPIEN BIT(0)
#define ATMEL_SPI_CR_SPIDIS BIT(1)
#define ATMEL_SPI_CR_SWRST BIT(7)
#define ATMEL_SPI_CR_LASTXFER BIT(24)
/* Bits in MR */
#define ATMEL_SPI_MR_MSTR (1 << 0)
#define ATMEL_SPI_MR_PS (1 << 1)
#define ATMEL_SPI_MR_PCSDEC (1 << 2)
#define ATMEL_SPI_MR_FDIV (1 << 3)
#define ATMEL_SPI_MR_MODFDIS (1 << 4)
#define ATMEL_SPI_MR_WDRBT (1 << 5)
#define ATMEL_SPI_MR_LLB (1 << 7)
#define ATMEL_SPI_MR_MSTR BIT(0)
#define ATMEL_SPI_MR_PS BIT(1)
#define ATMEL_SPI_MR_PCSDEC BIT(2)
#define ATMEL_SPI_MR_FDIV BIT(3)
#define ATMEL_SPI_MR_MODFDIS BIT(4)
#define ATMEL_SPI_MR_WDRBT BIT(5)
#define ATMEL_SPI_MR_LLB BIT(7)
#define ATMEL_SPI_MR_PCS(x) (((x) & 15) << 16)
#define ATMEL_SPI_MR_DLYBCS(x) ((x) << 24)
@ -38,28 +38,28 @@
/* Bits in TDR */
#define ATMEL_SPI_TDR_TD(x) (x)
#define ATMEL_SPI_TDR_PCS(x) ((x) << 16)
#define ATMEL_SPI_TDR_LASTXFER (1 << 24)
#define ATMEL_SPI_TDR_LASTXFER BIT(24)
/* Bits in SR/IER/IDR/IMR */
#define ATMEL_SPI_SR_RDRF (1 << 0)
#define ATMEL_SPI_SR_TDRE (1 << 1)
#define ATMEL_SPI_SR_MODF (1 << 2)
#define ATMEL_SPI_SR_OVRES (1 << 3)
#define ATMEL_SPI_SR_ENDRX (1 << 4)
#define ATMEL_SPI_SR_ENDTX (1 << 5)
#define ATMEL_SPI_SR_RXBUFF (1 << 6)
#define ATMEL_SPI_SR_TXBUFE (1 << 7)
#define ATMEL_SPI_SR_NSSR (1 << 8)
#define ATMEL_SPI_SR_TXEMPTY (1 << 9)
#define ATMEL_SPI_SR_SPIENS (1 << 16)
#define ATMEL_SPI_SR_RDRF BIT(0)
#define ATMEL_SPI_SR_TDRE BIT(1)
#define ATMEL_SPI_SR_MODF BIT(2)
#define ATMEL_SPI_SR_OVRES BIT(3)
#define ATMEL_SPI_SR_ENDRX BIT(4)
#define ATMEL_SPI_SR_ENDTX BIT(5)
#define ATMEL_SPI_SR_RXBUFF BIT(6)
#define ATMEL_SPI_SR_TXBUFE BIT(7)
#define ATMEL_SPI_SR_NSSR BIT(8)
#define ATMEL_SPI_SR_TXEMPTY BIT(9)
#define ATMEL_SPI_SR_SPIENS BIT(16)
/* Bits in CSRx */
#define ATMEL_SPI_CSRx_CPOL (1 << 0)
#define ATMEL_SPI_CSRx_NCPHA (1 << 1)
#define ATMEL_SPI_CSRx_CSAAT (1 << 3)
#define ATMEL_SPI_CSRx_CPOL BIT(0)
#define ATMEL_SPI_CSRx_NCPHA BIT(1)
#define ATMEL_SPI_CSRx_CSAAT BIT(3)
#define ATMEL_SPI_CSRx_BITS(x) ((x) << 4)
#define ATMEL_SPI_CSRx_SCBR(x) ((x) << 8)
#define ATMEL_SPI_CSRx_SCBR_MAX 0xff
#define ATMEL_SPI_CSRx_SCBR_MAX GENMASK(7, 0)
#define ATMEL_SPI_CSRx_DLYBS(x) ((x) << 16)
#define ATMEL_SPI_CSRx_DLYBCT(x) ((x) << 24)

8
drivers/spi/bfin_spi6xx.c
View file

@ -63,9 +63,9 @@ void spi_cs_activate(struct spi_slave *slave)
ssel = bfin_read32(&bss->regs->ssel);
ssel |= 1 << slave->cs;
if (bss->cs_pol)
ssel |= (1 << 8) << slave->cs;
ssel |= BIT(8) << slave->cs;
else
ssel &= ~((1 << 8) << slave->cs);
ssel &= ~(BIT(8) << slave->cs);
bfin_write32(&bss->regs->ssel, ssel);
}
@ -83,9 +83,9 @@ void spi_cs_deactivate(struct spi_slave *slave)
u32 ssel;
ssel = bfin_read32(&bss->regs->ssel);
if (bss->cs_pol)
ssel &= ~((1 << 8) << slave->cs);
ssel &= ~(BIT(8) << slave->cs);
else
ssel |= (1 << 8) << slave->cs;
ssel |= BIT(8) << slave->cs;
/* deassert cs */
bfin_write32(&bss->regs->ssel, ssel);
SSYNC();

28
drivers/spi/cadence_qspi_apb.c
View file

@ -58,10 +58,10 @@
#define CQSPI_REG_CONFIG 0x00
#define CQSPI_REG_CONFIG_CLK_POL_LSB 1
#define CQSPI_REG_CONFIG_CLK_PHA_LSB 2
#define CQSPI_REG_CONFIG_ENABLE_MASK (1 << 0)
#define CQSPI_REG_CONFIG_DIRECT_MASK (1 << 7)
#define CQSPI_REG_CONFIG_DECODE_MASK (1 << 9)
#define CQSPI_REG_CONFIG_XIP_IMM_MASK (1 << 18)
#define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0)
#define CQSPI_REG_CONFIG_DIRECT_MASK BIT(7)
#define CQSPI_REG_CONFIG_DECODE_MASK BIT(9)
#define CQSPI_REG_CONFIG_XIP_IMM_MASK BIT(18)
#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
#define CQSPI_REG_CONFIG_BAUD_LSB 19
#define CQSPI_REG_CONFIG_IDLE_LSB 31
@ -122,18 +122,18 @@
#define CQSPI_REG_IRQMASK 0x44
#define CQSPI_REG_INDIRECTRD 0x60
#define CQSPI_REG_INDIRECTRD_START_MASK (1 << 0)
#define CQSPI_REG_INDIRECTRD_CANCEL_MASK (1 << 1)
#define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK (1 << 2)
#define CQSPI_REG_INDIRECTRD_DONE_MASK (1 << 5)
#define CQSPI_REG_INDIRECTRD_START_MASK BIT(0)
#define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1)
#define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK BIT(2)
#define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5)
#define CQSPI_REG_INDIRECTRDWATERMARK 0x64
#define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
#define CQSPI_REG_INDIRECTRDBYTES 0x6C
#define CQSPI_REG_CMDCTRL 0x90
#define CQSPI_REG_CMDCTRL_EXECUTE_MASK (1 << 0)
#define CQSPI_REG_CMDCTRL_INPROGRESS_MASK (1 << 1)
#define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0)
#define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1)
#define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
#define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
@ -149,10 +149,10 @@
#define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF
#define CQSPI_REG_INDIRECTWR 0x70
#define CQSPI_REG_INDIRECTWR_START_MASK (1 << 0)
#define CQSPI_REG_INDIRECTWR_CANCEL_MASK (1 << 1)
#define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK (1 << 2)
#define CQSPI_REG_INDIRECTWR_DONE_MASK (1 << 5)
#define CQSPI_REG_INDIRECTWR_START_MASK BIT(0)
#define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1)
#define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK BIT(2)
#define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5)
#define CQSPI_REG_INDIRECTWRWATERMARK 0x74
#define CQSPI_REG_INDIRECTWRSTARTADDR 0x78

16
drivers/spi/designware_spi.c
View file

@ -74,14 +74,14 @@ DECLARE_GLOBAL_DATA_PTR;
#define SPI_CFS_OFFSET 12
/* Bit fields in SR, 7 bits */
#define SR_MASK 0x7f /* cover 7 bits */
#define SR_BUSY (1 << 0)
#define SR_TF_NOT_FULL (1 << 1)
#define SR_TF_EMPT (1 << 2)
#define SR_RF_NOT_EMPT (1 << 3)
#define SR_RF_FULL (1 << 4)
#define SR_TX_ERR (1 << 5)
#define SR_DCOL (1 << 6)
#define SR_MASK GENMASK(6, 0) /* cover 7 bits */
#define SR_BUSY BIT(0)
#define SR_TF_NOT_FULL BIT(1)
#define SR_TF_EMPT BIT(2)
#define SR_RF_NOT_EMPT BIT(3)
#define SR_RF_FULL BIT(4)
#define SR_TX_ERR BIT(5)
#define SR_DCOL BIT(6)
#define RX_TIMEOUT 1000 /* timeout in ms */

2
drivers/spi/fsl_dspi.c
View file

@ -24,7 +24,7 @@
DECLARE_GLOBAL_DATA_PTR;
/* fsl_dspi_platdata flags */
#define DSPI_FLAG_REGMAP_ENDIAN_BIG (1 << 0)
#define DSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0)
/* idle data value */
#define DSPI_IDLE_VAL 0x0

20
drivers/spi/fsl_espi.c
View file

@ -32,26 +32,26 @@ struct fsl_spi_slave {
#define ESPI_MAX_CS_NUM 4
#define ESPI_FIFO_WIDTH_BIT 32
#define ESPI_EV_RNE (1 << 9)
#define ESPI_EV_TNF (1 << 8)
#define ESPI_EV_DON (1 << 14)
#define ESPI_EV_TXE (1 << 15)
#define ESPI_EV_RNE BIT(9)
#define ESPI_EV_TNF BIT(8)
#define ESPI_EV_DON BIT(14)
#define ESPI_EV_TXE BIT(15)
#define ESPI_EV_RFCNT_SHIFT 24
#define ESPI_EV_RFCNT_MASK (0x3f << ESPI_EV_RFCNT_SHIFT)
#define ESPI_MODE_EN (1 << 31) /* Enable interface */
#define ESPI_MODE_EN BIT(31) /* Enable interface */
#define ESPI_MODE_TXTHR(x) ((x) << 8) /* Tx FIFO threshold */
#define ESPI_MODE_RXTHR(x) ((x) << 0) /* Rx FIFO threshold */
#define ESPI_COM_CS(x) ((x) << 30)
#define ESPI_COM_TRANLEN(x) ((x) << 0)
#define ESPI_CSMODE_CI_INACTIVEHIGH (1 << 31)
#define ESPI_CSMODE_CP_BEGIN_EDGCLK (1 << 30)
#define ESPI_CSMODE_REV_MSB_FIRST (1 << 29)
#define ESPI_CSMODE_DIV16 (1 << 28)
#define ESPI_CSMODE_CI_INACTIVEHIGH BIT(31)
#define ESPI_CSMODE_CP_BEGIN_EDGCLK BIT(30)
#define ESPI_CSMODE_REV_MSB_FIRST BIT(29)
#define ESPI_CSMODE_DIV16 BIT(28)
#define ESPI_CSMODE_PM(x) ((x) << 24)
#define ESPI_CSMODE_POL_ASSERTED_LOW (1 << 20)
#define ESPI_CSMODE_POL_ASSERTED_LOW BIT(20)
#define ESPI_CSMODE_LEN(x) ((x) << 16)
#define ESPI_CSMODE_CSBEF(x) ((x) << 12)
#define ESPI_CSMODE_CSAFT(x) ((x) << 8)

6
drivers/spi/fsl_qspi.c
View file

@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define TX_BUFFER_SIZE 0x40
#endif
#define OFFSET_BITS_MASK 0x00ffffff
#define OFFSET_BITS_MASK GENMASK(24, 0)
#define FLASH_STATUS_WEL 0x02
@ -68,7 +68,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define QSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */
/* fsl_qspi_platdata flags */
#define QSPI_FLAG_REGMAP_ENDIAN_BIG (1 << 0)
#define QSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0)
/* default SCK frequency, unit: HZ */
#define FSL_QSPI_DEFAULT_SCK_FREQ 50000000
@ -383,7 +383,7 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
/* Enable the module again (enable the DDR too) */
reg |= QSPI_MCR_DDR_EN_MASK;
/* Enable bit 29 for imx6sx */
reg |= (1 << 29);
reg |= BIT(29);
qspi_write32(priv->flags, &regs->mcr, reg);
}

4
drivers/spi/ich.c
View file

@ -692,13 +692,13 @@ static int ich_spi_probe(struct udevice *bus)
*/
if (plat->use_sbase) {
bios_cntl = ich_readb(priv, priv->bcr);
bios_cntl &= ~(1 << 5); /* clear Enable InSMM_STS (EISS) */
bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */
bios_cntl |= 1; /* Write Protect Disable (WPD) */
ich_writeb(priv, bios_cntl, priv->bcr);
} else {
pci_read_config_byte(plat->dev, 0xdc, &bios_cntl);
if (plat->ich_version == 9)
bios_cntl &= ~(1 << 5);
bios_cntl &= ~BIT(5);
pci_write_config_byte(plat->dev, 0xdc, bios_cntl | 0x1);
}

2
drivers/spi/mpc8xxx_spi.c
View file

@ -55,7 +55,7 @@ void spi_init(void)
* some registers
*/
spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN;
spi->mode = (spi->mode & 0xfff0ffff) | (1 << 16); /* Use SYSCLK / 8
spi->mode = (spi->mode & 0xfff0ffff) | BIT(16); /* Use SYSCLK / 8
(16.67MHz typ.) */
spi->event = 0xffffffff; /* Clear all SPI events */
spi->mask = 0x00000000; /* Mask all SPI interrupts */

54
drivers/spi/omap3_spi.h
View file

@ -52,40 +52,40 @@ struct mcspi {
/* per-register bitmasks */
#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP (1 << 2)
#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE (1 << 0)
#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET (1 << 1)
#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
#define OMAP3_MCSPI_SYSSTATUS_RESETDONE (1 << 0)
#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
#define OMAP3_MCSPI_MODULCTRL_SINGLE (1 << 0)
#define OMAP3_MCSPI_MODULCTRL_MS (1 << 2)
#define OMAP3_MCSPI_MODULCTRL_STEST (1 << 3)
#define OMAP3_MCSPI_MODULCTRL_SINGLE BIT(0)
#define OMAP3_MCSPI_MODULCTRL_MS BIT(2)
#define OMAP3_MCSPI_MODULCTRL_STEST BIT(3)
#define OMAP3_MCSPI_CHCONF_PHA (1 << 0)
#define OMAP3_MCSPI_CHCONF_POL (1 << 1)
#define OMAP3_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
#define OMAP3_MCSPI_CHCONF_EPOL (1 << 6)
#define OMAP3_MCSPI_CHCONF_WL_MASK (0x1f << 7)
#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY (0x01 << 12)
#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY (0x02 << 12)
#define OMAP3_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
#define OMAP3_MCSPI_CHCONF_DMAW (1 << 14)
#define OMAP3_MCSPI_CHCONF_DMAR (1 << 15)
#define OMAP3_MCSPI_CHCONF_DPE0 (1 << 16)
#define OMAP3_MCSPI_CHCONF_DPE1 (1 << 17)
#define OMAP3_MCSPI_CHCONF_IS (1 << 18)
#define OMAP3_MCSPI_CHCONF_TURBO (1 << 19)
#define OMAP3_MCSPI_CHCONF_FORCE (1 << 20)
#define OMAP3_MCSPI_CHCONF_PHA BIT(0)
#define OMAP3_MCSPI_CHCONF_POL BIT(1)
#define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2)
#define OMAP3_MCSPI_CHCONF_EPOL BIT(6)
#define OMAP3_MCSPI_CHCONF_WL_MASK GENMASK(11, 7)
#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
#define OMAP3_MCSPI_CHCONF_TRM_MASK GENMASK(13, 12)
#define OMAP3_MCSPI_CHCONF_DMAW BIT(14)
#define OMAP3_MCSPI_CHCONF_DMAR BIT(15)
#define OMAP3_MCSPI_CHCONF_DPE0 BIT(16)
#define OMAP3_MCSPI_CHCONF_DPE1 BIT(17)
#define OMAP3_MCSPI_CHCONF_IS BIT(18)
#define OMAP3_MCSPI_CHCONF_TURBO BIT(19)
#define OMAP3_MCSPI_CHCONF_FORCE BIT(20)
#define OMAP3_MCSPI_CHSTAT_RXS (1 << 0)
#define OMAP3_MCSPI_CHSTAT_TXS (1 << 1)
#define OMAP3_MCSPI_CHSTAT_EOT (1 << 2)
#define OMAP3_MCSPI_CHSTAT_RXS BIT(0)
#define OMAP3_MCSPI_CHSTAT_TXS BIT(1)
#define OMAP3_MCSPI_CHSTAT_EOT BIT(2)
#define OMAP3_MCSPI_CHCTRL_EN (1 << 0)
#define OMAP3_MCSPI_CHCTRL_EN BIT(0)
#define OMAP3_MCSPI_CHCTRL_DIS (0 << 0)
#define OMAP3_MCSPI_WAKEUPENABLE_WKEN (1 << 0)
#define OMAP3_MCSPI_WAKEUPENABLE_WKEN BIT(0)
struct omap3_spi_slave {
struct spi_slave slave;

16
drivers/spi/sh_qspi.c
View file

@ -21,19 +21,19 @@
#define SPPCR_IO3FV 0x04
#define SPPCR_IO2FV 0x02
#define SPPCR_IO1FV 0x01
#define SPBDCR_RXBC0 (1 << 0)
#define SPCMD_SCKDEN (1 << 15)
#define SPCMD_SLNDEN (1 << 14)
#define SPCMD_SPNDEN (1 << 13)
#define SPCMD_SSLKP (1 << 7)
#define SPCMD_BRDV0 (1 << 2)
#define SPBDCR_RXBC0 BIT(0)
#define SPCMD_SCKDEN BIT(15)
#define SPCMD_SLNDEN BIT(14)
#define SPCMD_SPNDEN BIT(13)
#define SPCMD_SSLKP BIT(7)
#define SPCMD_BRDV0 BIT(2)
#define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \
SPCMD_SPNDEN | SPCMD_SSLKP | \
SPCMD_BRDV0
#define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \
SPCMD_BRDV0
#define SPBFCR_TXRST (1 << 7)
#define SPBFCR_RXRST (1 << 6)
#define SPBFCR_TXRST BIT(7)
#define SPBFCR_RXRST BIT(6)
/* SH QSPI register set */
struct sh_qspi_regs {

76
drivers/spi/tegra114_spi.c
View file

@ -33,54 +33,54 @@
DECLARE_GLOBAL_DATA_PTR;
/* COMMAND1 */
#define SPI_CMD1_GO (1 << 31)
#define SPI_CMD1_M_S (1 << 30)
#define SPI_CMD1_MODE_MASK 0x3
#define SPI_CMD1_GO BIT(31)
#define SPI_CMD1_M_S BIT(30)
#define SPI_CMD1_MODE_MASK GENMASK(1, 0)
#define SPI_CMD1_MODE_SHIFT 28
#define SPI_CMD1_CS_SEL_MASK 0x3
#define SPI_CMD1_CS_SEL_MASK GENMASK(1, 0)
#define SPI_CMD1_CS_SEL_SHIFT 26
#define SPI_CMD1_CS_POL_INACTIVE3 (1 << 25)
#define SPI_CMD1_CS_POL_INACTIVE2 (1 << 24)
#define SPI_CMD1_CS_POL_INACTIVE1 (1 << 23)
#define SPI_CMD1_CS_POL_INACTIVE0 (1 << 22)
#define SPI_CMD1_CS_SW_HW (1 << 21)
#define SPI_CMD1_CS_SW_VAL (1 << 20)
#define SPI_CMD1_IDLE_SDA_MASK 0x3
#define SPI_CMD1_CS_POL_INACTIVE3 BIT(25)
#define SPI_CMD1_CS_POL_INACTIVE2 BIT(24)
#define SPI_CMD1_CS_POL_INACTIVE1 BIT(23)
#define SPI_CMD1_CS_POL_INACTIVE0 BIT(22)
#define SPI_CMD1_CS_SW_HW BIT(21)
#define SPI_CMD1_CS_SW_VAL BIT(20)
#define SPI_CMD1_IDLE_SDA_MASK GENMASK(1, 0)
#define SPI_CMD1_IDLE_SDA_SHIFT 18
#define SPI_CMD1_BIDIR (1 << 17)
#define SPI_CMD1_LSBI_FE (1 << 16)
#define SPI_CMD1_LSBY_FE (1 << 15)
#define SPI_CMD1_BOTH_EN_BIT (1 << 14)
#define SPI_CMD1_BOTH_EN_BYTE (1 << 13)
#define SPI_CMD1_RX_EN (1 << 12)
#define SPI_CMD1_TX_EN (1 << 11)
#define SPI_CMD1_PACKED (1 << 5)
#define SPI_CMD1_BIT_LEN_MASK 0x1F
#define SPI_CMD1_BIDIR BIT(17)
#define SPI_CMD1_LSBI_FE BIT(16)
#define SPI_CMD1_LSBY_FE BIT(15)
#define SPI_CMD1_BOTH_EN_BIT BIT(14)
#define SPI_CMD1_BOTH_EN_BYTE BIT(13)
#define SPI_CMD1_RX_EN BIT(12)
#define SPI_CMD1_TX_EN BIT(11)
#define SPI_CMD1_PACKED BIT(5)
#define SPI_CMD1_BIT_LEN_MASK GENMASK(4, 0)
#define SPI_CMD1_BIT_LEN_SHIFT 0
/* COMMAND2 */
#define SPI_CMD2_TX_CLK_TAP_DELAY (1 << 6)
#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6)
#define SPI_CMD2_RX_CLK_TAP_DELAY (1 << 0)
#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0)
#define SPI_CMD2_TX_CLK_TAP_DELAY BIT(6)
#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11, 6)
#define SPI_CMD2_RX_CLK_TAP_DELAY BIT(0)
#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5, 0)
/* TRANSFER STATUS */
#define SPI_XFER_STS_RDY (1 << 30)
#define SPI_XFER_STS_RDY BIT(30)
/* FIFO STATUS */
#define SPI_FIFO_STS_CS_INACTIVE (1 << 31)
#define SPI_FIFO_STS_FRAME_END (1 << 30)
#define SPI_FIFO_STS_RX_FIFO_FLUSH (1 << 15)
#define SPI_FIFO_STS_TX_FIFO_FLUSH (1 << 14)
#define SPI_FIFO_STS_ERR (1 << 8)
#define SPI_FIFO_STS_TX_FIFO_OVF (1 << 7)
#define SPI_FIFO_STS_TX_FIFO_UNR (1 << 6)
#define SPI_FIFO_STS_RX_FIFO_OVF (1 << 5)
#define SPI_FIFO_STS_RX_FIFO_UNR (1 << 4)
#define SPI_FIFO_STS_TX_FIFO_FULL (1 << 3)
#define SPI_FIFO_STS_TX_FIFO_EMPTY (1 << 2)
#define SPI_FIFO_STS_RX_FIFO_FULL (1 << 1)
#define SPI_FIFO_STS_RX_FIFO_EMPTY (1 << 0)
#define SPI_FIFO_STS_CS_INACTIVE BIT(31)
#define SPI_FIFO_STS_FRAME_END BIT(30)
#define SPI_FIFO_STS_RX_FIFO_FLUSH BIT(15)
#define SPI_FIFO_STS_TX_FIFO_FLUSH BIT(14)
#define SPI_FIFO_STS_ERR BIT(8)
#define SPI_FIFO_STS_TX_FIFO_OVF BIT(7)
#define SPI_FIFO_STS_TX_FIFO_UNR BIT(6)
#define SPI_FIFO_STS_RX_FIFO_OVF BIT(5)
#define SPI_FIFO_STS_RX_FIFO_UNR BIT(4)
#define SPI_FIFO_STS_TX_FIFO_FULL BIT(3)
#define SPI_FIFO_STS_TX_FIFO_EMPTY BIT(2)
#define SPI_FIFO_STS_RX_FIFO_FULL BIT(1)
#define SPI_FIFO_STS_RX_FIFO_EMPTY BIT(0)
#define SPI_TIMEOUT 1000
#define TEGRA_SPI_MAX_FREQ 52000000

52
drivers/spi/tegra20_sflash.c
View file

@ -20,37 +20,37 @@
DECLARE_GLOBAL_DATA_PTR;
#define SPI_CMD_GO (1 << 30)
#define SPI_CMD_GO BIT(30)
#define SPI_CMD_ACTIVE_SCLK_SHIFT 26
#define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
#define SPI_CMD_CK_SDA (1 << 21)
#define SPI_CMD_CK_SDA BIT(21)
#define SPI_CMD_ACTIVE_SDA_SHIFT 18
#define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT)
#define SPI_CMD_CS_POL (1 << 16)
#define SPI_CMD_TXEN (1 << 15)
#define SPI_CMD_RXEN (1 << 14)
#define SPI_CMD_CS_VAL (1 << 13)
#define SPI_CMD_CS_SOFT (1 << 12)
#define SPI_CMD_CS_DELAY (1 << 9)
#define SPI_CMD_CS3_EN (1 << 8)
#define SPI_CMD_CS2_EN (1 << 7)
#define SPI_CMD_CS1_EN (1 << 6)
#define SPI_CMD_CS0_EN (1 << 5)
#define SPI_CMD_BIT_LENGTH (1 << 4)
#define SPI_CMD_BIT_LENGTH_MASK 0x0000001F
#define SPI_CMD_CS_POL BIT(16)
#define SPI_CMD_TXEN BIT(15)
#define SPI_CMD_RXEN BIT(14)
#define SPI_CMD_CS_VAL BIT(13)
#define SPI_CMD_CS_SOFT BIT(12)
#define SPI_CMD_CS_DELAY BIT(9)
#define SPI_CMD_CS3_EN BIT(8)
#define SPI_CMD_CS2_EN BIT(7)
#define SPI_CMD_CS1_EN BIT(6)
#define SPI_CMD_CS0_EN BIT(5)
#define SPI_CMD_BIT_LENGTH BIT(4)
#define SPI_CMD_BIT_LENGTH_MASK GENMASK(4, 0)
#define SPI_STAT_BSY (1 << 31)
#define SPI_STAT_RDY (1 << 30)
#define SPI_STAT_RXF_FLUSH (1 << 29)
#define SPI_STAT_TXF_FLUSH (1 << 28)
#define SPI_STAT_RXF_UNR (1 << 27)
#define SPI_STAT_TXF_OVF (1 << 26)
#define SPI_STAT_RXF_EMPTY (1 << 25)
#define SPI_STAT_RXF_FULL (1 << 24)
#define SPI_STAT_TXF_EMPTY (1 << 23)
#define SPI_STAT_TXF_FULL (1 << 22)
#define SPI_STAT_SEL_TXRX_N (1 << 16)
#define SPI_STAT_CUR_BLKCNT (1 << 15)
#define SPI_STAT_BSY BIT(31)
#define SPI_STAT_RDY BIT(30)
#define SPI_STAT_RXF_FLUSH BIT(29)
#define SPI_STAT_TXF_FLUSH BIT(28)
#define SPI_STAT_RXF_UNR BIT(27)
#define SPI_STAT_TXF_OVF BIT(26)
#define SPI_STAT_RXF_EMPTY BIT(25)
#define SPI_STAT_RXF_FULL BIT(24)
#define SPI_STAT_TXF_EMPTY BIT(23)
#define SPI_STAT_TXF_FULL BIT(22)
#define SPI_STAT_SEL_TXRX_N BIT(16)
#define SPI_STAT_CUR_BLKCNT BIT(15)
#define SPI_TIMEOUT 1000
#define TEGRA_SPI_MAX_FREQ 52000000

62
drivers/spi/tegra20_slink.c
View file

@ -33,45 +33,45 @@
DECLARE_GLOBAL_DATA_PTR;
/* COMMAND */
#define SLINK_CMD_ENB (1 << 31)
#define SLINK_CMD_GO (1 << 30)
#define SLINK_CMD_M_S (1 << 28)
#define SLINK_CMD_ENB BIT(31)
#define SLINK_CMD_GO BIT(30)
#define SLINK_CMD_M_S BIT(28)
#define SLINK_CMD_IDLE_SCLK_DRIVE_LOW (0 << 24)
#define SLINK_CMD_IDLE_SCLK_DRIVE_HIGH (1 << 24)
#define SLINK_CMD_IDLE_SCLK_DRIVE_HIGH BIT(24)
#define SLINK_CMD_IDLE_SCLK_PULL_LOW (2 << 24)
#define SLINK_CMD_IDLE_SCLK_PULL_HIGH (3 << 24)
#define SLINK_CMD_IDLE_SCLK_MASK (3 << 24)
#define SLINK_CMD_CK_SDA (1 << 21)
#define SLINK_CMD_CS_POL (1 << 13)
#define SLINK_CMD_CS_VAL (1 << 12)
#define SLINK_CMD_CS_SOFT (1 << 11)
#define SLINK_CMD_BIT_LENGTH (1 << 4)
#define SLINK_CMD_BIT_LENGTH_MASK 0x0000001F
#define SLINK_CMD_CK_SDA BIT(21)
#define SLINK_CMD_CS_POL BIT(13)
#define SLINK_CMD_CS_VAL BIT(12)
#define SLINK_CMD_CS_SOFT BIT(11)
#define SLINK_CMD_BIT_LENGTH BIT(4)
#define SLINK_CMD_BIT_LENGTH_MASK GENMASK(4, 0)
/* COMMAND2 */
#define SLINK_CMD2_TXEN (1 << 30)
#define SLINK_CMD2_RXEN (1 << 31)
#define SLINK_CMD2_SS_EN (1 << 18)
#define SLINK_CMD2_TXEN BIT(30)
#define SLINK_CMD2_RXEN BIT(31)
#define SLINK_CMD2_SS_EN BIT(18)
#define SLINK_CMD2_SS_EN_SHIFT 18
#define SLINK_CMD2_SS_EN_MASK 0x000C0000
#define SLINK_CMD2_CS_ACTIVE_BETWEEN (1 << 17)
#define SLINK_CMD2_SS_EN_MASK GENMASK(19, 18)
#define SLINK_CMD2_CS_ACTIVE_BETWEEN BIT(17)
/* STATUS */
#define SLINK_STAT_BSY (1 << 31)
#define SLINK_STAT_RDY (1 << 30)
#define SLINK_STAT_ERR (1 << 29)
#define SLINK_STAT_RXF_FLUSH (1 << 27)
#define SLINK_STAT_TXF_FLUSH (1 << 26)
#define SLINK_STAT_RXF_OVF (1 << 25)
#define SLINK_STAT_TXF_UNR (1 << 24)
#define SLINK_STAT_RXF_EMPTY (1 << 23)
#define SLINK_STAT_RXF_FULL (1 << 22)
#define SLINK_STAT_TXF_EMPTY (1 << 21)
#define SLINK_STAT_TXF_FULL (1 << 20)
#define SLINK_STAT_TXF_OVF (1 << 19)
#define SLINK_STAT_RXF_UNR (1 << 18)
#define SLINK_STAT_CUR_BLKCNT (1 << 15)
#define SLINK_STAT_BSY BIT(31)
#define SLINK_STAT_RDY BIT(30)
#define SLINK_STAT_ERR BIT(29)
#define SLINK_STAT_RXF_FLUSH BIT(27)
#define SLINK_STAT_TXF_FLUSH BIT(26)
#define SLINK_STAT_RXF_OVF BIT(25)
#define SLINK_STAT_TXF_UNR BIT(24)
#define SLINK_STAT_RXF_EMPTY BIT(23)
#define SLINK_STAT_RXF_FULL BIT(22)
#define SLINK_STAT_TXF_EMPTY BIT(21)
#define SLINK_STAT_TXF_FULL BIT(20)
#define SLINK_STAT_TXF_OVF BIT(19)
#define SLINK_STAT_RXF_UNR BIT(18)
#define SLINK_STAT_CUR_BLKCNT BIT(15)
/* STATUS2 */
#define SLINK_STAT2_RXF_FULL_CNT (1 << 16)
#define SLINK_STAT2_TXF_FULL_CNT (1 << 0)
#define SLINK_STAT2_RXF_FULL_CNT BIT(16)
#define SLINK_STAT2_TXF_FULL_CNT BIT(0)
#define SPI_TIMEOUT 1000
#define TEGRA_SPI_MAX_FREQ 52000000

10
drivers/spi/ti_qspi.c
View file

@ -20,13 +20,13 @@
#define QSPI_TIMEOUT 2000000
#define QSPI_FCLK 192000000
/* clock control */
#define QSPI_CLK_EN (1 << 31)
#define QSPI_CLK_EN BIT(31)
#define QSPI_CLK_DIV_MAX 0xffff
/* command */
#define QSPI_EN_CS(n) (n << 28)
#define QSPI_WLEN(n) ((n-1) << 19)
#define QSPI_3_PIN (1 << 18)
#define QSPI_RD_SNGL (1 << 16)
#define QSPI_3_PIN BIT(18)
#define QSPI_RD_SNGL BIT(16)
#define QSPI_WR_SNGL (2 << 16)
#define QSPI_INVAL (4 << 16)
#define QSPI_RD_QUAD (7 << 16)
@ -36,8 +36,8 @@
#define QSPI_CSPOL(n) (1 << (1 + n*8))
#define QSPI_CKPOL(n) (1 << (n*8))
/* status */
#define QSPI_WC (1 << 1)
#define QSPI_BUSY (1 << 0)
#define QSPI_WC BIT(1)
#define QSPI_BUSY BIT(0)
#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
#define QSPI_XFER_DONE QSPI_WC
#define MM_SWITCH 0x01

46
drivers/spi/xilinx_spi.c
View file

@ -32,34 +32,34 @@
*/
/* SPI Control Register (spicr), [1] p9, [2] p8 */
#define SPICR_LSB_FIRST (1 << 9)
#define SPICR_MASTER_INHIBIT (1 << 8)
#define SPICR_MANUAL_SS (1 << 7)
#define SPICR_RXFIFO_RESEST (1 << 6)
#define SPICR_TXFIFO_RESEST (1 << 5)
#define SPICR_CPHA (1 << 4)
#define SPICR_CPOL (1 << 3)
#define SPICR_MASTER_MODE (1 << 2)
#define SPICR_SPE (1 << 1)
#define SPICR_LOOP (1 << 0)
#define SPICR_LSB_FIRST BIT(9)
#define SPICR_MASTER_INHIBIT BIT(8)
#define SPICR_MANUAL_SS BIT(7)
#define SPICR_RXFIFO_RESEST BIT(6)
#define SPICR_TXFIFO_RESEST BIT(5)
#define SPICR_CPHA BIT(4)
#define SPICR_CPOL BIT(3)
#define SPICR_MASTER_MODE BIT(2)
#define SPICR_SPE BIT(1)
#define SPICR_LOOP BIT(0)
/* SPI Status Register (spisr), [1] p11, [2] p10 */
#define SPISR_SLAVE_MODE_SELECT (1 << 5)
#define SPISR_MODF (1 << 4)
#define SPISR_TX_FULL (1 << 3)
#define SPISR_TX_EMPTY (1 << 2)
#define SPISR_RX_FULL (1 << 1)
#define SPISR_RX_EMPTY (1 << 0)
#define SPISR_SLAVE_MODE_SELECT BIT(5)
#define SPISR_MODF BIT(4)
#define SPISR_TX_FULL BIT(3)
#define SPISR_TX_EMPTY BIT(2)
#define SPISR_RX_FULL BIT(1)
#define SPISR_RX_EMPTY BIT(0)
/* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
#define SPIDTR_8BIT_MASK (0xff << 0)
#define SPIDTR_16BIT_MASK (0xffff << 0)
#define SPIDTR_32BIT_MASK (0xffffffff << 0)
#define SPIDTR_8BIT_MASK GENMASK(7, 0)
#define SPIDTR_16BIT_MASK GENMASK(15, 0)
#define SPIDTR_32BIT_MASK GENMASK(31, 0)
/* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */
#define SPIDRR_8BIT_MASK (0xff << 0)
#define SPIDRR_16BIT_MASK (0xffff << 0)
#define SPIDRR_32BIT_MASK (0xffffffff << 0)
#define SPIDRR_8BIT_MASK GENMASK(7, 0)
#define SPIDRR_16BIT_MASK GENMASK(15, 0)
#define SPIDRR_32BIT_MASK GENMASK(31, 0)
/* SPI Slave Select Register (spissr), [1] p13, [2] p13 */
#define SPISSR_MASK(cs) (1 << (cs))
@ -75,7 +75,7 @@
#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
#ifndef CONFIG_XILINX_SPI_IDLE_VAL
#define CONFIG_XILINX_SPI_IDLE_VAL 0xff
#define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0)
#endif
#ifndef CONFIG_SYS_XILINX_SPI_LIST

621
drivers/spi/zynq_qspi.c Normal file
View file

@ -0,0 +1,621 @@
/*
* (C) Copyright 2013 Xilinx, Inc.
* (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
*
* Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <spi.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
/* zynq qspi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
#define ZYNQ_QSPI_CR_IFMODE_MASK BIT(31) /* Flash intrface mode*/
#define ZYNQ_QSPI_CR_MSA_MASK BIT(15) /* Manual start enb */
#define ZYNQ_QSPI_CR_MCS_MASK BIT(14) /* Manual chip select */
#define ZYNQ_QSPI_CR_PCS_MASK BIT(10) /* Peri chip select */
#define ZYNQ_QSPI_CR_FW_MASK GENMASK(7, 6) /* FIFO width */
#define ZYNQ_QSPI_CR_SS_MASK GENMASK(13, 10) /* Slave Select */
#define ZYNQ_QSPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
#define ZYNQ_QSPI_CR_CPHA_MASK BIT(2) /* Clock phase */
#define ZYNQ_QSPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
#define ZYNQ_QSPI_CR_MSTREN_MASK BIT(0) /* Mode select */
#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
#define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
#define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
#define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
/* zynq qspi Transmit Data Register */
#define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */
#define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst */
#define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst */
#define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst */
#define ZYNQ_QSPI_TXFIFO_THRESHOLD 1 /* Tx FIFO threshold level*/
#define ZYNQ_QSPI_RXFIFO_THRESHOLD 32 /* Rx FIFO threshold level */
#define ZYNQ_QSPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
#define ZYNQ_QSPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
#define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */
#define ZYNQ_QSPI_FIFO_DEPTH 63
#ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT
#define CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
/* zynq qspi register set */
struct zynq_qspi_regs {
u32 cr; /* 0x00 */
u32 isr; /* 0x04 */
u32 ier; /* 0x08 */
u32 idr; /* 0x0C */
u32 imr; /* 0x10 */
u32 enr; /* 0x14 */
u32 dr; /* 0x18 */
u32 txd0r; /* 0x1C */
u32 drxr; /* 0x20 */
u32 sicr; /* 0x24 */
u32 txftr; /* 0x28 */
u32 rxftr; /* 0x2C */
u32 gpior; /* 0x30 */
u32 reserved0[19];
u32 txd1r; /* 0x80 */
u32 txd2r; /* 0x84 */
u32 txd3r; /* 0x88 */
};
/* zynq qspi platform data */
struct zynq_qspi_platdata {
struct zynq_qspi_regs *regs;
u32 frequency; /* input frequency */
u32 speed_hz;
};
/* zynq qspi priv */
struct zynq_qspi_priv {
struct zynq_qspi_regs *regs;
u8 cs;
u8 mode;
u8 fifo_depth;
u32 freq; /* required frequency */
const void *tx_buf;
void *rx_buf;
unsigned len;
int bytes_to_transfer;
int bytes_to_receive;
unsigned int is_inst;
unsigned cs_change:1;
};
static int zynq_qspi_ofdata_to_platdata(struct udevice *bus)
{
struct zynq_qspi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
int node = bus->of_offset;
plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
node, "reg");
/* FIXME: Use 166MHz as a suitable default */
plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
166666666);
plat->speed_hz = plat->frequency / 2;
debug("%s: regs=%p max-frequency=%d\n", __func__,
plat->regs, plat->frequency);
return 0;
}
static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
{
struct zynq_qspi_regs *regs = priv->regs;
u32 confr;
/* Disable QSPI */
writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
/* Disable Interrupts */
writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->idr);
/* Clear the TX and RX threshold reg */
writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, &regs->txftr);
writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, &regs->rxftr);
/* Clear the RX FIFO */
while (readl(&regs->isr) & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
readl(&regs->drxr);
/* Clear Interrupts */
writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->isr);
/* Manual slave select and Auto start */
confr = readl(&regs->cr);
confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
ZYNQ_QSPI_CR_MSTREN_MASK;
writel(confr, &regs->cr);
/* Enable SPI */
writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
}
static int zynq_qspi_probe(struct udevice *bus)
{
struct zynq_qspi_platdata *plat = dev_get_platdata(bus);
struct zynq_qspi_priv *priv = dev_get_priv(bus);
priv->regs = plat->regs;
priv->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH;
/* init the zynq spi hw */
zynq_qspi_init_hw(priv);
return 0;
}
/*
* zynq_qspi_read_data - Copy data to RX buffer
* @zqspi: Pointer to the zynq_qspi structure
* @data: The 32 bit variable where data is stored
* @size: Number of bytes to be copied from data to RX buffer
*/
static void zynq_qspi_read_data(struct zynq_qspi_priv *priv, u32 data, u8 size)
{
u8 byte3;
debug("%s: data 0x%04x rx_buf addr: 0x%08x size %d\n", __func__ ,
data, (unsigned)(priv->rx_buf), size);
if (priv->rx_buf) {
switch (size) {
case 1:
*((u8 *)priv->rx_buf) = data;
priv->rx_buf += 1;
break;
case 2:
*((u16 *)priv->rx_buf) = data;
priv->rx_buf += 2;
break;
case 3:
*((u16 *)priv->rx_buf) = data;
priv->rx_buf += 2;
byte3 = (u8)(data >> 16);
*((u8 *)priv->rx_buf) = byte3;
priv->rx_buf += 1;
break;
case 4:
/* Can not assume word aligned buffer */
memcpy(priv->rx_buf, &data, size);
priv->rx_buf += 4;
break;
default:
/* This will never execute */
break;
}
}
priv->bytes_to_receive -= size;
if (priv->bytes_to_receive < 0)
priv->bytes_to_receive = 0;
}
/*
* zynq_qspi_write_data - Copy data from TX buffer
* @zqspi: Pointer to the zynq_qspi structure
* @data: Pointer to the 32 bit variable where data is to be copied
* @size: Number of bytes to be copied from TX buffer to data
*/
static void zynq_qspi_write_data(struct zynq_qspi_priv *priv,
u32 *data, u8 size)
{
if (priv->tx_buf) {
switch (size) {
case 1:
*data = *((u8 *)priv->tx_buf);
priv->tx_buf += 1;
*data |= 0xFFFFFF00;
break;
case 2:
*data = *((u16 *)priv->tx_buf);
priv->tx_buf += 2;
*data |= 0xFFFF0000;
break;
case 3:
*data = *((u16 *)priv->tx_buf);
priv->tx_buf += 2;
*data |= (*((u8 *)priv->tx_buf) << 16);
priv->tx_buf += 1;
*data |= 0xFF000000;
break;
case 4:
/* Can not assume word aligned buffer */
memcpy(data, priv->tx_buf, size);
priv->tx_buf += 4;
break;
default:
/* This will never execute */
break;
}
} else {
*data = 0;
}
debug("%s: data 0x%08x tx_buf addr: 0x%08x size %d\n", __func__,
*data, (u32)priv->tx_buf, size);
priv->bytes_to_transfer -= size;
if (priv->bytes_to_transfer < 0)
priv->bytes_to_transfer = 0;
}
static void zynq_qspi_chipselect(struct zynq_qspi_priv *priv, int is_on)
{
u32 confr;
struct zynq_qspi_regs *regs = priv->regs;
confr = readl(&regs->cr);
if (is_on) {
/* Select the slave */
confr &= ~ZYNQ_QSPI_CR_SS_MASK;
confr |= (~(1 << priv->cs) << ZYNQ_QSPI_CR_SS_SHIFT) &
ZYNQ_QSPI_CR_SS_MASK;
} else
/* Deselect the slave */
confr |= ZYNQ_QSPI_CR_SS_MASK;
writel(confr, &regs->cr);
}
/*
* zynq_qspi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
* @zqspi: Pointer to the zynq_qspi structure
*/
static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size)
{
u32 data = 0;
u32 fifocount = 0;
unsigned len, offset;
struct zynq_qspi_regs *regs = priv->regs;
static const unsigned offsets[4] = {
ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET,
ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET };
while ((fifocount < size) &&
(priv->bytes_to_transfer > 0)) {
if (priv->bytes_to_transfer >= 4) {
if (priv->tx_buf) {
memcpy(&data, priv->tx_buf, 4);
priv->tx_buf += 4;
} else {
data = 0;
}
writel(data, &regs->txd0r);
priv->bytes_to_transfer -= 4;
fifocount++;
} else {
/* Write TXD1, TXD2, TXD3 only if TxFIFO is empty. */
if (!(readl(&regs->isr)
& ZYNQ_QSPI_IXR_TXOW_MASK) &&
!priv->rx_buf)
return;
len = priv->bytes_to_transfer;
zynq_qspi_write_data(priv, &data, len);
offset = (priv->rx_buf) ? offsets[0] : offsets[len];
writel(data, &regs->cr + (offset / 4));
}
}
}
/*
* zynq_qspi_irq_poll - Interrupt service routine of the QSPI controller
* @zqspi: Pointer to the zynq_qspi structure
*
* This function handles TX empty and Mode Fault interrupts only.
* On TX empty interrupt this function reads the received data from RX FIFO and
* fills the TX FIFO if there is any data remaining to be transferred.
* On Mode Fault interrupt this function indicates that transfer is completed,
* the SPI subsystem will identify the error as the remaining bytes to be
* transferred is non-zero.
*
* returns: 0 for poll timeout
* 1 transfer operation complete
*/
static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv)
{
struct zynq_qspi_regs *regs = priv->regs;
u32 rxindex = 0;
u32 rxcount;
u32 status, timeout;
/* Poll until any of the interrupt status bits are set */
timeout = get_timer(0);
do {
status = readl(&regs->isr);
} while ((status == 0) &&
(get_timer(timeout) < CONFIG_SYS_ZYNQ_QSPI_WAIT));
if (status == 0) {
printf("zynq_qspi_irq_poll: Timeout!\n");
return -ETIMEDOUT;
}
writel(status, &regs->isr);
/* Disable all interrupts */
writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->idr);
if ((status & ZYNQ_QSPI_IXR_TXOW_MASK) ||
(status & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)) {
/*
* This bit is set when Tx FIFO has < THRESHOLD entries. We have
* the THRESHOLD value set to 1, so this bit indicates Tx FIFO
* is empty
*/
rxcount = priv->bytes_to_receive - priv->bytes_to_transfer;
rxcount = (rxcount % 4) ? ((rxcount/4)+1) : (rxcount/4);
while ((rxindex < rxcount) &&
(rxindex < ZYNQ_QSPI_RXFIFO_THRESHOLD)) {
/* Read out the data from the RX FIFO */
u32 data;
data = readl(&regs->drxr);
if (priv->bytes_to_receive >= 4) {
if (priv->rx_buf) {
memcpy(priv->rx_buf, &data, 4);
priv->rx_buf += 4;
}
priv->bytes_to_receive -= 4;
} else {
zynq_qspi_read_data(priv, data,
priv->bytes_to_receive);
}
rxindex++;
}
if (priv->bytes_to_transfer) {
/* There is more data to send */
zynq_qspi_fill_tx_fifo(priv,
ZYNQ_QSPI_RXFIFO_THRESHOLD);
writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->ier);
} else {
/*
* If transfer and receive is completed then only send
* complete signal
*/
if (!priv->bytes_to_receive) {
/* return operation complete */
writel(ZYNQ_QSPI_IXR_ALL_MASK,
&regs->idr);
return 1;
}
}
}
return 0;
}
/*
* zynq_qspi_start_transfer - Initiates the QSPI transfer
* @qspi: Pointer to the spi_device structure
* @transfer: Pointer to the spi_transfer structure which provide information
* about next transfer parameters
*
* This function fills the TX FIFO, starts the QSPI transfer, and waits for the
* transfer to be completed.
*
* returns: Number of bytes transferred in the last transfer
*/
static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv)
{
u32 data = 0;
struct zynq_qspi_regs *regs = priv->regs;
debug("%s: qspi: 0x%08x transfer: 0x%08x len: %d\n", __func__,
(u32)priv, (u32)priv, priv->len);
priv->bytes_to_transfer = priv->len;
priv->bytes_to_receive = priv->len;
if (priv->len < 4)
zynq_qspi_fill_tx_fifo(priv, priv->len);
else
zynq_qspi_fill_tx_fifo(priv, priv->fifo_depth);
writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->ier);
/* wait for completion */
do {
data = zynq_qspi_irq_poll(priv);
} while (data == 0);
return (priv->len) - (priv->bytes_to_transfer);
}
static int zynq_qspi_transfer(struct zynq_qspi_priv *priv)
{
unsigned cs_change = 1;
int status = 0;
while (1) {
/* Select the chip if required */
if (cs_change)
zynq_qspi_chipselect(priv, 1);
cs_change = priv->cs_change;
if (!priv->tx_buf && !priv->rx_buf && priv->len) {
status = -1;
break;
}
/* Request the transfer */
if (priv->len) {
status = zynq_qspi_start_transfer(priv);
priv->is_inst = 0;
}
if (status != priv->len) {
if (status > 0)
status = -EMSGSIZE;
debug("zynq_qspi_transfer:%d len:%d\n",
status, priv->len);
break;
}
status = 0;
if (cs_change)
/* Deselect the chip */
zynq_qspi_chipselect(priv, 0);
break;
}
return 0;
}
static int zynq_qspi_claim_bus(struct udevice *dev)
{
struct udevice *bus = dev->parent;
struct zynq_qspi_priv *priv = dev_get_priv(bus);
struct zynq_qspi_regs *regs = priv->regs;
writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
return 0;
}
static int zynq_qspi_release_bus(struct udevice *dev)
{
struct udevice *bus = dev->parent;
struct zynq_qspi_priv *priv = dev_get_priv(bus);
struct zynq_qspi_regs *regs = priv->regs;
writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
return 0;
}
static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
struct udevice *bus = dev->parent;
struct zynq_qspi_priv *priv = dev_get_priv(bus);
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
priv->cs = slave_plat->cs;
priv->tx_buf = dout;
priv->rx_buf = din;
priv->len = bitlen / 8;
debug("zynq_qspi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
bus->seq, slave_plat->cs, bitlen, priv->len, flags);
/*
* Festering sore.
* Assume that the beginning of a transfer with bits to
* transmit must contain a device command.
*/
if (dout && flags & SPI_XFER_BEGIN)
priv->is_inst = 1;
else
priv->is_inst = 0;
if (flags & SPI_XFER_END)
priv->cs_change = 1;
else
priv->cs_change = 0;
zynq_qspi_transfer(priv);
return 0;
}
static int zynq_qspi_set_speed(struct udevice *bus, uint speed)
{
struct zynq_qspi_platdata *plat = bus->platdata;
struct zynq_qspi_priv *priv = dev_get_priv(bus);
struct zynq_qspi_regs *regs = priv->regs;
uint32_t confr;
u8 baud_rate_val = 0;
if (speed > plat->frequency)
speed = plat->frequency;
/* Set the clock frequency */
confr = readl(&regs->cr);
if (speed == 0) {
/* Set baudrate x8, if the freq is 0 */
baud_rate_val = 0x2;
} else if (plat->speed_hz != speed) {
while ((baud_rate_val < ZYNQ_QSPI_CR_BAUD_MAX) &&
((plat->frequency /
(2 << baud_rate_val)) > speed))
baud_rate_val++;
plat->speed_hz = speed / (2 << baud_rate_val);
}
confr &= ~ZYNQ_QSPI_CR_BAUD_MASK;
confr |= (baud_rate_val << ZYNQ_QSPI_CR_BAUD_SHIFT);
writel(confr, &regs->cr);
priv->freq = speed;
debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
return 0;
}
static int zynq_qspi_set_mode(struct udevice *bus, uint mode)
{
struct zynq_qspi_priv *priv = dev_get_priv(bus);
struct zynq_qspi_regs *regs = priv->regs;
uint32_t confr;
/* Set the SPI Clock phase and polarities */
confr = readl(&regs->cr);
confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK | ZYNQ_QSPI_CR_CPOL_MASK);
if (mode & SPI_CPHA)
confr |= ZYNQ_QSPI_CR_CPHA_MASK;
if (mode & SPI_CPOL)
confr |= ZYNQ_QSPI_CR_CPOL_MASK;
writel(confr, &regs->cr);
priv->mode = mode;
debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
return 0;
}
static const struct dm_spi_ops zynq_qspi_ops = {
.claim_bus = zynq_qspi_claim_bus,
.release_bus = zynq_qspi_release_bus,
.xfer = zynq_qspi_xfer,
.set_speed = zynq_qspi_set_speed,
.set_mode = zynq_qspi_set_mode,
};
static const struct udevice_id zynq_qspi_ids[] = {
{ .compatible = "xlnx,zynq-qspi-1.0" },
{ }
};
U_BOOT_DRIVER(zynq_qspi) = {
.name = "zynq_qspi",
.id = UCLASS_SPI,
.of_match = zynq_qspi_ids,
.ops = &zynq_qspi_ops,
.ofdata_to_platdata = zynq_qspi_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct zynq_qspi_platdata),
.priv_auto_alloc_size = sizeof(struct zynq_qspi_priv),
.probe = zynq_qspi_probe,
};

46
drivers/spi/zynq_spi.c
View file

@ -1,5 +1,5 @@
/*
* (C) Copyright 2013 Inc.
* (C) Copyright 2013 Xilinx, Inc.
* (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
*
* Xilinx Zynq PS SPI controller driver (master mode only)
@ -7,30 +7,30 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <spi.h>
#include <fdtdec.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
/* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
#define ZYNQ_SPI_CR_MSA_MASK (1 << 15) /* Manual start enb */
#define ZYNQ_SPI_CR_MCS_MASK (1 << 14) /* Manual chip select */
#define ZYNQ_SPI_CR_CS_MASK (0xF << 10) /* Chip select */
#define ZYNQ_SPI_CR_BRD_MASK (0x7 << 3) /* Baud rate div */
#define ZYNQ_SPI_CR_CPHA_MASK (1 << 2) /* Clock phase */
#define ZYNQ_SPI_CR_CPOL_MASK (1 << 1) /* Clock polarity */
#define ZYNQ_SPI_CR_MSTREN_MASK (1 << 0) /* Mode select */
#define ZYNQ_SPI_IXR_RXNEMPTY_MASK (1 << 4) /* RX_FIFO_not_empty */
#define ZYNQ_SPI_IXR_TXOW_MASK (1 << 2) /* TX_FIFO_not_full */
#define ZYNQ_SPI_IXR_ALL_MASK 0x7F /* All IXR bits */
#define ZYNQ_SPI_ENR_SPI_EN_MASK (1 << 0) /* SPI Enable */
#define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */
#define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */
#define ZYNQ_SPI_CR_CS_MASK GENMASK(13, 10) /* Chip select */
#define ZYNQ_SPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
#define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */
#define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
#define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */
#define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
#define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
#define ZYNQ_SPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
#define ZYNQ_SPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
#define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
#define ZYNQ_SPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
#define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */
#define ZYNQ_SPI_FIFO_DEPTH 128
#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT
@ -61,6 +61,7 @@ struct zynq_spi_platdata {
/* zynq spi priv */
struct zynq_spi_priv {
struct zynq_spi_regs *regs;
u8 cs;
u8 mode;
u8 fifo_depth;
u32 freq; /* required frequency */
@ -128,7 +129,7 @@ static int zynq_spi_probe(struct udevice *bus)
return 0;
}
static void spi_cs_activate(struct udevice *dev, uint cs)
static void spi_cs_activate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
struct zynq_spi_priv *priv = dev_get_priv(bus);
@ -143,7 +144,7 @@ static void spi_cs_activate(struct udevice *dev, uint cs)
* xx01 - cs1
* x011 - cs2
*/
cr |= (~(0x1 << cs) << 10) & ZYNQ_SPI_CR_CS_MASK;
cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
writel(cr, &regs->cr);
}
@ -199,8 +200,9 @@ static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
return -1;
}
priv->cs = slave_plat->cs;
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(dev, slave_plat->cs);
spi_cs_activate(dev);
while (rx_len > 0) {
/* Write the data into TX FIFO - tx threshold is fifo_depth */
@ -260,14 +262,14 @@ static int zynq_spi_set_speed(struct udevice *bus, uint speed)
/* Set baudrate x8, if the freq is 0 */
baud_rate_val = 0x2;
} else if (plat->speed_hz != speed) {
while ((baud_rate_val < 8) &&
while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) &&
((plat->frequency /
(2 << baud_rate_val)) > speed))
baud_rate_val++;
plat->speed_hz = speed / (2 << baud_rate_val);
}
confr &= ~ZYNQ_SPI_CR_BRD_MASK;
confr |= (baud_rate_val << 3);
confr &= ~ZYNQ_SPI_CR_BAUD_MASK;
confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);
writel(confr, &regs->cr);
priv->freq = speed;

15
include/configs/zynq-common.h
View file

@ -72,6 +72,17 @@
# define CONFIG_CMD_SF
#endif
/* QSPI */
#ifdef CONFIG_ZYNQ_QSPI
# define CONFIG_SF_DEFAULT_SPEED 30000000
# define CONFIG_SPI_FLASH_ISSI
# define CONFIG_SPI_FLASH_SPANSION
# define CONFIG_SPI_FLASH_STMICRO
# define CONFIG_SPI_FLASH_WINBOND
# define CONFIG_SPI_FLASH_BAR
# define CONFIG_CMD_SF
#endif
/* NOR */
#ifndef CONFIG_SYS_NO_FLASH
# define CONFIG_SYS_FLASH_BASE 0xE2000000
@ -344,6 +355,10 @@
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000
#define CONFIG_SYS_SPI_ARGS_OFFS 0x200000
#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
#define CONFIG_SYS_SPI_KERNEL_OFFS (CONFIG_SYS_SPI_ARGS_OFFS + \
CONFIG_SYS_SPI_ARGS_SIZE)
#endif
/* for booting directly linux */

6
include/spi_flash.h
View file

@ -38,10 +38,10 @@ struct spi_slave;
*
* @spi: SPI slave
* @dev: SPI flash device
* @flags: Indication of spi flash flags
* @name: Name of SPI flash
* @dual_flash: Indicates dual flash memories - dual stacked, parallel
* @shift: Flash shift useful in dual parallel
* @flags: Indication of spi flash flags
* @size: Total flash size
* @page_size: Write (page) size
* @sector_size: Sector size
@ -49,7 +49,6 @@ struct spi_slave;
* @bank_read_cmd: Bank read cmd
* @bank_write_cmd: Bank write cmd
* @bank_curr: Current flash bank
* @poll_cmd: Poll cmd - for flash erase/program
* @erase_cmd: Erase cmd 4K, 32K, 64K
* @read_cmd: Read cmd - Array Fast, Extn read and quad read.
* @write_cmd: Write cmd - page and quad program.
@ -67,11 +66,11 @@ struct spi_flash {
struct spi_slave *spi;
#ifdef CONFIG_DM_SPI_FLASH
struct udevice *dev;
u16 flags;
#endif
const char *name;
u8 dual_flash;
u8 shift;
u16 flags;
u32 size;
u32 page_size;
@ -82,7 +81,6 @@ struct spi_flash {
u8 bank_write_cmd;
u8 bank_curr;
#endif
u8 poll_cmd;
u8 erase_cmd;
u8 read_cmd;
u8 write_cmd;