From 0413f9c3e6f44b80dad8eabef4cf286d3f365684 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 11 Sep 2019 08:49:31 +0200 Subject: [PATCH 01/85] arm64: zynqmp: Define default SPL_TEXT_BASE address in Kconfig Define default address via Kconfig. There is no need to change this address for most of the boards but it is also possible. This one line save a lot of lines in defconfigs that's why make sense to do it. The similar change has been done by commit 9340d8fe8beb ("sunxi: move CONFIG_SPL_TEXT_BASE from *_defconfig to Kconfig") Signed-off-by: Michal Simek Reviewed-by: Luca Ceresoli --- common/spl/Kconfig | 1 + configs/avnet_ultra96_rev1_defconfig | 1 - configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig | 1 - configs/xilinx_zynqmp_mini_emmc0_defconfig | 1 - configs/xilinx_zynqmp_mini_emmc1_defconfig | 1 - configs/xilinx_zynqmp_mini_qspi_defconfig | 1 - configs/xilinx_zynqmp_zc1232_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1254_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 1 - configs/xilinx_zynqmp_zcu100_revC_defconfig | 1 - configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 - configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 - configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu111_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu1275_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu1275_revB_defconfig | 1 - 23 files changed, 1 insertion(+), 22 deletions(-) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index f467eca2be..59a7b20089 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -138,6 +138,7 @@ config SPL_TEXT_BASE default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I default 0x20060 if MACH_SUN50I_H6 default 0x00060 if ARCH_SUNXI + default 0xfffc0000 if ARCH_ZYNQMP default 0x0 help The address in memory that SPL will be running from. diff --git a/configs/avnet_ultra96_rev1_defconfig b/configs/avnet_ultra96_rev1_defconfig index feffcc0089..9241530811 100644 --- a/configs/avnet_ultra96_rev1_defconfig +++ b/configs/avnet_ultra96_rev1_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_ZYNQ_SDHCI_MAX_FREQ=15000000 CONFIG_ZYNQMP_USB=y CONFIG_DEBUG_UART=y -CONFIG_SPL_TEXT_BASE=0xfffc0000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig index 31e1bda428..f463318565 100644 --- a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig +++ b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig @@ -9,7 +9,6 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_ZYNQMP_TWO_SDHCI=y CONFIG_DEBUG_UART=y -CONFIG_SPL_TEXT_BASE=0xfffc0000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig index f15c0937bd..b4162abdd7 100644 --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig @@ -7,7 +7,6 @@ CONFIG_ENV_SIZE=0x80 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y # CONFIG_CMD_ZYNQMP is not set -CONFIG_SPL_TEXT_BASE=0xfffc0000 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y # CONFIG_BOARD_LATE_INIT is not set diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig index fb9a18263f..76d5aa6c71 100644 --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig @@ -7,7 +7,6 @@ CONFIG_ENV_SIZE=0x80 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y # CONFIG_CMD_ZYNQMP is not set -CONFIG_SPL_TEXT_BASE=0xfffc0000 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y # CONFIG_BOARD_LATE_INIT is not set diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index bc63c08330..a20534a488 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -10,7 +10,6 @@ CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_ZYNQMP_NO_DDR=y # CONFIG_PSCI_RESET is not set # CONFIG_CMD_ZYNQMP is not set -CONFIG_SPL_TEXT_BASE=0xfffc0000 # CONFIG_EXPERT is not set # CONFIG_LEGACY_IMAGE_FORMAT is not set # CONFIG_BOARD_LATE_INIT is not set diff --git a/configs/xilinx_zynqmp_zc1232_revA_defconfig b/configs/xilinx_zynqmp_zc1232_revA_defconfig index beb6d43812..80a310fb1c 100644 --- a/configs/xilinx_zynqmp_zc1232_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1232_revA_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_CLOCK=100000000 # CONFIG_SPL_FS_FAT is not set # CONFIG_SPL_LIBDISK_SUPPORT is not set CONFIG_DEBUG_UART=y -CONFIG_SPL_TEXT_BASE=0xfffc0000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/xilinx_zynqmp_zc1254_revA_defconfig b/configs/xilinx_zynqmp_zc1254_revA_defconfig index 849a398edc..75ec572827 100644 --- a/configs/xilinx_zynqmp_zc1254_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1254_revA_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_CLOCK=100000000 # CONFIG_SPL_FS_FAT is not set # CONFIG_SPL_LIBDISK_SUPPORT is not set CONFIG_DEBUG_UART=y -CONFIG_SPL_TEXT_BASE=0xfffc0000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index a1e69b267f..ce1ea089ce 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -9,7 +9,6 @@ CONFIG_ZYNQMP_USB=y CONFIG_SPL_ZYNQMP_TWO_SDHCI=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y -CONFIG_SPL_TEXT_BASE=0xfffc0000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index 02f6d4a9bc..01c29c0e70 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_CLOCK=100000000 # CONFIG_SPL_LIBDISK_SUPPORT is not set CONFIG_ZYNQMP_USB=y CONFIG_DEBUG_UART=y -CONFIG_SPL_TEXT_BASE=0xfffc0000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig index c243064112..877f5b230d 100644 --- a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_ZYNQMP_USB=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y -CONFIG_SPL_TEXT_BASE=0xfffc0000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig index e964faba30..6f14234a59 100644 --- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig @@ -6,7 +6,6 @@ CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xff000000 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART=y -CONFIG_SPL_TEXT_BASE=0xfffc0000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig index 5856d9532d..f1970aadf4 100644 --- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig @@ -6,7 +6,6 @@ CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xff000000 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART=y -CONFIG_SPL_TEXT_BASE=0xfffc0000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/xilinx_zynqmp_zcu100_revC_defconfig b/configs/xilinx_zynqmp_zcu100_revC_defconfig index 1ec1bdc71a..cd7d2f5376 100644 --- a/configs/xilinx_zynqmp_zcu100_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu100_revC_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_ZYNQ_SDHCI_MAX_FREQ=15000000 CONFIG_ZYNQMP_USB=y CONFIG_DEBUG_UART=y -CONFIG_SPL_TEXT_BASE=0xfffc0000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig index b27887e347..371e6363db 100644 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig @@ -10,7 +10,6 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_ZYNQMP_USB=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y -CONFIG_SPL_TEXT_BASE=0xfffc0000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig index 7746305e6f..a0fb6c3586 100644 --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@ -10,7 +10,6 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_ZYNQMP_USB=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y -CONFIG_SPL_TEXT_BASE=0xfffc0000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index 3d58c01db6..db7c093d5e 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -10,7 +10,6 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_ZYNQMP_USB=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y -CONFIG_SPL_TEXT_BASE=0xfffc0000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/xilinx_zynqmp_zcu104_revA_defconfig b/configs/xilinx_zynqmp_zcu104_revA_defconfig index e21c34c63c..eacf75d9f8 100644 --- a/configs/xilinx_zynqmp_zcu104_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revA_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_ZYNQMP_USB=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y -CONFIG_SPL_TEXT_BASE=0xfffc0000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/xilinx_zynqmp_zcu104_revC_defconfig b/configs/xilinx_zynqmp_zcu104_revC_defconfig index 3d66d0abae..1c9a6d6f1e 100644 --- a/configs/xilinx_zynqmp_zcu104_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revC_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_ZYNQMP_USB=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y -CONFIG_SPL_TEXT_BASE=0xfffc0000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/xilinx_zynqmp_zcu106_revA_defconfig b/configs/xilinx_zynqmp_zcu106_revA_defconfig index 300d3b2220..1b685ca049 100644 --- a/configs/xilinx_zynqmp_zcu106_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu106_revA_defconfig @@ -10,7 +10,6 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_ZYNQMP_USB=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y -CONFIG_SPL_TEXT_BASE=0xfffc0000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/xilinx_zynqmp_zcu111_revA_defconfig b/configs/xilinx_zynqmp_zcu111_revA_defconfig index a4caaff6a1..74106d7ea8 100644 --- a/configs/xilinx_zynqmp_zcu111_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu111_revA_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_ZYNQMP_USB=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y -CONFIG_SPL_TEXT_BASE=0xfffc0000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/xilinx_zynqmp_zcu1275_revA_defconfig b/configs/xilinx_zynqmp_zcu1275_revA_defconfig index 4790061b36..b9110ca3b9 100644 --- a/configs/xilinx_zynqmp_zcu1275_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu1275_revA_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_CLOCK=100000000 # CONFIG_SPL_FS_FAT is not set # CONFIG_SPL_LIBDISK_SUPPORT is not set CONFIG_DEBUG_UART=y -CONFIG_SPL_TEXT_BASE=0xfffc0000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/xilinx_zynqmp_zcu1275_revB_defconfig b/configs/xilinx_zynqmp_zcu1275_revB_defconfig index ce2aa24daa..03372c77e6 100644 --- a/configs/xilinx_zynqmp_zcu1275_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu1275_revB_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_CLOCK=100000000 # CONFIG_SPL_FS_FAT is not set # CONFIG_SPL_LIBDISK_SUPPORT is not set CONFIG_DEBUG_UART=y -CONFIG_SPL_TEXT_BASE=0xfffc0000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y From 3796d133a0cba265ec7995f1143af44b672da63e Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Fri, 8 Mar 2019 13:13:26 +0530 Subject: [PATCH 02/85] xilinx: Add qspi boot command script for reference Thsi patch adds qspiboot command script for reference. This can be converetd into uboot script using mkimage and use for booting. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- board/xilinx/bootscripts/qspiboot.cmd | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 board/xilinx/bootscripts/qspiboot.cmd diff --git a/board/xilinx/bootscripts/qspiboot.cmd b/board/xilinx/bootscripts/qspiboot.cmd new file mode 100644 index 0000000000..c10341c4d6 --- /dev/null +++ b/board/xilinx/bootscripts/qspiboot.cmd @@ -0,0 +1,10 @@ +# This is an example file to generate boot.scr - a boot script for U-Boot +# This example only target for qspi boot, sameway it can be created for boot +# devices like nand. +# Generate boot.scr: +# ./tools/mkimage -c none -A arm -T script -d qspiboot.cmd boot.scr +# +# It requires a list of environment variables to be defined before load: +# fdt_addr, fdt_offset, fdt_size, kernel_addr, kernel_offset, kernel_size +# +sf probe 0 0 0 && sf read $fdt_addr $fdt_offset $fdt_size && sf read $kernel_addr $kernel_offset $kernel_size && booti $kernel_addr - $fdt_addr From 91a5964f3b683c285444b04bd58f94fb51453a8c Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Wed, 27 Mar 2019 10:48:33 +0530 Subject: [PATCH 03/85] xilinx: Add sd boot command script for reference This patch adds sdboot command script for reference. This can be converetd into uboot script using mkimage and use for booting. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- board/xilinx/bootscripts/sdboot.cmd | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 board/xilinx/bootscripts/sdboot.cmd diff --git a/board/xilinx/bootscripts/sdboot.cmd b/board/xilinx/bootscripts/sdboot.cmd new file mode 100644 index 0000000000..0031900db0 --- /dev/null +++ b/board/xilinx/bootscripts/sdboot.cmd @@ -0,0 +1,10 @@ +# This is an example file to generate boot.scr - a boot script for U-Boot +# This example only target for qspi boot, sameway it can be created for boot +# devices like nand. +# Generate boot.scr: +# ./tools/mkimage -c none -A arm -T script -d sdboot.cmd boot.scr +# +# It requires a list of environment variables used below to be defined +# before load +# +mmc dev $devnum && mmcinfo && run uenvboot || run sdroot$devnum;load mmc $devnum:$partid $fdt_addr system.dtb && load mmc $devnum:$partid $kernel_addr Image && booti $kernel_addr - $fdt_addr From 0317a2c8c299e15c3c133522cfb9787b50bb7c2a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 29 May 2019 15:04:51 +0200 Subject: [PATCH 04/85] arm64: zynqmp: Enable gpio hog support for zcu102 Gpio hogs are used for GT mux setup after power up. Signed-off-by: Michal Simek --- configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 + configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 + configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig index 371e6363db..52ee2f2a0b 100644 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig @@ -58,6 +58,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y CONFIG_DM_GPIO=y +CONFIG_GPIO_HOG=y CONFIG_XILINX_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig index a0fb6c3586..2b7cab8add 100644 --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@ -58,6 +58,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y CONFIG_DM_GPIO=y +CONFIG_GPIO_HOG=y CONFIG_XILINX_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index db7c093d5e..ce271b5a31 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -58,6 +58,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y CONFIG_DM_GPIO=y +CONFIG_GPIO_HOG=y CONFIG_XILINX_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y From dd3c7b6ea1022ef050bf4183ca6460e03c242d01 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 10 Sep 2019 11:15:05 +0200 Subject: [PATCH 05/85] arm64: zynqmp: Add u-boot,dm-pre-reloc to clk300 node This node is used by qspi driver for supporting qspi boot mode in SPL. Similar changes have beeen done by commit a9022b017a90 ("ARM64: zynqmp: Add u-boot,dm-pre-reloc to clk nodes") Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-clk.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi index a795efdc15..c70f85a430 100644 --- a/arch/arm/dts/zynqmp-clk.dtsi +++ b/arch/arm/dts/zynqmp-clk.dtsi @@ -38,6 +38,7 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; + u-boot,dm-pre-reloc; }; clk600: clk600 { From cbe3101018a13d7cdb52e96a08577a83f2a0dbc0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 10 Sep 2019 11:48:52 +0200 Subject: [PATCH 06/85] arm64: zynqmp: Enable SPI support in SPL for zcu104 It is enabling this mode but full boot is not validated yet. Signed-off-by: Michal Simek --- configs/xilinx_zynqmp_zcu104_revC_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/xilinx_zynqmp_zcu104_revC_defconfig b/configs/xilinx_zynqmp_zcu104_revC_defconfig index 1c9a6d6f1e..2f269009df 100644 --- a/configs/xilinx_zynqmp_zcu104_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revC_defconfig @@ -5,6 +5,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xff000000 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y CONFIG_ZYNQMP_USB=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y @@ -16,6 +18,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_ATF=y CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_MEMTEST=y From bfd092f9ca1cf0a547d9f7269490c1ee9a432f33 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 31 Jan 2019 17:28:14 +0530 Subject: [PATCH 07/85] arm64: versal: Define board_late_init for versal Define board_late_init which performs bootmode detection and prepares corresponding distro boot commaand sequence. Also disable it for mini platforms because simply there is no need to have it enabled. But also disable it for virtual platform because Qemu is not modelling this register space that's why travis testing would fail. This configuration should be reverted when mainline Qemu is updated. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- arch/arm/Kconfig | 1 + arch/arm/mach-versal/include/mach/hardware.h | 23 ++++ board/xilinx/versal/board.c | 111 +++++++++++++++++++ configs/xilinx_versal_mini_defconfig | 1 + configs/xilinx_versal_mini_emmc0_defconfig | 1 + configs/xilinx_versal_mini_emmc1_defconfig | 1 + configs/xilinx_versal_virt_defconfig | 1 + 7 files changed, 139 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3b0e315061..a93138aa0a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -980,6 +980,7 @@ config ARCH_VERSAL select DM_MMC if MMC select DM_SERIAL select OF_CONTROL + imply BOARD_LATE_INIT config ARCH_VF610 bool "Freescale Vybrid" diff --git a/arch/arm/mach-versal/include/mach/hardware.h b/arch/arm/mach-versal/include/mach/hardware.h index 23fbc3d8f5..e26beab2e9 100644 --- a/arch/arm/mach-versal/include/mach/hardware.h +++ b/arch/arm/mach-versal/include/mach/hardware.h @@ -51,3 +51,26 @@ struct rpu_regs { }; #define rpu_base ((struct rpu_regs *)VERSAL_RPU_BASEADDR) + +#define VERSAL_CRP_BASEADDR 0xF1260000 + +struct crp_regs { + u32 reserved0[128]; + u32 boot_mode_usr; +}; + +#define crp_base ((struct crp_regs *)VERSAL_CRP_BASEADDR) + +/* Bootmode setting values */ +#define BOOT_MODES_MASK 0x0000000F +#define QSPI_MODE_24BIT 0x00000001 +#define QSPI_MODE_32BIT 0x00000002 +#define SD_MODE 0x00000003 /* sd 0 */ +#define SD_MODE1 0x00000005 /* sd 1 */ +#define EMMC_MODE 0x00000006 +#define USB_MODE 0x00000007 +#define OSPI_MODE 0x00000008 +#define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */ +#define JTAG_MODE 0x00000000 +#define BOOT_MODE_USE_ALT 0x100 +#define BOOT_MODE_ALT_SHIFT 12 diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 90751477b5..b5ddd0c5ad 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -9,6 +9,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -65,6 +67,115 @@ int board_early_init_r(void) return 0; } +int board_late_init(void) +{ + u32 reg = 0; + u8 bootmode; + struct udevice *dev; + int bootseq = -1; + int bootseq_len = 0; + int env_targets_len = 0; + const char *mode; + char *new_targets; + char *env_targets; + + if (!(gd->flags & GD_FLG_ENV_DEFAULT)) { + debug("Saved variables - Skipping\n"); + return 0; + } + + reg = readl(&crp_base->boot_mode_usr); + + if (reg >> BOOT_MODE_ALT_SHIFT) + reg >>= BOOT_MODE_ALT_SHIFT; + + bootmode = reg & BOOT_MODES_MASK; + + puts("Bootmode: "); + switch (bootmode) { + case JTAG_MODE: + puts("JTAG_MODE\n"); + mode = "pxe dhcp"; + break; + case QSPI_MODE_24BIT: + puts("QSPI_MODE_24\n"); + mode = "xspi0"; + break; + case QSPI_MODE_32BIT: + puts("QSPI_MODE_32\n"); + mode = "xspi0"; + break; + case OSPI_MODE: + puts("OSPI_MODE\n"); + mode = "xspi0"; + break; + case EMMC_MODE: + puts("EMMC_MODE\n"); + mode = "mmc0"; + break; + case SD_MODE: + puts("SD_MODE\n"); + if (uclass_get_device_by_name(UCLASS_MMC, + "sdhci@f1040000", &dev)) { + puts("Boot from SD0 but without SD0 enabled!\n"); + return -1; + } + debug("mmc0 device found at %p, seq %d\n", dev, dev->seq); + + mode = "mmc"; + bootseq = dev->seq; + break; + case SD1_LSHFT_MODE: + puts("LVL_SHFT_"); + /* fall through */ + case SD_MODE1: + puts("SD_MODE1\n"); + if (uclass_get_device_by_name(UCLASS_MMC, + "sdhci@f1050000", &dev)) { + puts("Boot from SD1 but without SD1 enabled!\n"); + return -1; + } + debug("mmc1 device found at %p, seq %d\n", dev, dev->seq); + + mode = "mmc"; + bootseq = dev->seq; + break; + default: + mode = ""; + printf("Invalid Boot Mode:0x%x\n", bootmode); + break; + } + + if (bootseq >= 0) { + bootseq_len = snprintf(NULL, 0, "%i", bootseq); + debug("Bootseq len: %x\n", bootseq_len); + } + + /* + * One terminating char + one byte for space between mode + * and default boot_targets + */ + env_targets = env_get("boot_targets"); + if (env_targets) + env_targets_len = strlen(env_targets); + + new_targets = calloc(1, strlen(mode) + env_targets_len + 2 + + bootseq_len); + if (!new_targets) + return -ENOMEM; + + if (bootseq >= 0) + sprintf(new_targets, "%s%x %s", mode, bootseq, + env_targets ? env_targets : ""); + else + sprintf(new_targets, "%s %s", mode, + env_targets ? env_targets : ""); + + env_set("boot_targets", new_targets); + + return 0; +} + int dram_init_banksize(void) { fdtdec_setup_memory_banksize(); diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig index 012ba3ebbe..98759d0705 100644 --- a/configs/xilinx_versal_mini_defconfig +++ b/configs/xilinx_versal_mini_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_COUNTER_FREQUENCY=2720000 # CONFIG_LEGACY_IMAGE_FORMAT is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_BOARD_LATE_INIT is not set # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/xilinx_versal_mini_emmc0_defconfig b/configs/xilinx_versal_mini_emmc0_defconfig index 440035f53b..08d23243be 100644 --- a/configs/xilinx_versal_mini_emmc0_defconfig +++ b/configs/xilinx_versal_mini_emmc0_defconfig @@ -8,6 +8,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_COUNTER_FREQUENCY=2720000 CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_BOARD_LATE_INIT is not set # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/xilinx_versal_mini_emmc1_defconfig b/configs/xilinx_versal_mini_emmc1_defconfig index 07ec6ebd66..fef5cadd6e 100644 --- a/configs/xilinx_versal_mini_emmc1_defconfig +++ b/configs/xilinx_versal_mini_emmc1_defconfig @@ -8,6 +8,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_COUNTER_FREQUENCY=2720000 CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_BOARD_LATE_INIT is not set # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 3b07545ac4..75f8b98308 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -12,6 +12,7 @@ CONFIG_FIT_VERBOSE=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_BOOTDELAY=-1 CONFIG_SUPPORT_RAW_INITRD=y +# CONFIG_BOARD_LATE_INIT is not set # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y From 13210cd951046e828ecf3463f0087acbfb4f185e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 11 Sep 2019 09:20:41 +0200 Subject: [PATCH 08/85] arm64: versal: Also record versal name to versal fragment Just to make sure that also drivers with versal name are assigned to proper fragment. Signed-off-by: Michal Simek --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index c53656695a..3302f9f9d1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -404,6 +404,7 @@ M: Michal Simek S: Maintained T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/arm/mach-versal/ +N: (? From 26e054c943a7348904a8b432fc9a85185b0861c7 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Mon, 5 Aug 2019 15:54:59 +0530 Subject: [PATCH 09/85] arm64: versal: fpga: Add PL bit stream load support This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- board/xilinx/versal/board.c | 10 ++++++++ drivers/fpga/Kconfig | 9 +++++++ drivers/fpga/Makefile | 1 + drivers/fpga/versalpl.c | 51 +++++++++++++++++++++++++++++++++++++ drivers/fpga/xilinx.c | 8 +++++- include/versalpl.h | 20 +++++++++++++++ include/xilinx.h | 2 ++ 7 files changed, 100 insertions(+), 1 deletion(-) create mode 100644 drivers/fpga/versalpl.c create mode 100644 include/versalpl.h diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index b5ddd0c5ad..a2b00aa0b6 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -11,13 +11,23 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_FPGA_VERSALPL) +static xilinx_desc versalpl = XILINX_VERSAL_DESC; +#endif + int board_init(void) { printf("EL Level:\tEL%d\n", current_el()); +#if defined(CONFIG_FPGA_VERSALPL) + fpga_init(); + fpga_add(fpga_xilinx, &versalpl); +#endif + return 0; } diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 105a299812..fe398a1d49 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -56,6 +56,15 @@ config FPGA_ZYNQMPPL Enable FPGA driver for loading bitstream in BIT and BIN format on Xilinx Zynq UltraScale+ (ZynqMP) device. +config FPGA_VERSALPL + bool "Enable Xilinx FPGA driver for Versal" + depends on FPGA_XILINX + help + Enable FPGA driver for loading bitstream in PDI format on Xilinx + Versal device. PDI is a new programmable device image format for + Versal. The bitstream will only be generated as PDI for Versal + platform. + config FPGA_SPARTAN3 bool "Enable Spartan3 FPGA driver" depends on FPGA_XILINX diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 5a778c10e8..04e6480f20 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -6,6 +6,7 @@ obj-y += fpga.o obj-$(CONFIG_FPGA_SPARTAN2) += spartan2.o obj-$(CONFIG_FPGA_SPARTAN3) += spartan3.o +obj-$(CONFIG_FPGA_VERSALPL) += versalpl.o obj-$(CONFIG_FPGA_VIRTEX2) += virtex2.o obj-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o obj-$(CONFIG_FPGA_ZYNQMPPL) += zynqmppl.o diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c new file mode 100644 index 0000000000..69617a9b1d --- /dev/null +++ b/drivers/fpga/versalpl.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2019, Xilinx, Inc, + * Siva Durga Prasad Paladugu + */ + +#include +#include +#include +#include + +static ulong versal_align_dma_buffer(ulong *buf, u32 len) +{ + ulong *new_buf; + + if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) { + new_buf = (ulong *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN); + memcpy(new_buf, buf, len); + buf = new_buf; + } + + return (ulong)buf; +} + +static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize, + bitstream_type bstype) +{ + ulong bin_buf; + int ret; + u32 buf_lo, buf_hi; + u32 ret_payload[5]; + + bin_buf = versal_align_dma_buffer((ulong *)buf, bsize); + + debug("%s called!\n", __func__); + flush_dcache_range(bin_buf, bin_buf + bsize); + + buf_lo = lower_32_bits(bin_buf); + buf_hi = upper_32_bits(bin_buf); + + ret = versal_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo, + buf_hi, 0, ret_payload); + if (ret) + puts("PL FPGA LOAD fail\n"); + + return ret; +} + +struct xilinx_fpga_op versal_op = { + .load = versal_load, +}; diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index f5135504ee..4b0334b6be 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -226,7 +226,10 @@ int xilinx_info(xilinx_desc *desc) case xilinx_zynqmp: printf("ZynqMP PL\n"); break; - /* Add new family types here */ + case xilinx_versal: + printf("Versal PL\n"); + break; + /* Add new family types here */ default: printf ("Unknown family type, %d\n", desc->family); } @@ -257,6 +260,9 @@ int xilinx_info(xilinx_desc *desc) case csu_dma: printf("csu_dma configuration interface (ZynqMP)\n"); break; + case cfi: + printf("CFI configuration interface (Versal)\n"); + break; /* Add new interface types here */ default: printf ("Unsupported interface type, %d\n", desc->iface); diff --git a/include/versalpl.h b/include/versalpl.h new file mode 100644 index 0000000000..b94c82e6e6 --- /dev/null +++ b/include/versalpl.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2019 Xilinx, Inc, + * Siva Durga Prasad Paladugu + */ + +#ifndef _VERSALPL_H_ +#define _VERSALPL_H_ + +#include + +#define VERSAL_PM_LOAD_PDI 0x701 +#define VERSAL_PM_PDI_TYPE 0xF + +extern struct xilinx_fpga_op versal_op; + +#define XILINX_VERSAL_DESC \ +{ xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op } + +#endif /* _VERSALPL_H_ */ diff --git a/include/xilinx.h b/include/xilinx.h index af40befa52..ab4537becf 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -21,6 +21,7 @@ typedef enum { /* typedef xilinx_iface */ slave_selectmap, /* slave SelectMap (virtex2) */ devcfg, /* devcfg interface (zynq) */ csu_dma, /* csu_dma interface (zynqmp) */ + cfi, /* CFI interface(versal) */ max_xilinx_iface_type /* insert all new types before this */ } xilinx_iface; /* end, typedef xilinx_iface */ @@ -32,6 +33,7 @@ typedef enum { /* typedef xilinx_family */ xilinx_spartan3, /* Spartan-III Family */ xilinx_zynq, /* Zynq Family */ xilinx_zynqmp, /* ZynqMP Family */ + xilinx_versal, /* Versal Family */ max_xilinx_type /* insert all new types before this */ } xilinx_family; /* end, typedef xilinx_family */ From 085201c246ee37ac6cc8f7dd3ec2ad602537601e Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Mon, 5 Aug 2019 23:28:30 +0530 Subject: [PATCH 10/85] arm64: versal: Set initrd_high to as high as possible This patch is setting up the initrd_high to as high as possible by leaving max stack size for u-boot so that bigger rootfs can also be loaded by u-boot for booting kernel. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- arch/arm/Kconfig | 16 ++++++++++++++++ board/xilinx/versal/board.c | 6 ++++++ include/configs/xilinx_versal.h | 1 - 3 files changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a93138aa0a..33cb3e0658 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -462,6 +462,22 @@ config TPL_USE_ARCH_MEMSET Such implementation may be faster under some conditions but may increase the binary size. +config SET_STACK_SIZE + bool "Enable an option to set max stack size that can be used" + default y if ARCH_VERSAL + help + This will enable an option to set max stack size that can be + used by u-boot. + +config STACK_SIZE + hex "Define max stack size that can be used by u-boot" + depends on SET_STACK_SIZE + default 0x4000000 if ARCH_VERSAL + help + Defines Max stack size that can be used by u-boot so that the + initrd_high will be calculated as base stack pointer minus this + stack size. + config ARM64_SUPPORT_AARCH32 bool "ARM64 system support AArch32 execution state" depends on ARM64 diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index a2b00aa0b6..2b4edd8738 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -12,6 +12,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -88,6 +89,7 @@ int board_late_init(void) const char *mode; char *new_targets; char *env_targets; + ulong initrd_hi; if (!(gd->flags & GD_FLG_ENV_DEFAULT)) { debug("Saved variables - Skipping\n"); @@ -183,6 +185,10 @@ int board_late_init(void) env_set("boot_targets", new_targets); + initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE; + initrd_hi = round_down(initrd_hi, SZ_16M); + env_set_addr("initrd_high", (void *)initrd_hi); + return 0; } diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index 296f4502c6..1e0951c1d9 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -65,7 +65,6 @@ #define ENV_MEM_LAYOUT_SETTINGS \ "fdt_high=10000000\0" \ - "initrd_high=10000000\0" \ "fdt_addr_r=0x40000000\0" \ "pxefile_addr_r=0x10000000\0" \ "kernel_addr_r=0x18000000\0" \ From a69814c815b9a1a027f461ef26dbe7b2b8e258e4 Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Tue, 20 Aug 2019 09:30:57 +0530 Subject: [PATCH 11/85] arm64: zynqmp: Set initrd_high to as high as possible This patch is setting up the initrd_high to as high as possible by leaving max stack size for u-boot so that bigger rootfs can also be loaded by u-boot for booting kernel. Signed-off-by: T Karthik Reddy Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- arch/arm/Kconfig | 4 ++-- board/xilinx/zynqmp/zynqmp.c | 6 ++++++ include/configs/xilinx_zynqmp.h | 1 - 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 33cb3e0658..257a98d795 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -464,7 +464,7 @@ config TPL_USE_ARCH_MEMSET config SET_STACK_SIZE bool "Enable an option to set max stack size that can be used" - default y if ARCH_VERSAL + default y if ARCH_VERSAL || ARCH_ZYNQMP help This will enable an option to set max stack size that can be used by u-boot. @@ -472,7 +472,7 @@ config SET_STACK_SIZE config STACK_SIZE hex "Define max stack size that can be used by u-boot" depends on SET_STACK_SIZE - default 0x4000000 if ARCH_VERSAL + default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP help Defines Max stack size that can be used by u-boot so that the initrd_high will be calculated as base stack pointer minus this diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index d649daba96..0c331e3322 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "pm_cfg_obj.h" @@ -530,6 +531,7 @@ int board_late_init(void) char *new_targets; char *env_targets; int ret; + ulong initrd_hi; #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD) usb_ether_init(); @@ -647,6 +649,10 @@ int board_late_init(void) env_set("boot_targets", new_targets); + initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE; + initrd_hi = round_down(initrd_hi, SZ_16M); + env_set_addr("initrd_high", (void *)initrd_hi); + reset_reason(); return 0; diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index a1c55a8306..d42696ba12 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -109,7 +109,6 @@ #define ENV_MEM_LAYOUT_SETTINGS \ "fdt_high=10000000\0" \ - "initrd_high=10000000\0" \ "fdt_addr_r=0x40000000\0" \ "pxefile_addr_r=0x10000000\0" \ "kernel_addr_r=0x18000000\0" \ From aef149e9dd3d8a99840b0a7e5af06565cde3ad74 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 29 Apr 2019 09:39:09 -0700 Subject: [PATCH 12/85] arm64: versal: Enable memory mapping via DT Code reads DT and setup MMU table based on memory node. This will ensure that only DT needs to be changed. Signed-off-by: Michal Simek --- arch/arm/mach-versal/cpu.c | 36 +++++++++++++------ arch/arm/mach-versal/include/mach/sys_proto.h | 1 + board/xilinx/versal/board.c | 9 ++++- 3 files changed, 35 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index 70c1908ec4..dc6a9205be 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -12,14 +12,15 @@ DECLARE_GLOBAL_DATA_PTR; -static struct mm_region versal_mem_map[] = { +#define VERSAL_MEM_MAP_USED 6 + +#define DRAM_BANKS CONFIG_NR_DRAM_BANKS + +/* +1 is end of list which needs to be empty */ +#define VERSAL_MEM_MAP_MAX (VERSAL_MEM_MAP_USED + DRAM_BANKS + 1) + +static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = { { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { .virt = 0x80000000UL, .phys = 0x80000000UL, .size = 0x70000000UL, @@ -59,12 +60,27 @@ static struct mm_region versal_mem_map[] = { .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, } }; +void mem_map_fill(void) +{ + int banks = VERSAL_MEM_MAP_USED; + + for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + /* Zero size means no more DDR that's this is end */ + if (!gd->bd->bi_dram[i].size) + break; + + versal_mem_map[banks].virt = gd->bd->bi_dram[i].start; + versal_mem_map[banks].phys = gd->bd->bi_dram[i].start; + versal_mem_map[banks].size = gd->bd->bi_dram[i].size; + versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE; + banks = banks + 1; + } +} + struct mm_region *mem_map = versal_mem_map; u64 get_page_table_size(void) diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h index 1dc7bf6656..05934c28d6 100644 --- a/arch/arm/mach-versal/include/mach/sys_proto.h +++ b/arch/arm/mach-versal/include/mach/sys_proto.h @@ -9,3 +9,4 @@ enum { }; void tcm_init(u8 mode); +void mem_map_fill(void); diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 2b4edd8738..5718e1aa7e 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -194,7 +195,13 @@ int board_late_init(void) int dram_init_banksize(void) { - fdtdec_setup_memory_banksize(); + int ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + return ret; + + mem_map_fill(); return 0; } From 3899ebdd88f08929fd4568ce1c924176e6aa4365 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 11 Sep 2019 09:39:59 +0200 Subject: [PATCH 13/85] arm64: zynqmp: Provide a Kconfig option to disable OCM and TCM MMU mapping This patch provides an option to enable/disable OCM and TCM memory into MMU table with corresponding memory attributes. The same change was done for ZynqMP by commit 189bec47ab1f ("arm64: zynqmp: Provide a Kconfig option to define OCM and TCM in MMU") Signed-off-by: Michal Simek --- arch/arm/mach-versal/Kconfig | 7 +++++++ arch/arm/mach-versal/cpu.c | 25 +++++++++++++++++-------- 2 files changed, 24 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig index 26d1756371..06a0352924 100644 --- a/arch/arm/mach-versal/Kconfig +++ b/arch/arm/mach-versal/Kconfig @@ -54,4 +54,11 @@ config SYS_MEM_RSVD_FOR_MMU MMU table than the one which will be allocated during relocation. +config DEFINE_TCM_OCM_MMAP + bool "Define TCM and OCM memory in MMU Table" + default y if MP + help + This option if enabled defines the TCM and OCM memory and its + memory attributes in MMU table entry. + endif diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index dc6a9205be..f0d047d323 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -12,12 +12,18 @@ DECLARE_GLOBAL_DATA_PTR; -#define VERSAL_MEM_MAP_USED 6 +#define VERSAL_MEM_MAP_USED 5 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS +#if defined(CONFIG_DEFINE_TCM_OCM_MMAP) +#define TCM_MAP 1 +#else +#define TCM_MAP 0 +#endif + /* +1 is end of list which needs to be empty */ -#define VERSAL_MEM_MAP_MAX (VERSAL_MEM_MAP_USED + DRAM_BANKS + 1) +#define VERSAL_MEM_MAP_MAX (VERSAL_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1) static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = { { @@ -34,12 +40,6 @@ static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = { .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0xffe00000UL, - .phys = 0xffe00000UL, - .size = 0x00200000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE }, { .virt = 0x400000000UL, .phys = 0x400000000UL, @@ -67,6 +67,15 @@ void mem_map_fill(void) { int banks = VERSAL_MEM_MAP_USED; +#if defined(CONFIG_DEFINE_TCM_OCM_MMAP) + versal_mem_map[banks].virt = 0xffe00000UL; + versal_mem_map[banks].phys = 0xffe00000UL; + versal_mem_map[banks].size = 0x00200000UL; + versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE; + banks = banks + 1; +#endif + for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { /* Zero size means no more DDR that's this is end */ if (!gd->bd->bi_dram[i].size) From 14723ed544f42c4ea8913eb151c1e9c52dd70c88 Mon Sep 17 00:00:00 2001 From: Rajan Vaja Date: Fri, 15 Feb 2019 04:45:32 -0800 Subject: [PATCH 14/85] zynqmp: firmware: Add Xilinx ZynqMP firmware driver Add simple ZynqMP firmware drive to populate child nodes under zynqmp_firmware DT node. Signed-off-by: Rajan Vaja Signed-off-by: Michal Simek --- MAINTAINERS | 1 + drivers/clk/Kconfig | 1 + drivers/firmware/Kconfig | 10 ++++++++++ drivers/firmware/Makefile | 1 + drivers/firmware/firmware-zynqmp.c | 15 +++++++++++++++ 5 files changed, 28 insertions(+) create mode 100644 drivers/firmware/firmware-zynqmp.c diff --git a/MAINTAINERS b/MAINTAINERS index 3302f9f9d1..59c766f206 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -443,6 +443,7 @@ S: Maintained T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/arm/mach-zynqmp/ F: drivers/clk/clk_zynqmp.c +F: driver/firmware/firmware-zynqmp.c F: drivers/fpga/zynqpl.c F: drivers/gpio/zynq_gpio.c F: drivers/i2c/i2c-cdns.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 95fe0aea2c..305cbd96f1 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -113,6 +113,7 @@ config CLK_ZYNQ config CLK_ZYNQMP bool "Enable clock driver support for ZynqMP" depends on ARCH_ZYNQMP + select ZYNQMP_FIRMWARE help This clock driver adds support for clock realted settings for ZynqMP platform. diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index 873bc8c796..b70a206355 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -26,3 +26,13 @@ config TI_SCI_PROTOCOL This protocol library is used by client drivers to use the features provided by the system controller. + +config ZYNQMP_FIRMWARE + bool "ZynqMP Firmware interface" + select FIRMWARE + help + Firmware interface driver is used by different + drivers to communicate with the firmware for + various platform management services. + Say yes to enable ZynqMP firmware interface driver. + If in doubt, say N. diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile index 6c3e129685..a0c250a473 100644 --- a/drivers/firmware/Makefile +++ b/drivers/firmware/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_FIRMWARE) += firmware-uclass.o obj-$(CONFIG_$(SPL_)ARM_PSCI_FW) += psci.o obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o obj-$(CONFIG_SANDBOX) += firmware-sandbox.o +obj-$(CONFIG_ZYNQMP_FIRMWARE) += firmware-zynqmp.o diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c new file mode 100644 index 0000000000..b36eda1b04 --- /dev/null +++ b/drivers/firmware/firmware-zynqmp.c @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +static const struct udevice_id zynqmp_firmware_ids[] = { + { .compatible = "xlnx,zynqmp-firmware" }, + { } +}; + +U_BOOT_DRIVER(zynqmp_firmware) = { + .id = UCLASS_FIRMWARE, + .name = "zynqmp-firmware", + .probe = dm_scan_fdt_dev, + .of_match = zynqmp_firmware_ids, +}; From 37d53180cd289cae5776a38891794099e8a954d0 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Mon, 22 Apr 2019 14:45:04 +0530 Subject: [PATCH 15/85] arm64: versal: Define configs related to USB DFU functionality This patch defines macros required for DFU functionality for Xilinx Versal platform. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- include/configs/xilinx_versal.h | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index 1e0951c1d9..35153e8cd2 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -52,6 +52,26 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_MAXARGS 64 +#if defined(CONFIG_CMD_DFU) +#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000 +#define DFU_DEFAULT_POLL_TIMEOUT 300 +#define CONFIG_THOR_RESET_OFF +#define DFU_ALT_INFO_RAM \ + "dfu_ram_info=" \ + "setenv dfu_alt_info " \ + "Image ram $kernel_addr_r $kernel_size_r\\\\;" \ + "system.dtb ram $fdt_addr_r $fdt_size_r\0" \ + "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ + "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" + +#define DFU_ALT_INFO \ + DFU_ALT_INFO_RAM +#endif + +#if !defined(DFU_ALT_INFO) +# define DFU_ALT_INFO +#endif + /* Ethernet driver */ #if defined(CONFIG_ZYNQ_GEM) # define CONFIG_NET_MULTI @@ -66,8 +86,10 @@ #define ENV_MEM_LAYOUT_SETTINGS \ "fdt_high=10000000\0" \ "fdt_addr_r=0x40000000\0" \ + "fdt_size_r=0x400000\0" \ "pxefile_addr_r=0x10000000\0" \ "kernel_addr_r=0x18000000\0" \ + "kernel_size_r=0x10000000\0" \ "scriptaddr=0x02000000\0" \ "ramdisk_addr_r=0x02100000\0" \ "script_offset_f=0x3f80000\0" \ @@ -105,7 +127,8 @@ #ifndef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ - BOOTENV + BOOTENV \ + DFU_ALT_INFO #endif #endif /* __XILINX_VERSAL_H */ From 3d865acb70e2b9420c1985f78ba4e829e34bd02e Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 25 Jun 2019 17:13:14 +0530 Subject: [PATCH 16/85] arm64: versal: Add new jtag distro boot command This patch adds new jtag distro boot command to look for bootscript file in DDR and execute it first incase of jtag bootmode. This patch also updates scriptaddr to 512MB as there is high of script corruption incase of bigger kernel image. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- board/xilinx/versal/board.c | 2 +- include/configs/xilinx_versal.h | 11 ++++++++++- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 5718e1aa7e..dcfb8878c6 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -108,7 +108,7 @@ int board_late_init(void) switch (bootmode) { case JTAG_MODE: puts("JTAG_MODE\n"); - mode = "pxe dhcp"; + mode = "jtag pxe dhcp"; break; case QSPI_MODE_24BIT: puts("QSPI_MODE_24\n"); diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index 35153e8cd2..2f1cddbb6f 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -90,7 +90,7 @@ "pxefile_addr_r=0x10000000\0" \ "kernel_addr_r=0x18000000\0" \ "kernel_size_r=0x10000000\0" \ - "scriptaddr=0x02000000\0" \ + "scriptaddr=0x20000000\0" \ "ramdisk_addr_r=0x02100000\0" \ "script_offset_f=0x3f80000\0" \ "script_size_f=0x80000\0" @@ -115,7 +115,16 @@ #define BOOTENV_DEV_NAME_XSPI(devtypeu, devtypel, instance) \ "xspi " +#define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na) + +#define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \ + "bootcmd_jtag=source $scriptaddr; echo SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \ + "jtag " + #define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_JTAG(func) \ BOOT_TARGET_DEVICES_MMC(func) \ BOOT_TARGET_DEVICES_XSPI(func) \ func(PXE, pxe, na) \ From f0c16cd6f3bc5cff132c13b890f911b9a10dcfaf Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Thu, 11 Jul 2019 16:07:57 +0530 Subject: [PATCH 17/85] arm64: versal: Add new dfu usb distro boot command This patch adds new dfu usb distro boot command to look for bootscript from dfu-util and runs it. Signed-off-by: T Karthik Reddy --- board/xilinx/versal/board.c | 4 ++++ include/configs/xilinx_versal.h | 11 +++++++++++ 2 files changed, 15 insertions(+) diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index dcfb8878c6..abdd580c01 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -106,6 +106,10 @@ int board_late_init(void) puts("Bootmode: "); switch (bootmode) { + case USB_MODE: + puts("USB_MODE\n"); + mode = "dfu_usb"; + break; case JTAG_MODE: puts("JTAG_MODE\n"); mode = "jtag pxe dhcp"; diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index 2f1cddbb6f..67f5739555 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -123,10 +123,21 @@ #define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \ "jtag " +#define BOOT_TARGET_DEVICES_DFU_USB(func) func(DFU_USB, dfu_usb, 0) + +#define BOOTENV_DEV_DFU_USB(devtypeu, devtypel, instance) \ + "bootcmd_dfu_usb=setenv dfu_alt_info boot.scr ram $scriptaddr " \ + "$script_size_f; dfu 0 ram 0 && source $scriptaddr; " \ + "echo SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_DFU_USB(devtypeu, devtypel, instance) \ + "dfu_usb " + #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_DEVICES_JTAG(func) \ BOOT_TARGET_DEVICES_MMC(func) \ BOOT_TARGET_DEVICES_XSPI(func) \ + BOOT_TARGET_DEVICES_DFU_USB(func) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) From e76bc3cbc01537510c8aaffbd5d98f97f2609a4d Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Mon, 5 Aug 2019 16:18:56 +0530 Subject: [PATCH 18/85] arm64: versal: Change boot script offset address in versal With the current boot script offset address in qspi is being overlaped by BOOT.BIN as it is over 90MB with fpga included. So moving the script offset address to end of flash after "bootenv" mtd partition. Here we are considering qspi flash size >= 128Mbytes on versal and left 512Kbytes space to save boot.scr script. Signed-off-by: T Karthik Reddy Signed-off-by: Michal Simek --- include/configs/xilinx_versal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index 67f5739555..f426127edc 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -92,7 +92,7 @@ "kernel_size_r=0x10000000\0" \ "scriptaddr=0x20000000\0" \ "ramdisk_addr_r=0x02100000\0" \ - "script_offset_f=0x3f80000\0" \ + "script_offset_f=0x7F80000\0" \ "script_size_f=0x80000\0" #if defined(CONFIG_MMC_SDHCI_ZYNQ) From 81764f5361dbd95a5468435faedbff0bc06155fe Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 25 Jun 2019 17:41:08 +0530 Subject: [PATCH 19/85] arm64: zynqmp: Update scriptaddr value to 512MB This patch updates scriptaddr value to 512MB as having it at 32MB has high chance of script corruption incase of bigger kernel. Be aware that 512MB is used for SPL malloc area that's why images should be loaded after SPL (the best after u-boot relocation). Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- include/configs/xilinx_zynqmp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index d42696ba12..1c0ffe5738 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -112,7 +112,7 @@ "fdt_addr_r=0x40000000\0" \ "pxefile_addr_r=0x10000000\0" \ "kernel_addr_r=0x18000000\0" \ - "scriptaddr=0x02000000\0" \ + "scriptaddr=0x20000000\0" \ "ramdisk_addr_r=0x02100000\0" \ "script_offset_f=0x3e80000\0" \ "script_size_f=0x80000\0" \ From 5d2274c00f068bf1d3b37e8146d78582325f482a Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 25 Jun 2019 17:41:09 +0530 Subject: [PATCH 20/85] arm64: zynqmp: Add new jtag distro boot command This patch adds new jtag distro boot command to look for bootscript file in DDR and execute it first incase of jtag bootmode. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- board/xilinx/zynqmp/zynqmp.c | 2 +- include/configs/xilinx_zynqmp.h | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 0c331e3322..f36d49fded 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -564,7 +564,7 @@ int board_late_init(void) break; case JTAG_MODE: puts("JTAG_MODE\n"); - mode = "pxe dhcp"; + mode = "jtag pxe dhcp"; env_set("modeboot", "jtagboot"); break; case QSPI_MODE_24BIT: diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 1c0ffe5738..ee1ceebf12 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -175,7 +175,16 @@ #define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ #devtypel #instance " " +#define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na) + +#define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \ + "bootcmd_jtag=source $scriptaddr; echo SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \ + "jtag " + #define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_JTAG(func) \ BOOT_TARGET_DEVICES_MMC(func) \ BOOT_TARGET_DEVICES_QSPI(func) \ BOOT_TARGET_DEVICES_NAND(func) \ From 74969a074c37ade94ea628b9660c403658d504af Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 25 Apr 2019 11:30:22 -0700 Subject: [PATCH 21/85] net: gem: Remove DECLARE_GLOBAL_DATA_PTR from gem driver GD is not used anywhere that's why there is no reason to have this macro in the driver. Signed-off-by: Michal Simek --- drivers/net/zynq_gem.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 033efb8195..a2ed50fa1e 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -26,8 +26,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* Bit/mask specification */ #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ From 1ff8bdb8d36692760481cc939770a401d26ddac0 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 25 Jul 2019 23:07:59 -0700 Subject: [PATCH 22/85] net: zynq_gem: Add new versal compatible string This patch adds new versal compatible string to GEM driver for Versal platform. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/net/zynq_gem.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index a2ed50fa1e..a35ecab79e 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -751,6 +751,7 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev) } static const struct udevice_id zynq_gem_ids[] = { + { .compatible = "cdns,versal-gem" }, { .compatible = "cdns,zynqmp-gem" }, { .compatible = "cdns,zynq-gem" }, { .compatible = "cdns,gem" }, From 95105089afe2a204883e9c0f4c2c694469ec31d1 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Sun, 23 Jun 2019 12:24:57 +0530 Subject: [PATCH 23/85] clk: versal: Add clock driver support This patch adds clock driver support for Versal platform. The clock driver queries and performs clock operations using PLM firmware by communicating with it using SMC calls. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- arch/arm/mach-versal/cpu.c | 25 + arch/arm/mach-versal/include/mach/sys_proto.h | 60 ++ drivers/clk/Kconfig | 8 + drivers/clk/Makefile | 1 + drivers/clk/clk_versal.c | 746 ++++++++++++++++++ drivers/firmware/firmware-zynqmp.c | 1 + 6 files changed, 841 insertions(+) create mode 100644 drivers/clk/clk_versal.c diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index f0d047d323..db96225827 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -121,3 +121,28 @@ void *board_fdt_blob_setup(void) return fw_dtb; } #endif + +int versal_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2, + u32 arg3, u32 *ret_payload) +{ + struct pt_regs regs; + + if (current_el() == 3) + return 0; + + regs.regs[0] = PM_SIP_SVC | api_id; + regs.regs[1] = ((u64)arg1 << 32) | arg0; + regs.regs[2] = ((u64)arg3 << 32) | arg2; + + smc_call(®s); + + if (ret_payload) { + ret_payload[0] = (u32)regs.regs[0]; + ret_payload[1] = upper_32_bits(regs.regs[0]); + ret_payload[2] = (u32)regs.regs[1]; + ret_payload[3] = upper_32_bits(regs.regs[1]); + ret_payload[4] = (u32)regs.regs[2]; + } + + return regs.regs[0]; +} diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h index 05934c28d6..2f5ad02bf4 100644 --- a/arch/arm/mach-versal/include/mach/sys_proto.h +++ b/arch/arm/mach-versal/include/mach/sys_proto.h @@ -8,5 +8,65 @@ enum { TCM_SPLIT, }; +enum pm_api_id { + PM_GET_API_VERSION = 1, + PM_SET_CONFIGURATION, + PM_GET_NODE_STATUS, + PM_GET_OPERATING_CHARACTERISTIC, + PM_REGISTER_NOTIFIER, + PM_REQUEST_SUSPEND, + PM_SELF_SUSPEND, + PM_FORCE_POWERDOWN, + PM_ABORT_SUSPEND, + PM_REQUEST_WAKEUP, + PM_SET_WAKEUP_SOURCE, + PM_SYSTEM_SHUTDOWN, + PM_REQUEST_NODE, + PM_RELEASE_NODE, + PM_SET_REQUIREMENT, + PM_SET_MAX_LATENCY, + PM_RESET_ASSERT, + PM_RESET_GET_STATUS, + PM_MMIO_WRITE, + PM_MMIO_READ, + PM_PM_INIT_FINALIZE, + PM_FPGA_LOAD, + PM_FPGA_GET_STATUS, + PM_GET_CHIPID, + PM_SECURE_SHA = 26, + PM_SECURE_RSA, + PM_PINCTRL_REQUEST, + PM_PINCTRL_RELEASE, + PM_PINCTRL_GET_FUNCTION, + PM_PINCTRL_SET_FUNCTION, + PM_PINCTRL_CONFIG_PARAM_GET, + PM_PINCTRL_CONFIG_PARAM_SET, + PM_IOCTL, + PM_QUERY_DATA, + PM_CLOCK_ENABLE, + PM_CLOCK_DISABLE, + PM_CLOCK_GETSTATE, + PM_CLOCK_SETDIVIDER, + PM_CLOCK_GETDIVIDER, + PM_CLOCK_SETRATE, + PM_CLOCK_GETRATE, + PM_CLOCK_SETPARENT, + PM_CLOCK_GETPARENT, + PM_SECURE_IMAGE, + PM_FPGA_READ = 46, + PM_SECURE_AES, + PM_CLOCK_PLL_GETPARAM = 49, + PM_REGISTER_ACCESS = 52, + PM_EFUSE_ACCESS, + PM_FEATURE_CHECK = 63, + PM_API_MAX, +}; + +#define PM_SIP_SVC 0xC2000000 +#define PAYLOAD_ARG_CNT 4U + void tcm_init(u8 mode); void mem_map_fill(void); + +int versal_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2, + u32 arg3, u32 *ret_payload); diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 305cbd96f1..0035f0a9c6 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -95,6 +95,14 @@ config CLK_HSDK help Enable this to support the cgu clocks on Synopsys ARC HSDK +config CLK_VERSAL + bool "Enable clock driver support for Versal" + depends on ARCH_VERSAL + select ZYNQMP_FIRMWARE + help + This clock driver adds support for clock realted settings for + Versal platform. + config CLK_VEXPRESS_OSC bool "Enable driver for Arm Versatile Express OSC clock generators" depends on CLK && VEXPRESS_CONFIG diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 68aabe1ca9..d7cea3b8bf 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -43,3 +43,4 @@ obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o obj-$(CONFIG_STM32H7) += clk_stm32h7.o obj-$(CONFIG_CLK_TI_SCI) += clk-ti-sci.o +obj-$(CONFIG_CLK_VERSAL) += clk_versal.o diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c new file mode 100644 index 0000000000..df87645774 --- /dev/null +++ b/drivers/clk/clk_versal.c @@ -0,0 +1,746 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Xilinx, Inc. + * Siva Durga Prasad Paladugu + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_PARENT 100 +#define MAX_NODES 6 +#define MAX_NAME_LEN 50 + +#define CLK_TYPE_SHIFT 2 + +#define PM_API_PAYLOAD_LEN 3 + +#define NA_PARENT 0xFFFFFFFF +#define DUMMY_PARENT 0xFFFFFFFE + +#define CLK_TYPE_FIELD_LEN 4 +#define CLK_TOPOLOGY_NODE_OFFSET 16 +#define NODES_PER_RESP 3 + +#define CLK_TYPE_FIELD_MASK 0xF +#define CLK_FLAG_FIELD_MASK GENMASK(21, 8) +#define CLK_TYPE_FLAG_FIELD_MASK GENMASK(31, 24) +#define CLK_TYPE_FLAG2_FIELD_MASK GENMASK(7, 4) +#define CLK_TYPE_FLAG_BITS 8 + +#define CLK_PARENTS_ID_LEN 16 +#define CLK_PARENTS_ID_MASK 0xFFFF + +#define END_OF_TOPOLOGY_NODE 1 +#define END_OF_PARENTS 1 + +#define CLK_VALID_MASK 0x1 +#define NODE_CLASS_SHIFT 26U +#define NODE_SUBCLASS_SHIFT 20U +#define NODE_TYPE_SHIFT 14U +#define NODE_INDEX_SHIFT 0U + +#define CLK_GET_NAME_RESP_LEN 16 +#define CLK_GET_TOPOLOGY_RESP_WORDS 3 +#define CLK_GET_PARENTS_RESP_WORDS 3 +#define CLK_GET_ATTR_RESP_WORDS 1 + +#define NODE_SUBCLASS_CLOCK_PLL 1 +#define NODE_SUBCLASS_CLOCK_OUT 2 +#define NODE_SUBCLASS_CLOCK_REF 3 + +#define NODE_CLASS_CLOCK 2 +#define NODE_CLASS_MASK 0x3F + +#define CLOCK_NODE_TYPE_MUX 1 +#define CLOCK_NODE_TYPE_DIV 4 +#define CLOCK_NODE_TYPE_GATE 6 + +enum pm_query_id { + PM_QID_INVALID, + PM_QID_CLOCK_GET_NAME, + PM_QID_CLOCK_GET_TOPOLOGY, + PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS, + PM_QID_CLOCK_GET_PARENTS, + PM_QID_CLOCK_GET_ATTRIBUTES, + PM_QID_PINCTRL_GET_NUM_PINS, + PM_QID_PINCTRL_GET_NUM_FUNCTIONS, + PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS, + PM_QID_PINCTRL_GET_FUNCTION_NAME, + PM_QID_PINCTRL_GET_FUNCTION_GROUPS, + PM_QID_PINCTRL_GET_PIN_GROUPS, + PM_QID_CLOCK_GET_NUM_CLOCKS, + PM_QID_CLOCK_GET_MAX_DIVISOR, +}; + +enum clk_type { + CLK_TYPE_OUTPUT, + CLK_TYPE_EXTERNAL, +}; + +struct clock_parent { + char name[MAX_NAME_LEN]; + int id; + u32 flag; +}; + +struct clock_topology { + u32 type; + u32 flag; + u32 type_flag; +}; + +struct versal_clock { + char clk_name[MAX_NAME_LEN]; + u32 valid; + enum clk_type type; + struct clock_topology node[MAX_NODES]; + u32 num_nodes; + struct clock_parent parent[MAX_PARENT]; + u32 num_parents; + u32 clk_id; +}; + +struct versal_clk_priv { + struct versal_clock *clk; +}; + +static ulong alt_ref_clk; +static ulong pl_alt_ref_clk; +static ulong ref_clk; + +struct versal_pm_query_data { + u32 qid; + u32 arg1; + u32 arg2; + u32 arg3; +}; + +static struct versal_clock *clock; +static unsigned int clock_max_idx; + +#define PM_QUERY_DATA 35 + +static int versal_pm_query(struct versal_pm_query_data qdata, u32 *ret_payload) +{ + struct pt_regs regs; + + regs.regs[0] = PM_SIP_SVC | PM_QUERY_DATA; + regs.regs[1] = ((u64)qdata.arg1 << 32) | qdata.qid; + regs.regs[2] = ((u64)qdata.arg3 << 32) | qdata.arg2; + + smc_call(®s); + + if (ret_payload) { + ret_payload[0] = (u32)regs.regs[0]; + ret_payload[1] = upper_32_bits(regs.regs[0]); + ret_payload[2] = (u32)regs.regs[1]; + ret_payload[3] = upper_32_bits(regs.regs[1]); + ret_payload[4] = (u32)regs.regs[2]; + } + + return qdata.qid == PM_QID_CLOCK_GET_NAME ? 0 : regs.regs[0]; +} + +static inline int versal_is_valid_clock(u32 clk_id) +{ + if (clk_id >= clock_max_idx) + return -ENODEV; + + return clock[clk_id].valid; +} + +static int versal_get_clock_name(u32 clk_id, char *clk_name) +{ + int ret; + + ret = versal_is_valid_clock(clk_id); + if (ret == 1) { + strncpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN); + return 0; + } + + return ret == 0 ? -EINVAL : ret; +} + +static int versal_get_clock_type(u32 clk_id, u32 *type) +{ + int ret; + + ret = versal_is_valid_clock(clk_id); + if (ret == 1) { + *type = clock[clk_id].type; + return 0; + } + + return ret == 0 ? -EINVAL : ret; +} + +static int versal_pm_clock_get_num_clocks(u32 *nclocks) +{ + struct versal_pm_query_data qdata = {0}; + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + qdata.qid = PM_QID_CLOCK_GET_NUM_CLOCKS; + + ret = versal_pm_query(qdata, ret_payload); + *nclocks = ret_payload[1]; + + return ret; +} + +static int versal_pm_clock_get_name(u32 clock_id, char *name) +{ + struct versal_pm_query_data qdata = {0}; + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + qdata.qid = PM_QID_CLOCK_GET_NAME; + qdata.arg1 = clock_id; + + ret = versal_pm_query(qdata, ret_payload); + if (ret) + return ret; + memcpy(name, ret_payload, CLK_GET_NAME_RESP_LEN); + + return 0; +} + +static int versal_pm_clock_get_topology(u32 clock_id, u32 index, u32 *topology) +{ + struct versal_pm_query_data qdata = {0}; + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + qdata.qid = PM_QID_CLOCK_GET_TOPOLOGY; + qdata.arg1 = clock_id; + qdata.arg2 = index; + + ret = versal_pm_query(qdata, ret_payload); + memcpy(topology, &ret_payload[1], CLK_GET_TOPOLOGY_RESP_WORDS * 4); + + return ret; +} + +static int versal_pm_clock_get_parents(u32 clock_id, u32 index, u32 *parents) +{ + struct versal_pm_query_data qdata = {0}; + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + qdata.qid = PM_QID_CLOCK_GET_PARENTS; + qdata.arg1 = clock_id; + qdata.arg2 = index; + + ret = versal_pm_query(qdata, ret_payload); + memcpy(parents, &ret_payload[1], CLK_GET_PARENTS_RESP_WORDS * 4); + + return ret; +} + +static int versal_pm_clock_get_attributes(u32 clock_id, u32 *attr) +{ + struct versal_pm_query_data qdata = {0}; + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + qdata.qid = PM_QID_CLOCK_GET_ATTRIBUTES; + qdata.arg1 = clock_id; + + ret = versal_pm_query(qdata, ret_payload); + memcpy(attr, &ret_payload[1], CLK_GET_ATTR_RESP_WORDS * 4); + + return ret; +} + +static int __versal_clock_get_topology(struct clock_topology *topology, + u32 *data, u32 *nnodes) +{ + int i; + + for (i = 0; i < PM_API_PAYLOAD_LEN; i++) { + if (!(data[i] & CLK_TYPE_FIELD_MASK)) + return END_OF_TOPOLOGY_NODE; + topology[*nnodes].type = data[i] & CLK_TYPE_FIELD_MASK; + topology[*nnodes].flag = FIELD_GET(CLK_FLAG_FIELD_MASK, + data[i]); + topology[*nnodes].type_flag = + FIELD_GET(CLK_TYPE_FLAG_FIELD_MASK, data[i]); + topology[*nnodes].type_flag |= + FIELD_GET(CLK_TYPE_FLAG2_FIELD_MASK, data[i]) << + CLK_TYPE_FLAG_BITS; + debug("topology type:0x%x, flag:0x%x, type_flag:0x%x\n", + topology[*nnodes].type, topology[*nnodes].flag, + topology[*nnodes].type_flag); + (*nnodes)++; + } + + return 0; +} + +static int versal_clock_get_topology(u32 clk_id, + struct clock_topology *topology, + u32 *num_nodes) +{ + int j, ret; + u32 pm_resp[PM_API_PAYLOAD_LEN] = {0}; + + *num_nodes = 0; + for (j = 0; j <= MAX_NODES; j += 3) { + ret = versal_pm_clock_get_topology(clock[clk_id].clk_id, j, + pm_resp); + if (ret) + return ret; + ret = __versal_clock_get_topology(topology, pm_resp, num_nodes); + if (ret == END_OF_TOPOLOGY_NODE) + return 0; + } + + return 0; +} + +static int __versal_clock_get_parents(struct clock_parent *parents, u32 *data, + u32 *nparent) +{ + int i; + struct clock_parent *parent; + + for (i = 0; i < PM_API_PAYLOAD_LEN; i++) { + if (data[i] == NA_PARENT) + return END_OF_PARENTS; + + parent = &parents[i]; + parent->id = data[i] & CLK_PARENTS_ID_MASK; + if (data[i] == DUMMY_PARENT) { + strcpy(parent->name, "dummy_name"); + parent->flag = 0; + } else { + parent->flag = data[i] >> CLK_PARENTS_ID_LEN; + if (versal_get_clock_name(parent->id, parent->name)) + continue; + } + debug("parent name:%s\n", parent->name); + *nparent += 1; + } + + return 0; +} + +static int versal_clock_get_parents(u32 clk_id, struct clock_parent *parents, + u32 *num_parents) +{ + int j = 0, ret; + u32 pm_resp[PM_API_PAYLOAD_LEN] = {0}; + + *num_parents = 0; + do { + /* Get parents from firmware */ + ret = versal_pm_clock_get_parents(clock[clk_id].clk_id, j, + pm_resp); + if (ret) + return ret; + + ret = __versal_clock_get_parents(&parents[j], pm_resp, + num_parents); + if (ret == END_OF_PARENTS) + return 0; + j += PM_API_PAYLOAD_LEN; + } while (*num_parents <= MAX_PARENT); + + return 0; +} + +static u32 versal_clock_get_div(u32 clk_id) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + u32 div; + + versal_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload); + div = ret_payload[1]; + + return div; +} + +static u32 versal_clock_set_div(u32 clk_id, u32 div) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + + versal_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload); + + return div; +} + +static u64 versal_clock_ref(u32 clk_id) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ref; + + versal_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload); + ref = ret_payload[0]; + if (!(ref & 1)) + return ref_clk; + if (ref & 2) + return pl_alt_ref_clk; + return 0; +} + +static u64 versal_clock_get_pll_rate(u32 clk_id) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + u32 fbdiv; + u32 res; + u32 frac; + u64 freq; + u32 parent_rate, parent_id; + u32 id = clk_id & 0xFFF; + + versal_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload); + res = ret_payload[1]; + if (!res) { + printf("0%x PLL not enabled\n", clk_id); + return 0; + } + + parent_id = clock[clock[id].parent[0].id].clk_id; + parent_rate = versal_clock_ref(parent_id); + + versal_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload); + fbdiv = ret_payload[1]; + versal_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload); + frac = ret_payload[1]; + + freq = (fbdiv * parent_rate) >> (1 << frac); + + return freq; +} + +static u32 versal_clock_mux(u32 clk_id) +{ + int i; + u32 id = clk_id & 0xFFF; + + for (i = 0; i < clock[id].num_nodes; i++) + if (clock[id].node[i].type == CLOCK_NODE_TYPE_MUX) + return 1; + + return 0; +} + +static u32 versal_clock_get_parentid(u32 clk_id) +{ + u32 parent_id = 0; + u32 ret_payload[PAYLOAD_ARG_CNT]; + u32 id = clk_id & 0xFFF; + + if (versal_clock_mux(clk_id)) { + versal_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, + ret_payload); + parent_id = ret_payload[1]; + } + + debug("parent_id:0x%x\n", clock[clock[id].parent[parent_id].id].clk_id); + return clock[clock[id].parent[parent_id].id].clk_id; +} + +static u32 versal_clock_gate(u32 clk_id) +{ + u32 id = clk_id & 0xFFF; + int i; + + for (i = 0; i < clock[id].num_nodes; i++) + if (clock[id].node[i].type == CLOCK_NODE_TYPE_GATE) + return 1; + + return 0; +} + +static u32 versal_clock_div(u32 clk_id) +{ + int i; + u32 id = clk_id & 0xFFF; + + for (i = 0; i < clock[id].num_nodes; i++) + if (clock[id].node[i].type == CLOCK_NODE_TYPE_DIV) + return 1; + + return 0; +} + +static u32 versal_clock_pll(u32 clk_id, u64 *clk_rate) +{ + if (((clk_id >> NODE_SUBCLASS_SHIFT) & NODE_CLASS_MASK) == + NODE_SUBCLASS_CLOCK_PLL && + ((clk_id >> NODE_CLASS_SHIFT) & NODE_CLASS_MASK) == + NODE_CLASS_CLOCK) { + *clk_rate = versal_clock_get_pll_rate(clk_id); + return 1; + } + + return 0; +} + +static u64 versal_clock_calc(u32 clk_id) +{ + u32 parent_id; + u64 clk_rate; + u32 div; + + if (versal_clock_pll(clk_id, &clk_rate)) + return clk_rate; + + parent_id = versal_clock_get_parentid(clk_id); + if (((parent_id >> NODE_SUBCLASS_SHIFT) & + NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF) + return versal_clock_ref(clk_id); + + clk_rate = versal_clock_calc(parent_id); + + if (versal_clock_div(clk_id)) { + div = versal_clock_get_div(clk_id); + clk_rate = DIV_ROUND_CLOSEST(clk_rate, div); + } + + return clk_rate; +} + +static int versal_clock_get_rate(u32 clk_id, u64 *clk_rate) +{ + if (((clk_id >> NODE_SUBCLASS_SHIFT) & + NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF) + *clk_rate = versal_clock_ref(clk_id); + + if (versal_clock_pll(clk_id, clk_rate)) + return 0; + + if (((clk_id >> NODE_SUBCLASS_SHIFT) & + NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_OUT && + ((clk_id >> NODE_CLASS_SHIFT) & + NODE_CLASS_MASK) == NODE_CLASS_CLOCK) { + if (!versal_clock_gate(clk_id)) + return -EINVAL; + *clk_rate = versal_clock_calc(clk_id); + return 0; + } + + return 0; +} + +int soc_clk_dump(void) +{ + u64 clk_rate = 0; + u32 type, ret, i = 0; + + printf("\n ****** VERSAL CLOCKS *****\n"); + + printf("alt_ref_clk:%ld pl_alt_ref_clk:%ld ref_clk:%ld\n", + alt_ref_clk, pl_alt_ref_clk, ref_clk); + for (i = 0; i < clock_max_idx; i++) { + debug("%s\n", clock[i].clk_name); + ret = versal_get_clock_type(i, &type); + if (ret || type != CLK_TYPE_OUTPUT) + continue; + + ret = versal_clock_get_rate(clock[i].clk_id, &clk_rate); + + if (ret != -EINVAL) + printf("clk: %s freq:%lld\n", + clock[i].clk_name, clk_rate); + } + + return 0; +} + +static void versal_get_clock_info(void) +{ + int i, ret; + u32 attr, type = 0, nodetype, subclass, class; + + for (i = 0; i < clock_max_idx; i++) { + ret = versal_pm_clock_get_attributes(i, &attr); + if (ret) + continue; + + clock[i].valid = attr & CLK_VALID_MASK; + clock[i].type = ((attr >> CLK_TYPE_SHIFT) & 0x1) ? + CLK_TYPE_EXTERNAL : CLK_TYPE_OUTPUT; + nodetype = (attr >> NODE_TYPE_SHIFT) & NODE_CLASS_MASK; + subclass = (attr >> NODE_SUBCLASS_SHIFT) & NODE_CLASS_MASK; + class = (attr >> NODE_CLASS_SHIFT) & NODE_CLASS_MASK; + + clock[i].clk_id = (class << NODE_CLASS_SHIFT) | + (subclass << NODE_SUBCLASS_SHIFT) | + (nodetype << NODE_TYPE_SHIFT) | + (i << NODE_INDEX_SHIFT); + + ret = versal_pm_clock_get_name(clock[i].clk_id, + clock[i].clk_name); + if (ret) + continue; + debug("clk name:%s, Valid:%d, type:%d, clk_id:0x%x\n", + clock[i].clk_name, clock[i].valid, + clock[i].type, clock[i].clk_id); + } + + /* Get topology of all clock */ + for (i = 0; i < clock_max_idx; i++) { + ret = versal_get_clock_type(i, &type); + if (ret || type != CLK_TYPE_OUTPUT) + continue; + debug("clk name:%s\n", clock[i].clk_name); + ret = versal_clock_get_topology(i, clock[i].node, + &clock[i].num_nodes); + if (ret) + continue; + + ret = versal_clock_get_parents(i, clock[i].parent, + &clock[i].num_parents); + if (ret) + continue; + } +} + +int versal_clock_setup(void) +{ + int ret; + + ret = versal_pm_clock_get_num_clocks(&clock_max_idx); + if (ret) + return ret; + + debug("%s, clock_max_idx:0x%x\n", __func__, clock_max_idx); + clock = calloc(clock_max_idx, sizeof(*clock)); + if (!clock) + return -ENOMEM; + + versal_get_clock_info(); + + return 0; +} + +static int versal_clock_get_freq_by_name(char *name, struct udevice *dev, + ulong *freq) +{ + struct clk clk; + int ret; + + ret = clk_get_by_name(dev, name, &clk); + if (ret < 0) { + dev_err(dev, "failed to get %s\n", name); + return ret; + } + + *freq = clk_get_rate(&clk); + if (IS_ERR_VALUE(*freq)) { + dev_err(dev, "failed to get rate %s\n", name); + return -EINVAL; + } + + return 0; +} + +static int versal_clk_probe(struct udevice *dev) +{ + int ret; + struct versal_clk_priv *priv = dev_get_priv(dev); + + debug("%s\n", __func__); + + ret = versal_clock_get_freq_by_name("alt_ref_clk", dev, &alt_ref_clk); + if (ret < 0) + return -EINVAL; + + ret = versal_clock_get_freq_by_name("pl_alt_ref_clk", + dev, &pl_alt_ref_clk); + if (ret < 0) + return -EINVAL; + + ret = versal_clock_get_freq_by_name("ref_clk", dev, &ref_clk); + if (ret < 0) + return -EINVAL; + + versal_clock_setup(); + + priv->clk = clock; + + return ret; +} + +static ulong versal_clk_get_rate(struct clk *clk) +{ + struct versal_clk_priv *priv = dev_get_priv(clk->dev); + u32 id = clk->id; + u32 clk_id; + u64 clk_rate = 0; + + debug("%s\n", __func__); + + clk_id = priv->clk[id].clk_id; + + versal_clock_get_rate(clk_id, &clk_rate); + + return clk_rate; +} + +static ulong versal_clk_set_rate(struct clk *clk, ulong rate) +{ + struct versal_clk_priv *priv = dev_get_priv(clk->dev); + u32 id = clk->id; + u32 clk_id; + u64 clk_rate = 0; + u32 div; + int ret; + + debug("%s\n", __func__); + + clk_id = priv->clk[id].clk_id; + + ret = versal_clock_get_rate(clk_id, &clk_rate); + if (ret) { + printf("Clock is not a Gate:0x%x\n", clk_id); + return 0; + } + + do { + if (versal_clock_div(clk_id)) { + div = versal_clock_get_div(clk_id); + clk_rate *= div; + div = DIV_ROUND_CLOSEST(clk_rate, rate); + versal_clock_set_div(clk_id, div); + debug("%s, div:%d, newrate:%lld\n", __func__, + div, DIV_ROUND_CLOSEST(clk_rate, div)); + return DIV_ROUND_CLOSEST(clk_rate, div); + } + clk_id = versal_clock_get_parentid(clk_id); + } while (((clk_id >> NODE_SUBCLASS_SHIFT) & + NODE_CLASS_MASK) != NODE_SUBCLASS_CLOCK_REF); + + printf("Clock didn't has Divisors:0x%x\n", priv->clk[id].clk_id); + + return clk_rate; +} + +static struct clk_ops versal_clk_ops = { + .set_rate = versal_clk_set_rate, + .get_rate = versal_clk_get_rate, +}; + +static const struct udevice_id versal_clk_ids[] = { + { .compatible = "xlnx,versal-clk" }, + { } +}; + +U_BOOT_DRIVER(versal_clk) = { + .name = "versal-clk", + .id = UCLASS_CLK, + .of_match = versal_clk_ids, + .probe = versal_clk_probe, + .ops = &versal_clk_ops, + .priv_auto_alloc_size = sizeof(struct versal_clk_priv), +}; diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index b36eda1b04..4077126581 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -4,6 +4,7 @@ static const struct udevice_id zynqmp_firmware_ids[] = { { .compatible = "xlnx,zynqmp-firmware" }, + { .compatible = "xlnx,versal-firmware"}, { } }; From bc493d911e8c4e59ddaf0def0d35f1e2db0899ab Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Mon, 1 Jul 2019 12:19:25 +0530 Subject: [PATCH 24/85] net: zynq_gem: Remove check for Versal This patch removes check for Versal platform in gem driver as it now supports clock setting through clock framework. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/net/zynq_gem.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index a35ecab79e..a7a6ce987f 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -463,7 +463,6 @@ static int zynq_gem_init(struct udevice *dev) break; } -#if !defined(CONFIG_ARCH_VERSAL) ret = clk_set_rate(&priv->clk, clk_rate); if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) { dev_err(dev, "failed to set tx clock rate\n"); @@ -475,9 +474,6 @@ static int zynq_gem_init(struct udevice *dev) dev_err(dev, "failed to enable tx clock\n"); return ret; } -#else - debug("requested clk_rate %ld\n", clk_rate); -#endif setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | ZYNQ_GEM_NWCTRL_TXEN_MASK); From d882f0847cc000a380b468a47ab9647d482adc69 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Mon, 27 May 2019 14:33:14 +0530 Subject: [PATCH 25/85] mmc: sdhci: Move ZYNQ_HISPD_BROKEN to Kconfig This patch moves CONFIG_ZYNQ_HISPD_BROKEN to Kconfig Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/mmc/Kconfig | 6 ++++++ scripts/config_whitelist.txt | 1 - 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 7361bcaf8e..2bc9d8d22d 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -634,6 +634,12 @@ config ZYNQ_SDHCI_MIN_FREQ help Set the minimum frequency of the controller. +config ZYNQ_HISPD_BROKEN + bool "High speed broken for Zynq SDHCI controller" + depends on MMC_SDHCI_ZYNQ + help + Set if high speed mode is broken. + config MMC_SUNXI bool "Allwinner sunxi SD/MMC Host Controller support" depends on ARCH_SUNXI && !UART0_PORT_F diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 5a007d3709..94751acef6 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -4364,5 +4364,4 @@ CONFIG_YAFFS_WINCE CONFIG_YELLOW_LED CONFIG_ZLT CONFIG_ZM7300 -CONFIG_ZYNQ_HISPD_BROKEN CONFIG_eTSEC_MDIO_BUS From 23decf013bdd8fb2a7727225229d3bf9daa2827e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 2 Aug 2019 12:43:29 +0200 Subject: [PATCH 26/85] fpga: zynqmp: Fix second local variable declaration No reason to define new_buf again. Signed-off-by: Michal Simek --- drivers/fpga/zynqmppl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index 22bfdd8dce..f6d9d50ef1 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -153,7 +153,7 @@ static ulong zynqmp_align_dma_buffer(u32 *buf, u32 len, u32 swap) } else if ((swap != SWAP_DONE) && (zynqmp_pmufw_version() <= PMUFW_V1_0)) { /* For bitstream which are aligned */ - u32 *new_buf = (u32 *)buf; + new_buf = buf; printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__, swap); From d6f48ea5ce181aa48810029e2cd32fae2842de01 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 10 Sep 2019 15:39:15 +0200 Subject: [PATCH 27/85] ARM: zynq: Do not enable NETBSD support by default This option is disable in Xilinx tree for quite a long time that's why let's disable it in mainline. If there is anybody who requires this options then it should be moved to Kconfig first and should be removed from this config. Signed-off-by: Michal Simek --- include/configs/zynq-common.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index ae08ebf2af..b7e6666812 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -274,6 +274,8 @@ /* Boot FreeBSD/vxWorks from an ELF image */ #define CONFIG_SYS_MMC_MAX_DEVICE 1 +#undef CONFIG_BOOTM_NETBSD + /* MMC support */ #ifdef CONFIG_MMC_SDHCI_ZYNQ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 From d6d82cb0bee0b4ea53e6873010c67371af2dd5aa Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Mon, 24 Jul 2017 16:53:15 +0530 Subject: [PATCH 28/85] ARM: zynq: Increase init ram size by 4K Increase init ram size by 4K such that more stack space will be available during initialization as the present stackspace is not sufficient if DEBUG option is enabled and causes system hang. Increasing init ram size provides sufficient stack space during init even if DEBUG enabled and solves the hang issue. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- include/configs/zynq-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index b7e6666812..785377e0b6 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -262,7 +262,7 @@ #define CONFIG_SYS_MEMTEST_END 0x1000 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) From 8567717dff2b3d972003d91361004f2ecef3935c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 10 Sep 2019 15:49:42 +0200 Subject: [PATCH 29/85] ARM: zynq: Increase input buffer console size to 2k ZynqMP and Versal is using 2k that's why aligned all platform together to be able to use the same scripts. Signed-off-by: Michal Simek --- include/configs/zynq-common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 785377e0b6..283a784941 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -257,6 +257,7 @@ #define CONFIG_CLOCKS #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +#define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ #define CONFIG_SYS_MEMTEST_START 0 #define CONFIG_SYS_MEMTEST_END 0x1000 From a85f388565063404ec6cd8b908094c0e3e6472e3 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Mon, 9 Sep 2019 03:31:08 -0600 Subject: [PATCH 30/85] arm64: versal: Fix for OCM overwriting issue This patch reduces the console buffer size from 2048 to 1024, thus fixes OCM overwriting issue. Differences are in bss section as is shown from output: xilinx_versal_mini: all -2056 bss -2048 text -8 u-boot: add: 0/0, grow: 0/-3 bytes: 0/-2056 (-2056) function old new delta cli_simple_run_command 340 332 -8 static.lastcommand 2049 1025 -1024 console_buffer 2049 1025 -1024 Better would be to use PPU RAM but this change is also aligned with changes done in ZynqMP mini configurations. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek --- include/configs/xilinx_versal_mini.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/xilinx_versal_mini.h b/include/configs/xilinx_versal_mini.h index d30a697a57..ee305e0226 100644 --- a/include/configs/xilinx_versal_mini.h +++ b/include/configs/xilinx_versal_mini.h @@ -26,4 +26,7 @@ #undef CONFIG_BOOTP_BOOTFILESIZE #undef CONFIG_BOOTP_MAY_FAIL +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 1024 + #endif /* __CONFIG_VERSAL_MINI_H */ From 134b0c8d6a8ed07b9b382792c24ca9ecce56106d Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 23 Jul 2019 11:56:17 +0530 Subject: [PATCH 31/85] arm64: zynqmp: Add idcodes for new RFSoC silicons ZU48DR and ZU49DR Add zu48dr and zu49dr to the list of zynqmp devices. The zu48dr and zu49dr are the new RFSoC silicons with id values of 0x7b and 0x7e. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- board/xilinx/zynqmp/zynqmp.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index f36d49fded..6524badf29 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -174,6 +174,14 @@ static const struct { .id = 0x66, .name = "39dr", }, + { + .id = 0x7b, + .name = "48dr", + }, + { + .id = 0x7e, + .name = "49dr", + }, }; #endif From a6af30908bd61f3aa77f78c463834eb2f635670f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 27 May 2019 10:13:34 +0200 Subject: [PATCH 32/85] ARM: zynq: Align model name with DT Use model property to distinguish different configurations. Signed-off-by: Michal Simek --- arch/arm/dts/zynq-cse-qspi-single.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/zynq-cse-qspi-single.dts b/arch/arm/dts/zynq-cse-qspi-single.dts index 0d680dfc06..ac6982a74e 100644 --- a/arch/arm/dts/zynq-cse-qspi-single.dts +++ b/arch/arm/dts/zynq-cse-qspi-single.dts @@ -7,6 +7,10 @@ #include "zynq-cse-qspi.dtsi" +/ { + model = "Zynq CSE QSPI SINGLE Board"; +}; + &flash0 { spi-rx-bus-width = <4>; }; From 69b67ec8c90b0fc5856efc915415d06131a36be4 Mon Sep 17 00:00:00 2001 From: Vipul Kumar Date: Tue, 7 Aug 2018 16:30:04 +0530 Subject: [PATCH 33/85] ARM: zynq: dts: Added alias for usb node This patch added alias for usb node in dts file. Signed-off-by: Vipul Kumar Signed-off-by: Michal Simek --- arch/arm/dts/zynq-zc702.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index 54231cd580..d10695740f 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -16,6 +16,7 @@ serial0 = &uart1; spi0 = &qspi; mmc0 = &sdhci0; + usb0 = &usb0; }; memory@0 { From be49508a0f3229ff589dfabad80ab2774f47875a Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Fri, 15 Mar 2019 17:46:47 +0530 Subject: [PATCH 34/85] net: phy: Define init routine and register generic phy driver This patch define init routine for generic phy driver and registers it using phy_register as this generic phy driver also needs to be relocated incase of manual reloc. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/net/phy/phy.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index ae37dd6c1e..8c4043445e 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -458,6 +458,11 @@ static struct phy_driver genphy_driver = { .shutdown = genphy_shutdown, }; +int genphy_init(void) +{ + return phy_register(&genphy_driver); +} + static LIST_HEAD(phy_drivers); int phy_init(void) @@ -540,6 +545,8 @@ int phy_init(void) #ifdef CONFIG_PHY_FIXED phy_fixed_init(); #endif + genphy_init(); + return 0; } From 7712fb1ff738802a81a3989ad988e7ac8c0d16ff Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 11 Sep 2019 12:51:49 +0200 Subject: [PATCH 35/85] ARM: zynq: Specify MMC controller number for boot sequence Xilinx Zynq SoC has two sdhci controllers but boot is only possible from the first one. That's why there is a need to specify controller number. mmc1 is supposed to be secondary boot device and should be also listed in distribution boot. Signed-off-by: Michal Simek --- board/xilinx/zynq/board.c | 2 +- include/configs/zynq-common.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 35191b2f81..7cfe69db69 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -52,7 +52,7 @@ int board_late_init(void) env_set("modeboot", "norboot"); break; case ZYNQ_BM_SD: - mode = "mmc"; + mode = "mmc0"; env_set("modeboot", "sdboot"); break; case ZYNQ_BM_JTAG: diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 283a784941..824efa9c00 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -111,7 +111,7 @@ #else #ifdef CONFIG_CMD_MMC -#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) #else #define BOOT_TARGET_DEVICES_MMC(func) #endif From 559e5a68f40c68988a5fadbd1f930c3230376cf9 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 11 Sep 2019 13:00:57 +0200 Subject: [PATCH 36/85] ARM: zynq: Enable USB1 as secondary boot device Xilinx Zynq SoC has two usb controllers and both could be used as secondary boot method. Signed-off-by: Michal Simek --- include/configs/zynq-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 824efa9c00..de6c06ba3c 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -117,7 +117,7 @@ #endif #ifdef CONFIG_CMD_USB -#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) +#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) func(USB, usb, 1) #else #define BOOT_TARGET_DEVICES_USB(func) #endif From 90b9fcb9d4fb7e9205bdd6e73fb902533a6146db Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 11 Sep 2019 13:16:33 +0200 Subject: [PATCH 37/85] ARM: zynq: Fix NOR boot mode There are two typos in this command that's why it couldn't work properly. This bootmode is almost unused from the beggining on this SoC. Fixes: 90e97ab31e02 ("arm: zynq: Define distro boot commnads for qspi, nand and nor") Signed-off-by: Michal Simek --- include/configs/zynq-common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index de6c06ba3c..09eada3902 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -175,7 +175,8 @@ "nand " #define BOOTENV_DEV_NOR(devtypeu, devtypel, instance) \ - "bootcmd_nor=cp.b $scropt_offset_nor $scriptaddr $script_size_f && " \ + "script_offset_nor=0xE2FC0000\0" \ + "bootcmd_nor=cp.b ${script_offset_nor} ${scriptaddr} ${script_size_f} && " \ "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" #define BOOTENV_DEV_NAME_NOR(devtypeu, devtypel, instance) \ @@ -205,7 +206,6 @@ "fdt_high=0x20000000\0" \ "initrd_high=0x20000000\0" \ "scriptaddr=0x20000\0" \ - "script_offser_nor=0xE2FC0000\0" \ "script_offset_f=0xFC0000\0" \ "script_size_f=0x40000\0" \ "loadbootenv_addr=0x2000000\0" \ From a542a937350b486223f7ed72f8471967df53cf49 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 11 Sep 2019 13:12:43 +0200 Subject: [PATCH 38/85] ARM: zynq: Use {} around variables for qspi and nand boot cmds Follow conventions and used {} around variables. Fixes: 90e97ab31e02 ("arm: zynq: Define distro boot commnads for qspi, nand and nor") Signed-off-by: Michal Simek --- include/configs/zynq-common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 09eada3902..4b12be30c8 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -160,7 +160,7 @@ #define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ "bootcmd_qspi=sf probe 0 0 0 && " \ - "sf read $scriptaddr $script_offset_f $script_size_f && " \ + "sf read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \ "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" #define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ @@ -168,7 +168,7 @@ #define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ "bootcmd_nand=nand info && " \ - "nand read $scriptaddr $script_offset_f $script_size_f && " \ + "nand read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \ "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" #define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ From 83a0e8054e2bf7c2adb95a00af8ec641d19eb4df Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 10 Sep 2019 15:01:53 +0200 Subject: [PATCH 39/85] ARM: zynq: Remove all Xilinx private commands All platforms have been moved to distro boot that's why remove the rest of configurations to have unified boot flow. Signed-off-by: Michal Simek --- include/configs/zynq-common.h | 54 ++--------------------------------- 1 file changed, 3 insertions(+), 51 deletions(-) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 4b12be30c8..b6c9f2c8dd 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -152,12 +152,6 @@ # define BOOT_TARGET_DEVICES_NOR(func) #endif -#define BOOTENV_DEV_XILINX(devtypeu, devtypel, instance) \ - "bootcmd_xilinx=run $modeboot\0" - -#define BOOTENV_DEV_NAME_XILINX(devtypeu, devtypel, instance) \ - "xilinx " - #define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ "bootcmd_qspi=sf probe 0 0 0 && " \ "sf read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \ @@ -189,8 +183,7 @@ BOOT_TARGET_DEVICES_NOR(func) \ BOOT_TARGET_DEVICES_USB(func) \ BOOT_TARGET_DEVICES_PXE(func) \ - BOOT_TARGET_DEVICES_DHCP(func) \ - func(XILINX, xilinx, na) + BOOT_TARGET_DEVICES_DHCP(func) #include #endif /* CONFIG_SPL_BUILD */ @@ -198,59 +191,18 @@ /* Default environment */ #ifndef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ - "fit_image=fit.itb\0" \ - "load_addr=0x2000000\0" \ - "fit_size=0x800000\0" \ - "flash_off=0x100000\0" \ - "nor_flash_off=0xE2100000\0" \ "fdt_high=0x20000000\0" \ "initrd_high=0x20000000\0" \ "scriptaddr=0x20000\0" \ "script_offset_f=0xFC0000\0" \ "script_size_f=0x40000\0" \ - "loadbootenv_addr=0x2000000\0" \ "fdt_addr_r=0x1f00000\0" \ "pxefile_addr_r=0x2000000\0" \ "kernel_addr_r=0x2000000\0" \ "scriptaddr=0x3000000\0" \ "ramdisk_addr_r=0x3100000\0" \ - "bootenv=uEnv.txt\0" \ - "bootenv_dev=mmc\0" \ - "loadbootenv=load ${bootenv_dev} 0 ${loadbootenv_addr} ${bootenv}\0" \ - "importbootenv=echo Importing environment from ${bootenv_dev} ...; " \ - "env import -t ${loadbootenv_addr} $filesize\0" \ - "bootenv_existence_test=test -e ${bootenv_dev} 0 /${bootenv}\0" \ - "setbootenv=if env run bootenv_existence_test; then " \ - "if env run loadbootenv; then " \ - "env run importbootenv; " \ - "fi; " \ - "fi; \0" \ - "sd_loadbootenv=setenv bootenv_dev mmc && " \ - "run setbootenv \0" \ - "usb_loadbootenv=setenv bootenv_dev usb && usb start && run setbootenv \0" \ - "preboot=if test $modeboot = sdboot; then " \ - "run sd_loadbootenv; " \ - "echo Checking if uenvcmd is set ...; " \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...; " \ - "run uenvcmd; " \ - "fi; " \ - "fi; \0" \ - "norboot=echo Copying FIT from NOR flash to RAM... && " \ - "cp.b ${nor_flash_off} ${load_addr} ${fit_size} && " \ - "bootm ${load_addr}\0" \ - "sdboot=echo Copying FIT from SD to RAM... && " \ - "load mmc 0 ${load_addr} ${fit_image} && " \ - "bootm ${load_addr}\0" \ - "jtagboot=echo TFTPing FIT to RAM... && " \ - "tftpboot ${load_addr} ${fit_image} && " \ - "bootm ${load_addr}\0" \ - "usbboot=if usb start; then " \ - "echo Copying FIT from USB to RAM... && " \ - "load usb 0 ${load_addr} ${fit_image} && " \ - "bootm ${load_addr}; fi\0" \ - DFU_ALT_INFO \ - BOOTENV + DFU_ALT_INFO \ + BOOTENV #endif /* Miscellaneous configurable options */ From f41e588c033f31cdf4b1f1c70fac2e0264c6c4db Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 27 Nov 2018 11:49:11 +0530 Subject: [PATCH 40/85] net: phy: Add gmiitorgmii converter support This patch adds support for gmiitorgmii converter. This converter sits between the MAC and the external phy MAC <==> GMII2RGMII <==> RGMII_PHY. The ethernet driver probes this bridge and this bridge driver probes real phy driver and invokes the real phy functionalities as requested. This bridge just needs to be configured based on real phy negotiated speed and duplex. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/net/phy/Kconfig | 7 ++ drivers/net/phy/Makefile | 1 + drivers/net/phy/phy.c | 42 ++++++++ drivers/net/phy/xilinx_gmii2rgmii.c | 144 ++++++++++++++++++++++++++++ include/phy.h | 6 ++ 5 files changed, 200 insertions(+) create mode 100644 drivers/net/phy/xilinx_gmii2rgmii.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 2a3da068c9..30bd8e7653 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -228,6 +228,13 @@ config PHY_VITESSE config PHY_XILINX bool "Xilinx Ethernet PHYs support" +config PHY_XILINX_GMII2RGMII + bool "Xilinx GMII to RGMII Ethernet PHYs support" + help + This adds support for Xilinx GMII to RGMII IP core. This IP acts + as bridge between MAC connected over GMII and external phy that + is connected over RGMII interface. + config PHY_FIXED bool "Fixed-Link PHY" depends on DM_ETH diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 555da83630..76b6197009 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_PHY_SMSC) += smsc.o obj-$(CONFIG_PHY_TERANETICS) += teranetics.o obj-$(CONFIG_PHY_TI) += ti.o obj-$(CONFIG_PHY_XILINX) += xilinx_phy.o +obj-$(CONFIG_PHY_XILINX_GMII2RGMII) += xilinx_gmii2rgmii.o obj-$(CONFIG_PHY_VITESSE) += vitesse.o obj-$(CONFIG_PHY_MSCC) += mscc.o obj-$(CONFIG_PHY_FIXED) += fixed.o diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 8c4043445e..f2d17aa91a 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -544,6 +544,9 @@ int phy_init(void) #endif #ifdef CONFIG_PHY_FIXED phy_fixed_init(); +#endif +#ifdef CONFIG_PHY_XILINX_GMII2RGMII + phy_xilinx_gmii2rgmii_init(); #endif genphy_init(); @@ -918,6 +921,41 @@ void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev) debug("%s connected to %s\n", dev->name, phydev->drv->name); } +#ifdef CONFIG_PHY_XILINX_GMII2RGMII +#ifdef CONFIG_DM_ETH +static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus, + struct udevice *dev, + phy_interface_t interface) +#else +static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus, + struct eth_device *dev, + phy_interface_t interface) +#endif +{ + struct phy_device *phydev = NULL; + int sn = dev_of_offset(dev); + int off; + + while (sn > 0) { + off = fdt_node_offset_by_compatible(gd->fdt_blob, sn, + "xlnx,gmii-to-rgmii-1.0"); + if (off > 0) { + phydev = phy_device_create(bus, off, + PHY_GMII2RGMII_ID, false, + interface); + break; + } + if (off == -FDT_ERR_NOTFOUND) + sn = fdt_first_subnode(gd->fdt_blob, sn); + else + printf("%s: Error finding compat string:%d\n", + __func__, off); + } + + return phydev; +} +#endif + #ifdef CONFIG_PHY_FIXED #ifdef CONFIG_DM_ETH static struct phy_device *phy_connect_fixed(struct mii_dev *bus, @@ -964,6 +1002,10 @@ struct phy_device *phy_connect(struct mii_dev *bus, int addr, #ifdef CONFIG_PHY_FIXED phydev = phy_connect_fixed(bus, dev, interface); #endif +#ifdef CONFIG_PHY_XILINX_GMII2RGMII + if (!phydev) + phydev = phy_connect_gmii2rgmii(bus, dev, interface); +#endif if (!phydev) phydev = phy_find_by_mask(bus, mask, interface); diff --git a/drivers/net/phy/xilinx_gmii2rgmii.c b/drivers/net/phy/xilinx_gmii2rgmii.c new file mode 100644 index 0000000000..8c20da2682 --- /dev/null +++ b/drivers/net/phy/xilinx_gmii2rgmii.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx GMII2RGMII phy driver + * + * Copyright (C) 2018 Xilinx, Inc. + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define ZYNQ_GMII2RGMII_REG 0x10 +#define ZYNQ_GMII2RGMII_SPEED_MASK (BMCR_SPEED1000 | BMCR_SPEED100) + +static int xilinxgmiitorgmii_config(struct phy_device *phydev) +{ + struct phy_device *ext_phydev = phydev->priv; + + debug("%s\n", __func__); + if (ext_phydev->drv->config) + ext_phydev->drv->config(ext_phydev); + + return 0; +} + +static int xilinxgmiitorgmii_extread(struct phy_device *phydev, int addr, + int devaddr, int regnum) +{ + struct phy_device *ext_phydev = phydev->priv; + + debug("%s\n", __func__); + if (ext_phydev->drv->readext) + ext_phydev->drv->readext(ext_phydev, addr, devaddr, regnum); + + return 0; +} + +static int xilinxgmiitorgmii_extwrite(struct phy_device *phydev, int addr, + int devaddr, int regnum, u16 val) + +{ + struct phy_device *ext_phydev = phydev->priv; + + debug("%s\n", __func__); + if (ext_phydev->drv->writeext) + ext_phydev->drv->writeext(ext_phydev, addr, devaddr, regnum, + val); + + return 0; +} + +static int xilinxgmiitorgmii_startup(struct phy_device *phydev) +{ + u16 val = 0; + struct phy_device *ext_phydev = phydev->priv; + + debug("%s\n", __func__); + ext_phydev->dev = phydev->dev; + if (ext_phydev->drv->startup) + ext_phydev->drv->startup(ext_phydev); + + val = phy_read(phydev, phydev->addr, ZYNQ_GMII2RGMII_REG); + val &= ~ZYNQ_GMII2RGMII_SPEED_MASK; + + if (ext_phydev->speed == SPEED_1000) + val |= BMCR_SPEED1000; + else if (ext_phydev->speed == SPEED_100) + val |= BMCR_SPEED100; + + phy_write(phydev, phydev->addr, ZYNQ_GMII2RGMII_REG, val | + BMCR_FULLDPLX); + + phydev->duplex = ext_phydev->duplex; + phydev->speed = ext_phydev->speed; + phydev->link = ext_phydev->link; + + return 0; +} + +static int xilinxgmiitorgmii_probe(struct phy_device *phydev) +{ + int ofnode = phydev->addr; + u32 phy_of_handle; + int ext_phyaddr = -1; + struct phy_device *ext_phydev; + + debug("%s\n", __func__); + + if (phydev->interface != PHY_INTERFACE_MODE_GMII) { + printf("Incorrect interface type\n"); + return -EINVAL; + } + + /* + * Read the phy address again as the one we read in ethernet driver + * was overwritten for the purpose of storing the ofnode + */ + phydev->addr = fdtdec_get_int(gd->fdt_blob, ofnode, "reg", -1); + phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, ofnode, + "phy-handle"); + if (phy_of_handle > 0) + ext_phyaddr = fdtdec_get_int(gd->fdt_blob, + phy_of_handle, + "reg", -1); + ext_phydev = phy_find_by_mask(phydev->bus, + 1 << ext_phyaddr, + PHY_INTERFACE_MODE_RGMII); + if (!ext_phydev) { + printf("%s, No external phy device found\n", __func__); + return -EINVAL; + } + + ext_phydev->node = offset_to_ofnode(phy_of_handle); + phydev->priv = ext_phydev; + + debug("%s, gmii2rgmmi:0x%x, extphy:0x%x\n", __func__, phydev->addr, + ext_phyaddr); + + phydev->flags |= PHY_FLAG_BROKEN_RESET; + + return 0; +} + +static struct phy_driver gmii2rgmii_driver = { + .name = "XILINX GMII2RGMII", + .uid = PHY_GMII2RGMII_ID, + .mask = 0xffffffff, + .features = PHY_GBIT_FEATURES, + .probe = xilinxgmiitorgmii_probe, + .config = xilinxgmiitorgmii_config, + .startup = xilinxgmiitorgmii_startup, + .writeext = xilinxgmiitorgmii_extwrite, + .readext = xilinxgmiitorgmii_extread, +}; + +int phy_xilinx_gmii2rgmii_init(void) +{ + phy_register(&gmii2rgmii_driver); + + return 0; +} diff --git a/include/phy.h b/include/phy.h index f4530faeb9..e50f56b6eb 100644 --- a/include/phy.h +++ b/include/phy.h @@ -17,6 +17,11 @@ #include #define PHY_FIXED_ID 0xa5a55a5a +/* + * There is no actual id for this. + * This is just a dummy id for gmii2rgmmi converter. + */ +#define PHY_GMII2RGMII_ID 0x5a5a5a5a #define PHY_MAX_ADDR 32 @@ -391,6 +396,7 @@ int phy_vitesse_init(void); int phy_xilinx_init(void); int phy_mscc_init(void); int phy_fixed_init(void); +int phy_xilinx_gmii2rgmii_init(void); int board_phy_config(struct phy_device *phydev); int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id); From b96b695f2c51f2e3eb5e289d621a605984368599 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 11 Sep 2019 14:55:37 +0200 Subject: [PATCH 41/85] arm64: zynqmp: Switch spi-flash to jedec, spi-nor compatible Change has been done across the whole tree only zynqmp-mini-qspi hasn't been fixed. Origin changed done by commit ffd4c7c2ecb7 ("dts: switch spi-flash to jedec, spi-nor compatible") Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-mini-qspi.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts index 1716d5179d..e4ba5ae9b6 100644 --- a/arch/arm/dts/zynqmp-mini-qspi.dts +++ b/arch/arm/dts/zynqmp-mini-qspi.dts @@ -64,7 +64,7 @@ &qspi { status = "okay"; flash0: flash@0 { - compatible = "n25q512a11", "spi-flash"; + compatible = "n25q512a11", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; From c95b19acac5c55c26bcc65e4064ffc97f1313dc4 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Fri, 2 Aug 2019 16:46:26 +0530 Subject: [PATCH 42/85] mmc: zynq_sdhci: Remove check for DM_MMC config The zynq_sdhci drivers depends on DM_MMC in Kconfig so no need to check for DM_MMC in the driver so this patch removes it. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/mmc/zynq_sdhci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 3225a7ac93..529eec9c45 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -190,7 +190,7 @@ static void arasan_sdhci_set_control_reg(struct sdhci_host *host) } #endif -#if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP) +#if defined(CONFIG_ARCH_ZYNQMP) const struct sdhci_ops arasan_ops = { .platform_execute_tuning = &arasan_sdhci_execute_tuning, .set_delay = &arasan_sdhci_set_tapdelay, @@ -266,7 +266,7 @@ static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) priv->host->name = dev->name; -#if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP) +#if defined(CONFIG_ARCH_ZYNQMP) priv->host->ops = &arasan_ops; #endif From ad704bbdba86004ed45f2095483e179d5cbb1f69 Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Fri, 26 Jul 2019 02:49:28 -0700 Subject: [PATCH 43/85] doc: README.xilinx: Add dt bindings Devicetree bindings are already specified in Linux kernel documentation. Instead of maintaining same dt bindings in U-Boot doc specify path to dt bindings in Linux kernel & documenting specific changes that are in U-Boot. Signed-off-by: T Karthik Reddy Signed-off-by: Michal Simek Reviewed-by: Bin Meng Tested-by: Bin Meng --- doc/board/xilinx/index.rst | 1 + doc/board/xilinx/xilinx.rst | 38 +++++++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) create mode 100644 doc/board/xilinx/xilinx.rst diff --git a/doc/board/xilinx/index.rst b/doc/board/xilinx/index.rst index 2416fbd216..47f09290af 100644 --- a/doc/board/xilinx/index.rst +++ b/doc/board/xilinx/index.rst @@ -6,4 +6,5 @@ Xilinx .. toctree:: :maxdepth: 2 + xilinx zynq diff --git a/doc/board/xilinx/xilinx.rst b/doc/board/xilinx/xilinx.rst new file mode 100644 index 0000000000..f6ea5dbe21 --- /dev/null +++ b/doc/board/xilinx/xilinx.rst @@ -0,0 +1,38 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. (C) Copyright 2019 Xilinx, Inc. + +U-Boot device tree bindings +---------------------------- + +All the device tree bindings used in U-Boot are specified in Linux +kernel. Please refer dt bindings from below specified paths in Linux +kernel. + +* ata + - Documentation/devicetree/bindings/ata/ahci-ceva.txt +* gpio + - Documentation/devicetree/bindings/gpio/gpio-xilinx.txt + - Documentation/devicetree/bindings/gpio/gpio-zynq.txt +* i2c + - Documentation/devicetree/bindings/i2c/i2c-xiic.txt + - Documentation/devicetree/bindings/i2c/i2c-cadence.txt +* mmc + - Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +* net + - Documentation/devicetree/bindings/net/macb.txt + - Documentation/devicetree/bindings/net/xilinx_axienet.txt + - Documentation/devicetree/bindings/net/xilinx_emaclite.txt +* serial + - Documentation/devicetree/bindings/serial/cdns,uart.txt + - Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt +* spi + - Documentation/devicetree/bindings/spi/spi-cadence.txt + - Documentation/devicetree/bindings/spi/spi-xilinx.txt + - Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt + - Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt +* usb + - Documentation/devicetree/bindings/usb/dwc3-xilinx.txt + - Documentation/devicetree/bindings/usb/dwc3.txt + - Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt +* wdt + - Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt From 0d0fbc857c20c2c426dbf6d13185a1d549c1edeb Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Fri, 19 Apr 2019 09:10:37 +0530 Subject: [PATCH 44/85] arm64: zynqmp: Enable 2 NAND chips support for zynqmp_mini_nand This patch enables 2 nand chips support for zynqmp mini nand Signed-off-by: T Karthik Reddy Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- configs/xilinx_zynqmp_mini_nand_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig index 4be624813c..2b896f79a7 100644 --- a/configs/xilinx_zynqmp_mini_nand_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_defconfig @@ -49,4 +49,5 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand" # CONFIG_MMC is not set CONFIG_NAND=y CONFIG_NAND_ARASAN=y +CONFIG_SYS_NAND_MAX_CHIPS=2 # CONFIG_EFI_LOADER is not set From 1a031d236a9eeb28ced5438242987ae6a45f3054 Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Wed, 1 May 2019 10:14:49 +0530 Subject: [PATCH 45/85] drivers: usb: dwc3: setup phy before dwc3 core soft reset Phy setup should be done before dwc3 soft core reset as it is done in linux & this fixes unreliable detection of usb cable on host side. Signed-off-by: T Karthik Reddy Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/usb/dwc3/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 56e2a046bf..2498f0efb1 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -440,6 +440,8 @@ static int dwc3_core_init(struct dwc3 *dwc) goto err0; } + dwc3_phy_setup(dwc); + ret = dwc3_core_soft_reset(dwc); if (ret) goto err0; @@ -514,8 +516,6 @@ static int dwc3_core_init(struct dwc3 *dwc) dwc3_writel(dwc->regs, DWC3_GCTL, reg); - dwc3_phy_setup(dwc); - ret = dwc3_alloc_scratch_buffers(dwc); if (ret) goto err0; From f8c0f9fa7cbd2be377b4af4106674b3d4f6538db Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Mon, 5 Aug 2019 16:18:57 +0530 Subject: [PATCH 46/85] env: Kconfig: Add environment default offset in versal This patch adds default offset & sector size values for environment variables to save in qspi/ospi flash for versal. Signed-off-by: T Karthik Reddy Signed-off-by: Michal Simek --- env/Kconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/env/Kconfig b/env/Kconfig index 74db2f38cc..e4ba12ece3 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -473,6 +473,7 @@ config ENV_OFFSET default 0x88000 if ARCH_SUNXI default 0xE0000 if ARCH_ZYNQ default 0x1E00000 if ARCH_ZYNQMP + default 0x7F40000 if ARCH_VERSAL default 0 if ARC default 0x140000 if ARCH_AT91 default 0x260000 if ARCH_OMAP2PLUS @@ -491,8 +492,8 @@ config ENV_SIZE config ENV_SECT_SIZE hex "Environment Sector-Size" - depends on (!ENV_IS_NOWHERE && (ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_OMAP2PLUS || ARCH_AT91) )|| ARCH_STM32MP - default 0x40000 if ARCH_ZYNQMP + depends on (!ENV_IS_NOWHERE && (ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_OMAP2PLUS || ARCH_AT91) )|| ARCH_STM32MP + default 0x40000 if ARCH_ZYNQMP || ARCH_VERSAL default 0x20000 if ARCH_ZYNQ || ARCH_OMAP2PLUS || ARCH_AT91 help Size of the sector containing the environment. From 5bbc4dc0388460c7fa28bdf1a19357088fcae1cc Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 18 Jul 2019 15:56:59 +0530 Subject: [PATCH 47/85] arm64: versal: mini_emmc: Enable fatwrite support This patch enable fatwrite support for mini emmc configurations. Signed-off-by: Siva Durga Prasad Paladugu --- configs/xilinx_versal_mini_emmc0_defconfig | 1 + configs/xilinx_versal_mini_emmc1_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/xilinx_versal_mini_emmc0_defconfig b/configs/xilinx_versal_mini_emmc0_defconfig index 08d23243be..49386e21d3 100644 --- a/configs/xilinx_versal_mini_emmc0_defconfig +++ b/configs/xilinx_versal_mini_emmc0_defconfig @@ -50,4 +50,5 @@ CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc0" # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_FAT_WRITE=y # CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_versal_mini_emmc1_defconfig b/configs/xilinx_versal_mini_emmc1_defconfig index fef5cadd6e..5de1873dad 100644 --- a/configs/xilinx_versal_mini_emmc1_defconfig +++ b/configs/xilinx_versal_mini_emmc1_defconfig @@ -50,4 +50,5 @@ CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc1" # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_FAT_WRITE=y # CONFIG_EFI_LOADER is not set From b82d520c34de34f549304f1c1e58edcd73b40ce5 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 25 Jun 2019 16:51:37 +0530 Subject: [PATCH 48/85] arm64: versal: Remove unneeded configs for mini configurations The PSCI_RESET and EXPERT are not needed for mini configurations so remove them to save space. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- configs/xilinx_versal_mini_defconfig | 2 ++ configs/xilinx_versal_mini_emmc0_defconfig | 2 ++ configs/xilinx_versal_mini_emmc1_defconfig | 2 ++ 3 files changed, 6 insertions(+) diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig index 98759d0705..742aa1208a 100644 --- a/configs/xilinx_versal_mini_defconfig +++ b/configs/xilinx_versal_mini_defconfig @@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MALLOC_LEN=0x2000 CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_COUNTER_FREQUENCY=2720000 +# CONFIG_PSCI_RESET is not set +# CONFIG_EXPERT is not set # CONFIG_LEGACY_IMAGE_FORMAT is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_BOARD_LATE_INIT is not set diff --git a/configs/xilinx_versal_mini_emmc0_defconfig b/configs/xilinx_versal_mini_emmc0_defconfig index 49386e21d3..7610abf4db 100644 --- a/configs/xilinx_versal_mini_emmc0_defconfig +++ b/configs/xilinx_versal_mini_emmc0_defconfig @@ -7,6 +7,8 @@ CONFIG_ENV_SIZE=0x80 CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_COUNTER_FREQUENCY=2720000 +# CONFIG_PSCI_RESET is not set +# CONFIG_EXPERT is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_BOARD_LATE_INIT is not set # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/xilinx_versal_mini_emmc1_defconfig b/configs/xilinx_versal_mini_emmc1_defconfig index 5de1873dad..ffc913a6eb 100644 --- a/configs/xilinx_versal_mini_emmc1_defconfig +++ b/configs/xilinx_versal_mini_emmc1_defconfig @@ -7,6 +7,8 @@ CONFIG_ENV_SIZE=0x80 CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_COUNTER_FREQUENCY=2720000 +# CONFIG_PSCI_RESET is not set +# CONFIG_EXPERT is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_BOARD_LATE_INIT is not set # CONFIG_DISPLAY_CPUINFO is not set From 0384ac058376aa2fbac9965e0f2a4ddb5729b37a Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Wed, 11 Sep 2019 04:40:11 -0600 Subject: [PATCH 49/85] gpio: zynq: fix issue in set gpio output direction This patch fixes zynq_gpio_direction() to call driver specific zynq_gpio_set_value function rather than top level gpio_set_value. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek --- drivers/gpio/zynq_gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c index 55a5cba068..a760c5bdda 100644 --- a/drivers/gpio/zynq_gpio.c +++ b/drivers/gpio/zynq_gpio.c @@ -292,7 +292,7 @@ static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio, writel(reg, platdata->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); /* set the state of the pin */ - gpio_set_value(gpio, value); + zynq_gpio_set_value(dev, gpio, value); return 0; } From fccfb71004cba0f89eed01bec73b1efc9a149e90 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Fri, 15 Mar 2019 17:46:45 +0530 Subject: [PATCH 50/85] net: xilinx_axiemac: Fill the phy node pointer in phydev This patch assings the phynode pointer to the phydev node as it is needed later in the corresponding phy driver to read phy properties from DT. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/net/xilinx_axi_emac.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index 26c21c6d70..36d651109c 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -93,6 +93,7 @@ struct axidma_priv { struct phy_device *phydev; struct mii_dev *bus; u8 eth_hasnobuf; + int phy_of_handle; }; /* BD descriptors */ @@ -276,6 +277,8 @@ static int axiemac_phy_init(struct udevice *dev) phydev->supported &= supported; phydev->advertising = phydev->supported; priv->phydev = phydev; + if (priv->phy_of_handle) + priv->phydev->node = offset_to_ofnode(priv->phy_of_handle); phy_config(phydev); return 0; @@ -736,8 +739,10 @@ static int axi_emac_ofdata_to_platdata(struct udevice *dev) priv->phyaddr = -1; offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle"); - if (offset > 0) + if (offset > 0) { priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); + priv->phy_of_handle = offset; + } phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); if (phy_mode) From be972b2bd1c75f9e56ff5c7d2c4075a1389dde65 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 11 Apr 2019 10:35:37 +0200 Subject: [PATCH 51/85] arm64: zynqmp: Add generic a2197 system controller config Add generic configuration for a2197-p/-m/-g boards. Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 1 + arch/arm/dts/zynqmp-a2197-revA.dts | 89 ++ .../zynqmp/zynqmp-a2197-revA/psu_init_gpl.c | 1171 +++++++++++++++++ configs/xilinx_zynqmp_a2197_revA_defconfig | 117 ++ 4 files changed, 1378 insertions(+) create mode 100644 arch/arm/dts/zynqmp-a2197-revA.dts create mode 100644 board/xilinx/zynqmp/zynqmp-a2197-revA/psu_init_gpl.c create mode 100644 configs/xilinx_zynqmp_a2197_revA_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 62da168ef8..78c0b09c27 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -247,6 +247,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ dtb-$(CONFIG_ARCH_ZYNQMP) += \ avnet-ultra96-rev1.dtb \ avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb \ + zynqmp-a2197-revA.dtb \ zynqmp-mini.dtb \ zynqmp-mini-emmc0.dtb \ zynqmp-mini-emmc1.dtb \ diff --git a/arch/arm/dts/zynqmp-a2197-revA.dts b/arch/arm/dts/zynqmp-a2197-revA.dts new file mode 100644 index 0000000000..3153138542 --- /dev/null +++ b/arch/arm/dts/zynqmp-a2197-revA.dts @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal a2197 RevA System Controller + * + * (C) Copyright 2019, Xilinx, Inc. + * + * Michal Simek + */ +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include + +/ { + model = "Versal System Controller on a2197 board RevA"; + compatible = "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; + + aliases { + i2c0 = &i2c0; + serial0 = &uart0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + xlnx,eeprom = <&eeprom1 &eeprom0 &eeprom0>; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&uart0 { /* uart0 MIO38-39 */ + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&i2c0 { + status = "okay"; + u-boot,dm-pre-reloc; + clock-frequency = <400000>; + i2c-mux@74 { /* this cover MGT board */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + u-boot,dm-pre-reloc; + /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* Use for storing information about SC board */ + eeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */ + compatible = "atmel,24c32"; + u-boot,dm-pre-reloc; + reg = <0x50>; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + u-boot,dm-pre-reloc; + clock-frequency = <400000>; + i2c-mux@74 { /* This cover processor board */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + u-boot,dm-pre-reloc; + /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* Use for storing information about SC board */ + eeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */ + compatible = "atmel,24c32"; + u-boot,dm-pre-reloc; + reg = <0x50>; + }; + }; + }; +}; diff --git a/board/xilinx/zynqmp/zynqmp-a2197-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-a2197-revA/psu_init_gpl.c new file mode 100644 index 0000000000..ac4a073e1b --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-a2197-revA/psu_init_gpl.c @@ -0,0 +1,1171 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (c) Copyright 2015 Xilinx, Inc. All rights reserved. + */ + +#include +#include + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014000U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U); + psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U); + psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014000U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000200U); + psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U); + + return 1; +} + +static unsigned long psu_clock_init_data(void) +{ + psu_mask_write(0xFF5E0050, 0x063F3F07U, 0x06010C00U); + psu_mask_write(0xFF180360, 0x00000003U, 0x00000001U); + psu_mask_write(0xFF180308, 0x00000006U, 0x00000006U); + psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U); + psu_mask_write(0xFF5E0064, 0x023F3F07U, 0x02010600U); + psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U); + psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U); + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000400U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010B02U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000104U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000202U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_init_data(void) +{ + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0xC1081020U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000202U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00516120U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000008U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00418096U); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00030413U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x006A0000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x00440024U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00310008U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000077FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x15161117U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040422U); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x060C1310U); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00F08000U); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x0A04060CU); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x01040808U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010005U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000401U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040606U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x82160010U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x01B65B96U); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x0495820AU); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x83FF0003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000004U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00001308U); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00070707U); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x0F000000U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x060F0606U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x06060606U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x06060606U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x06060606U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000006U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x04000400U); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000000U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x87001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F07E38U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000DDU); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0000040DU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x0B2E1708U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x282B0510U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0133U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000501U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x012B2B0BU); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x0044260BU); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000C18U); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000044U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000024U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000031U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000056U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x00000021U); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x00000019U); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000016U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x0000000AU); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300BD99U); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAC58U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x0001B39BU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x0001BB9BU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00F50CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00F50CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00F50CU); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00F50CU); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x0129A4A4U); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0C00BD00U); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0C00BD00U); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0C00BD00U); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0C00BD00U); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00BD00U); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x71000000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x71000000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x21100000U); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x21100000U); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); + + return 1; +} + +static unsigned long psu_ddr_qos_init_data(void) +{ + return 1; +} + +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180088, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180090, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180094, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180098, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180100, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180104, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180108, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180110, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180114, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180118, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180120, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180124, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180128, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x00000060U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x00000060U); + psu_mask_write(0xFF180204, 0x00FFE000U, 0x00000000U); + psu_mask_write(0xFF180208, 0xFFFFE3FCU, 0x00B02240U); + psu_mask_write(0xFF18020C, 0x00003FFFU, 0x0000000BU); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_peripherals_pre_init_data(void) +{ + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U); + + return 1; +} + +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x0000007CU, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000C00U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U); + psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U); + psu_mask_write(0xFF180320, 0x33843384U, 0x00801284U); + psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U); + psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U); + psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); + psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U); + psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); + psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x01FC9F08U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + + mask_delay(1); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U); + + mask_delay(5); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + + return 1; +} + +static unsigned long psu_serdes_init_data(void) +{ + psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000FU); + psu_mask_write(0xFD410004, 0x0000001FU, 0x00000008U); + psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD402864, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD406094, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD406368, 0x000000FFU, 0x00000038U); + psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD406370, 0x000000FFU, 0x000000F4U); + psu_mask_write(0xFD406374, 0x000000FFU, 0x00000031U); + psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD40106C, 0x0000000FU, 0x0000000FU); + psu_mask_write(0xFD4000F4, 0x0000000BU, 0x0000000BU); + psu_mask_write(0xFD40506C, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD4040F4, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD4050CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4018F8, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD4018FC, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD401990, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD401924, 0x000000FFU, 0x00000082U); + psu_mask_write(0xFD401928, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401914, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD401940, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40589C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4058F8, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD4058FC, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD405990, 0x000000FFU, 0x00000010U); + psu_mask_write(0xFD405924, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD405928, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD405900, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD405980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD405918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD405940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD405944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD410010, 0x00000077U, 0x00000035U); + psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U); + + return 1; +} + +static unsigned long psu_resetout_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000800U, 0x00000000U); + psu_mask_write(0xFF9E0080, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF9E007C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E023C, 0x00000280U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U); + psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U); + psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U); + psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U); + psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U); + psu_mask_write(0xFE30C200, 0x00023FFFU, 0x00022457U); + psu_mask_write(0xFE30C630, 0x003FFF00U, 0x00000000U); + psu_mask_write(0xFE30C12C, 0x00004000U, 0x00004000U); + psu_mask_write(0xFE30C11C, 0x00000400U, 0x00000400U); + psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); + mask_poll(0xFD4023E4, 0x00000010U); + mask_poll(0xFD4063E4, 0x00000010U); + + return 1; +} + +static unsigned long psu_resetin_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U); + psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000A80U); + psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000001U); + + return 1; +} + +static unsigned long psu_afi_config(void) +{ + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); + psu_mask_write(0xFF419000, 0x00000300U, 0x00000000U); + + return 1; +} + +static void dpll_prog(int ddr_pll_fbdiv, int d_lock_dly, int d_lock_cnt, + int d_lfhf, int d_cp, int d_res) +{ + unsigned int pll_ctrl_regval; + unsigned int pll_status_regval; + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00010000U); + pll_ctrl_regval = pll_ctrl_regval | (1 << 16); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); + pll_ctrl_regval = pll_ctrl_regval & (~0xFE000000U); + pll_ctrl_regval = pll_ctrl_regval | (d_lock_dly << 25); + Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); + pll_ctrl_regval = pll_ctrl_regval & (~0x007FE000U); + pll_ctrl_regval = pll_ctrl_regval | (d_lock_cnt << 13); + Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00000C00U); + pll_ctrl_regval = pll_ctrl_regval | (d_lfhf << 10); + Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); + pll_ctrl_regval = pll_ctrl_regval & (~0x000001E0U); + pll_ctrl_regval = pll_ctrl_regval | (d_cp << 5); + Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); + pll_ctrl_regval = pll_ctrl_regval & (~0x0000000FU); + pll_ctrl_regval = pll_ctrl_regval | (d_res << 0); + Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00007F00U); + pll_ctrl_regval = pll_ctrl_regval | (ddr_pll_fbdiv << 8); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U); + pll_ctrl_regval = pll_ctrl_regval | (1 << 3); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U); + pll_ctrl_regval = pll_ctrl_regval | (1 << 0); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U); + pll_ctrl_regval = pll_ctrl_regval | (0 << 0); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + + pll_status_regval = 0x00000000; + while ((pll_status_regval & 0x00000002U) != 0x00000002U) + pll_status_regval = Xil_In32(((0xFD1A0000U) + 0x00000044)); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U); + pll_ctrl_regval = pll_ctrl_regval | (0 << 3); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); +} + +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; + + for (int tp = 0; tp < 20; tp++) + regval = Xil_In32(0xFD070018); + int cur_PLLCR0; + + cur_PLLCR0 = (Xil_In32(0xFD080068U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SL0PLLCR0; + + cur_DX8SL0PLLCR0 = (Xil_In32(0xFD081404U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SL1PLLCR0; + + cur_DX8SL1PLLCR0 = (Xil_In32(0xFD081444U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SL2PLLCR0; + + cur_DX8SL2PLLCR0 = (Xil_In32(0xFD081484U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SL3PLLCR0; + + cur_DX8SL3PLLCR0 = (Xil_In32(0xFD0814C4U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SL4PLLCR0; + + cur_DX8SL4PLLCR0 = (Xil_In32(0xFD081504U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SLBPLLCR0; + + cur_DX8SLBPLLCR0 = (Xil_In32(0xFD0817C4U) & 0xFFFFFFFFU) >> 0x00000000U; + Xil_Out32(0xFD080068, 0x02120000); + Xil_Out32(0xFD081404, 0x02120000); + Xil_Out32(0xFD081444, 0x02120000); + Xil_Out32(0xFD081484, 0x02120000); + Xil_Out32(0xFD0814C4, 0x02120000); + Xil_Out32(0xFD081504, 0x02120000); + Xil_Out32(0xFD0817C4, 0x02120000); + int cur_fbdiv; + + cur_fbdiv = (Xil_In32(0xFD1A002CU) & 0x00007F00U) >> 0x00000008U; + dpll_prog(48, 63, 625, 3, 3, 2); + for (int tp = 0; tp < 20; tp++) + regval = Xil_In32(0xFD070018); + unsigned int pll_retry = 10; + unsigned int pll_locked = 0; + + while ((pll_retry > 0) && (!pll_locked)) { + Xil_Out32(0xFD080004, 0x00040010); + Xil_Out32(0xFD080004, 0x00040011); + + while ((Xil_In32(0xFD080030) & 0x1) != 1) + ; + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) + >> 31; + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) + >> 16; + pll_retry--; + } + Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16)); + if (!pll_locked) + return (0); + + Xil_Out32(0xFD080004U, 0x00040063U); + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + Xil_Out32(0xFD070010U, 0x80000018U); + Xil_Out32(0xFD0701B0U, 0x00000005U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018); + + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00000331U); + Xil_Out32(0xFD070010U, 0x80000018U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018); + + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00000B36U); + Xil_Out32(0xFD070010U, 0x80000018U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018); + + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00000C21U); + Xil_Out32(0xFD070010U, 0x80000018U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018); + + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00000E19U); + Xil_Out32(0xFD070010U, 0x80000018U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018); + + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00001616U); + Xil_Out32(0xFD070010U, 0x80000018U); + Xil_Out32(0xFD070010U, 0x80000010U); + Xil_Out32(0xFD0701B0U, 0x00000005U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U); + prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000001U); + prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U); + prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U); + prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000002U); + prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U); + for (int tp = 0; tp < 20; tp++) + regval = Xil_In32(0xFD070018); + + Xil_Out32(0xFD080068, cur_PLLCR0); + Xil_Out32(0xFD081404, cur_DX8SL0PLLCR0); + Xil_Out32(0xFD081444, cur_DX8SL1PLLCR0); + Xil_Out32(0xFD081484, cur_DX8SL2PLLCR0); + Xil_Out32(0xFD0814C4, cur_DX8SL3PLLCR0); + Xil_Out32(0xFD081504, cur_DX8SL4PLLCR0); + Xil_Out32(0xFD0817C4, cur_DX8SLBPLLCR0); + for (int tp = 0; tp < 20; tp++) + regval = Xil_In32(0xFD070018); + + dpll_prog(cur_fbdiv, 63, 625, 3, 3, 2); + for (int tp = 0; tp < 2000; tp++) + regval = Xil_In32(0xFD070018); + + prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000000U); + prog_reg(0xFD080004U, 0x00040000U, 0x00000012U, 0x00000001U); + prog_reg(0xFD080004U, 0x00000040U, 0x00000006U, 0x00000001U); + prog_reg(0xFD080004U, 0x00000020U, 0x00000005U, 0x00000001U); + prog_reg(0xFD080004U, 0x00000010U, 0x00000004U, 0x00000001U); + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + for (int tp = 0; tp < 2000; tp++) + regval = Xil_In32(0xFD070018); + + prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000000U); + prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U); + prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U); + prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000003U); + prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U); + for (int tp = 0; tp < 2000; tp++) + regval = Xil_In32(0xFD070018); + + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0014FE01); + + regval = Xil_In32(0xFD080030); + while (regval != 0x8000007E) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD080200U, 0x000091C7U); + regval = Xil_In32(0xFD080030); + while (regval != 0x80008FFF) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD080200U, 0x800091C7U); + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); + if (regval != 0) + return (0); + + Xil_Out32(0xFD080200U, 0x800091C7U); + int cur_R006_tREFPRD; + + cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U; + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); + + Xil_Out32(0xFD080004, 0x00060001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80004001) != 0x80004001) + regval = Xil_In32(0xFD080030); + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); + + Xil_Out32(0xFD080200U, 0x800091C7U); + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); + + Xil_Out32(0xFD080004, 0x0000C001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80000C01) != 0x80000C01) + regval = Xil_In32(0xFD080030); + + prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000000U); + prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000001U); + prog_reg(0xFD0701A0U, 0x80000000U, 0x0000001FU, 0x00000000U); + prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000001U); + Xil_Out32(0xFD070180U, 0x02160010U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + for (int tp = 0; tp < 4000; tp++) + regval = Xil_In32(0xFD070018); + + prog_reg(0xFD080090U, 0x00000FC0U, 0x00000006U, 0x00000007U); + prog_reg(0xFD080090U, 0x00000004U, 0x00000002U, 0x00000001U); + prog_reg(0xFD08070CU, 0x02000000U, 0x00000019U, 0x00000000U); + prog_reg(0xFD08080CU, 0x02000000U, 0x00000019U, 0x00000000U); + prog_reg(0xFD08090CU, 0x02000000U, 0x00000019U, 0x00000000U); + prog_reg(0xFD080A0CU, 0x02000000U, 0x00000019U, 0x00000000U); + prog_reg(0xFD080F0CU, 0x02000000U, 0x00000019U, 0x00000000U); + prog_reg(0xFD080200U, 0x00000010U, 0x00000004U, 0x00000001U); + prog_reg(0xFD080250U, 0x00000002U, 0x00000001U, 0x00000000U); + prog_reg(0xFD080250U, 0x0000000CU, 0x00000002U, 0x00000001U); + prog_reg(0xFD080250U, 0x000000F0U, 0x00000004U, 0x00000000U); + prog_reg(0xFD080250U, 0x00300000U, 0x00000014U, 0x00000001U); + prog_reg(0xFD080250U, 0xF0000000U, 0x0000001CU, 0x00000002U); + prog_reg(0xFD08070CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD08080CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD08090CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080A0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080B0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080C0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080D0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080E0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080F0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080254U, 0x000000FFU, 0x00000000U, 0x00000001U); + prog_reg(0xFD080254U, 0x000F0000U, 0x00000010U, 0x0000000AU); + prog_reg(0xFD080250U, 0x00000001U, 0x00000000U, 0x00000001U); + + return 1; +} + +static int serdes_enb_coarse_saturation(void) +{ + Xil_Out32(0xFD402094, 0x00000010); + Xil_Out32(0xFD406094, 0x00000010); + Xil_Out32(0xFD40A094, 0x00000010); + Xil_Out32(0xFD40E094, 0x00000010); + return 1; +} + +static int serdes_fixcal_code(void) +{ + int maskstatus = 1; + unsigned int rdata = 0; + unsigned int match_pmos_code[23]; + unsigned int match_nmos_code[23]; + unsigned int match_ical_code[7]; + unsigned int match_rcal_code[7]; + unsigned int p_code = 0; + unsigned int n_code = 0; + unsigned int i_code = 0; + unsigned int r_code = 0; + unsigned int repeat_count = 0; + unsigned int L3_TM_CALIB_DIG20 = 0; + unsigned int L3_TM_CALIB_DIG19 = 0; + unsigned int L3_TM_CALIB_DIG18 = 0; + unsigned int L3_TM_CALIB_DIG16 = 0; + unsigned int L3_TM_CALIB_DIG15 = 0; + unsigned int L3_TM_CALIB_DIG14 = 0; + int i = 0, count = 0; + + rdata = Xil_In32(0xFD40289C); + rdata = rdata & ~0x03; + rdata = rdata | 0x1; + Xil_Out32(0xFD40289C, rdata); + + do { + if (count == 1100000) + break; + rdata = Xil_In32(0xFD402B1C); + count++; + } while ((rdata & 0x0000000E) != 0x0000000E); + + for (i = 0; i < 23; i++) { + match_pmos_code[i] = 0; + match_nmos_code[i] = 0; + } + for (i = 0; i < 7; i++) { + match_ical_code[i] = 0; + match_rcal_code[i] = 0; + } + + do { + Xil_Out32(0xFD410010, 0x00000000); + Xil_Out32(0xFD410014, 0x00000000); + + Xil_Out32(0xFD410010, 0x00000001); + Xil_Out32(0xFD410014, 0x00000000); + + maskstatus = mask_poll(0xFD40EF14, 0x2); + if (maskstatus == 0) { + xil_printf("#SERDES initialization timed out\n\r"); + return maskstatus; + } + + p_code = mask_read(0xFD40EF18, 0xFFFFFFFF); + n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF); + ; + i_code = mask_read(0xFD40EF24, 0xFFFFFFFF); + r_code = mask_read(0xFD40EF28, 0xFFFFFFFF); + ; + + if (p_code >= 0x26 && p_code <= 0x3C) + match_pmos_code[p_code - 0x26] += 1; + + if (n_code >= 0x26 && n_code <= 0x3C) + match_nmos_code[n_code - 0x26] += 1; + + if (i_code >= 0xC && i_code <= 0x12) + match_ical_code[i_code - 0xC] += 1; + + if (r_code >= 0x6 && r_code <= 0xC) + match_rcal_code[r_code - 0x6] += 1; + + } while (repeat_count++ < 10); + + for (i = 0; i < 23; i++) { + if (match_pmos_code[i] >= match_pmos_code[0]) { + match_pmos_code[0] = match_pmos_code[i]; + p_code = 0x26 + i; + } + if (match_nmos_code[i] >= match_nmos_code[0]) { + match_nmos_code[0] = match_nmos_code[i]; + n_code = 0x26 + i; + } + } + + for (i = 0; i < 7; i++) { + if (match_ical_code[i] >= match_ical_code[0]) { + match_ical_code[0] = match_ical_code[i]; + i_code = 0xC + i; + } + if (match_rcal_code[i] >= match_rcal_code[0]) { + match_rcal_code[0] = match_rcal_code[i]; + r_code = 0x6 + i; + } + } + + L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0); + L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7); + + L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18); + L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) + | 0x20 | 0x4 | ((n_code >> 3) & 0x3); + + L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F); + L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10; + + L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8); + L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7); + + L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30); + L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) + | 0x40 | 0x8 | ((i_code >> 1) & 0x7); + + L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F); + L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40; + + Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20); + Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19); + Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18); + Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16); + Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15); + Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14); + return maskstatus; +} + +static int init_serdes(void) +{ + int status = 1; + + status &= psu_resetin_init_data(); + + status &= serdes_fixcal_code(); + status &= serdes_enb_coarse_saturation(); + + status &= psu_serdes_init_data(); + status &= psu_resetout_init_data(); + + return status; +} + +static void init_peripheral(void) +{ + psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU); +} + +int psu_init(void) +{ + int status = 1; + + status &= psu_mio_init_data(); + status &= psu_peripherals_pre_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + status &= psu_peripherals_init_data(); + status &= init_serdes(); + init_peripheral(); + + status &= psu_afi_config(); + psu_ddr_qos_init_data(); + + if (status == 0) + return 1; + return 0; +} diff --git a/configs/xilinx_zynqmp_a2197_revA_defconfig b/configs/xilinx_zynqmp_a2197_revA_defconfig new file mode 100644 index 0000000000..2d70805dc3 --- /dev/null +++ b/configs/xilinx_zynqmp_a2197_revA_defconfig @@ -0,0 +1,117 @@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal" +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_ZYNQMP_USB=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y +CONFIG_SYS_PROMPT="ZynqMP> " +CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SDRAM=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-revA" +CONFIG_ENV_IS_IN_FAT=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_CLK_ZYNQMP=y +CONFIG_DFU_RAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_DM_GPIO=y +CONFIG_XILINX_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_MARVELL=y +CONFIG_PHY_NATSEMI=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_TI=y +CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y +CONFIG_PHY_GIGE=y +CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_ZYNQMP_GQSPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_ZYNQMP=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Xilinx" +CONFIG_USB_GADGET_VENDOR_NUM=0x03FD +CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 +CONFIG_USB_FUNCTION_THOR=y +CONFIG_SPL_GZIP=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y From 917c57845a749613132bd5a8665a61166b5b4a61 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 27 Mar 2019 20:14:19 +0100 Subject: [PATCH 52/85] arm64: zynqmp: Add System Controller for a2197-g/p Similar SCs but different wiring. - dc_i2c is connected to X-PRC cards that's why label is required to have an option to hook up some devices. - Exactly identify i2c devices on x-prc boards. In case of missing i2c connection devices won't be accessible. - USB 0 should be device mode with super speed. - USB 1 should be host mode. - Fix i2c mux reset pin entry - commented, not verified. - Fix i2c1 eeprom compatible string - it is an ST 128Kbit device. Need to use atmel fallback. - Fix si570 I2C slave address and add corresponding part numbers. - Enable AMS for system monitoring. - phy reset property should be commented because it will throw a warning dump when called from context that can sleep. No support for phys property (zynqmp phy driver) with SGMII. Add is-internal-pcspma property required by uboot. Signed-off-by: Michal Simek Signed-off-by: Harini Katakam --- arch/arm/dts/Makefile | 2 + arch/arm/dts/zynqmp-a2197-g-revA.dts | 282 +++++++++ arch/arm/dts/zynqmp-a2197-p-revA.dts | 567 +++++++++++++++++++ board/xilinx/zynqmp/zynqmp-a2197-g-revA | 1 + board/xilinx/zynqmp/zynqmp-a2197-p-revA | 1 + configs/xilinx_zynqmp_a2197_g_revA_defconfig | 116 ++++ configs/xilinx_zynqmp_a2197_p_revA_defconfig | 117 ++++ configs/xilinx_zynqmp_a2197_revA_defconfig | 1 + 8 files changed, 1087 insertions(+) create mode 100644 arch/arm/dts/zynqmp-a2197-g-revA.dts create mode 100644 arch/arm/dts/zynqmp-a2197-p-revA.dts create mode 120000 board/xilinx/zynqmp/zynqmp-a2197-g-revA create mode 120000 board/xilinx/zynqmp/zynqmp-a2197-p-revA create mode 100644 configs/xilinx_zynqmp_a2197_g_revA_defconfig create mode 100644 configs/xilinx_zynqmp_a2197_p_revA_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 78c0b09c27..dd1060acd6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -248,6 +248,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ avnet-ultra96-rev1.dtb \ avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb \ zynqmp-a2197-revA.dtb \ + zynqmp-a2197-g-revA.dtb \ + zynqmp-a2197-p-revA.dtb \ zynqmp-mini.dtb \ zynqmp-mini-emmc0.dtb \ zynqmp-mini-emmc1.dtb \ diff --git a/arch/arm/dts/zynqmp-a2197-g-revA.dts b/arch/arm/dts/zynqmp-a2197-g-revA.dts new file mode 100644 index 0000000000..c6072b5f42 --- /dev/null +++ b/arch/arm/dts/zynqmp-a2197-g-revA.dts @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal a2197 RevA System Controller on MGT + * + * (C) Copyright 2019, Xilinx, Inc. + * + * Michal Simek + */ +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include + +/ { + model = "Versal System Controller on a2197 MGT Char board RevA"; + compatible = "xlnx,zynqmp-a2197-g-revA", "xlnx,zynqmp-a2197-revA", + "xlnx,zynqmp-a2197", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem0; + gpio0 = &gpio; + i2c0 = &i2c0; + mmc0 = &sdhci0; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &dcc; + usb0 = &usb0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + xlnx,eeprom = <&eeprom>; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&sdhci0 { /* emmc MIO 13-23 16GB */ + status = "okay"; + non-removable; + disable-wp; + bus-width = <8>; + xlnx,mio_bank = <0>; +}; + +&uart0 { /* uart0 MIO38-39 */ + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&gem0 { /* eth MDIO 76/77 */ + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "sgmii"; + is-internal-pcspma; + phy0: phy@0 { /* marwell m88e1512 */ + reg = <0>; + reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; +/* xlnx,phy-type = ; */ + }; +/* phy-names = "..."; + phys = <&lane0 PHY_TYPE_SGMII ... > + Note: lane0 sgmii/lane1 usb3 */ +}; + +&gpio { + status = "okay"; + gpio-line-names = "", "", "", "", "", /* 0 - 4 */ + "", "", "", "", "", /* 5 - 9 */ + "", "", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ + "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ + "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ + "", "", "", "", "", /* 25 - 29 */ + "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ + "LP_I2C0_PMC_SDA", "", "", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ + "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ + "", "", "", "", "", /* 45 - 49 */ + "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ + "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ + "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ + "", "", "", "", "", /* 65 - 69 */ + "", "", "", "", "", /* 70 - 74 */ + "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ + "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ + "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ + "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ + "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ + "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ + "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ + "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ + "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ + "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ + "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ + "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ + "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ + "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ + "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ + "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ + "", "", "", "", "", /* 150 - 154 */ + "", "", "", "", "", /* 155 - 159 */ + "", "", "", "", "", /* 160 - 164 */ + "", "", "", "", "", /* 165 - 169 */ + "", "", "", ""; /* 170 - 174 */ +}; + +&i2c0 { /* MIO 34-35 - can't stay here */ + status = "okay"; + clock-frequency = <400000>; + scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; + i2c-mux@74 { /* u94 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* Use for storing information about SC board */ + eeprom: eeprom@50 { /* u96 - 24LC32A - 256B */ + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + i2c@1 { /* CM_I2C_SCL - Samtec */ + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + i2c@2 { /* PMBUS - AFX_PMBUS */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + tps544@d { /* u85 */ + compatible = "ti,tps544b25"; + reg = <0xd>; + }; + tps544@10 { /* u73 */ + compatible = "ti,tps544b25"; + reg = <0x10>; + }; + tps544@11 { /* u76 */ + compatible = "ti,tps544b25"; + reg = <0x11>; + }; + tps544@12 { /* u77 */ + compatible = "ti,tps544b25"; + reg = <0x12>; + }; + tps544@13 { /* u80 */ + compatible = "ti,tps544b25"; + reg = <0x13>; + }; + tps544@14 { /* u81 */ + compatible = "ti,tps544b25"; + reg = <0x14>; + }; + tps544@15 { /* u83 */ + compatible = "ti,tps544b25"; + reg = <0x15>; + }; + tps544@16 { /* u63 */ + compatible = "ti,tps544b25"; + reg = <0x16>; + }; + tps544@17 { /* u66 */ + compatible = "ti,tps544b25"; + reg = <0x17>; + }; + tps544@18 { /* u67 */ + compatible = "ti,tps544b25"; + reg = <0x18>; + }; + tps544@19 { /* u69 */ + compatible = "ti,tps544b25"; + reg = <0x19>; + }; + tps544@1d { /* u88 */ + compatible = "ti,tps544b25"; + reg = <0x1d>; + }; + tps544@1e { /* u89 */ + compatible = "ti,tps544b25"; + reg = <0x1e>; + }; + tps544@1f { /* u87 */ + compatible = "ti,tps544b25"; + reg = <0x1f>; + }; + tps544@20 { /* u71 */ + compatible = "ti,tps544b25"; + reg = <0x20>; + }; + ina226@40 { /* u74 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + ina226@41 { /* u75 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <1000>; + }; + ina226@42 { /* u78 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + ina226@43 { /* u79 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <1000>; + }; + ina226@44 { /* u82 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + ina226@45 { /* u84 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + tps53681@c0 { /* u53 - FIXME name - don't know what it does - also vcc_io_soc */ + compatible = "ti,tps53681"; /* FIXME no linux driver */ + reg = <0xc0>; + }; + }; + i2c@3 { /* fmc1 via JA2G */ + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + eeprom_fmc1: eeprom@50 { /* on FMC */ + compatible = "atmel,24c04"; + reg = <0x50>; + }; + }; + i2c@4 { /* fmc2 via JA3G */ + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + eeprom_fmc2: eeprom@50 { /* on FMC */ + compatible = "atmel,24c04"; + reg = <0x50>; + }; + }; + i2c@5 { /* fmc3 via JA4G */ + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + eeprom_fmc3: eeprom@50 { /* on FMC */ + compatible = "atmel,24c04"; + reg = <0x50>; + }; + }; + i2c@6 { /* ddr dimm */ + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + /* 7 unused */ + }; +}; + +&usb0 { /* USB0 MIO52-63 */ + status = "okay"; + xlnx,usb-polarity = <0>; + xlnx,usb-reset-mode = <0>; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "peripheral"; + maximum-speed = "high-speed"; +}; diff --git a/arch/arm/dts/zynqmp-a2197-p-revA.dts b/arch/arm/dts/zynqmp-a2197-p-revA.dts new file mode 100644 index 0000000000..322b36e391 --- /dev/null +++ b/arch/arm/dts/zynqmp-a2197-p-revA.dts @@ -0,0 +1,567 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal a2197 RevA System Controller + * + * (C) Copyright 2019, Xilinx, Inc. + * + * Michal Simek + */ +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include + +/ { + model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ + compatible = "xlnx,zynqmp-a2197-p-revA", "xlnx,zynqmp-a2197-revA", + "xlnx,zynqmp-a2197", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem0; + gpio0 = &gpio; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &dcc; + usb0 = &usb0; + usb1 = &usb1; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + xlnx,eeprom = <&eeprom>; + /* xlnx,fmc-eeprom = FIXME */ + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */ + }; +}; + +&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ + status = "okay"; + non-removable; + disable-wp; + bus-width = <8>; + xlnx,mio_bank = <0>; +}; + +&uart0 { /* uart0 MIO38-39 */ + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&uart1 { /* uart1 MIO40-41 */ + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&sdhci1 { /* sd1 MIO45-51 cd in place */ + status = "okay"; + no-1-8-v; + disable-wp; + xlnx,mio_bank = <1>; +}; + +&gem0 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "sgmii"; /* DTG generates this properly 1512 */ + is-internal-pcspma; + /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ + phy0: phy@0 { + reg = <0>; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = "", "", "", "", "", /* 0 - 4 */ + "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ + "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ + "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ + "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ + "", "", "", "", "", /* 25 - 29 */ + "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ + "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ + "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ + "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ + "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ + "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ + "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ + "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ + "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ + "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ + "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ + "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ + "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ + "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ + "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ + "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ + "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ + "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ + "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ + "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ + "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ + "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ + "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ + "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ + "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ + "", "", "", "", "", /* 150 - 154 */ + "", "", "", "", "", /* 155 - 159 */ + "", "", "", "", "", /* 160 - 164 */ + "", "", "", "", "", /* 165 - 169 */ + "", "", "", ""; /* 170 - 174 */ +}; + +&i2c0 { /* MIO 34-35 - can't stay here */ + status = "okay"; + clock-frequency = <400000>; + i2c-mux@74 { /* u33 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + i2c@0 { /* PMBUS1 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* On connector J98 */ + reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + reg = <0x7>; + regulator-name = "reg_vcc_fmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2600000>; + /* enable-gpio = <&gpio0 23 0x4>; optional */ + }; + reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + reg = <0x8>; + }; + reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + reg = <0x9>; + }; + reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + reg = <0xa>; + }; + reg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ + compatible = "ti,tps53681"; /* FIXME no linux driver */ + reg = <0xc0>; + /* vccint, vcc_io_soc */ + }; + }; + i2c@1 { /* PMBUS1_INA226 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* FIXME check alerts comming to SC */ + vcc_fmc: ina226@42 { /* u81 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + vcc_ram: ina226@43 { /* u82 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + vcc_pslp: ina226@44 { /* u84 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; + }; + vcc_psfp: ina226@45 { /* u87 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + }; + i2c@2 { /* PMBUS2 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* On connector J104 */ + reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + reg = <0xd>; + }; + reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + reg = <0xe>; + }; + reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + reg = <0xf>; + }; + reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + reg = <0x10>; + }; + reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + reg = <0x11>; + }; + reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + reg = <0x12>; + }; + reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + reg = <0x13>; + }; + reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + reg = <0x14>; + }; + reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + reg = <0x15>; + }; + reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + reg = <0x16>; + }; + reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + reg = <0x17>; + }; + reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + reg = <0x19>; + }; + reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + reg = <0x1a>; + }; + reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + reg = <0x1b>; + }; + reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + reg = <0x1c>; + }; + reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + reg = <0x1d>; + }; + reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + reg = <0x1e>; + }; + reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + reg = <0x1f>; + }; + }; + i2c@3 { /* PMBUS2_INA226 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* FIXME check alerts coming to SC */ + vccaux: ina226@40 { /* u89 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + vccaux_fmc: ina226@41 { /* u91 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + vcco_500: ina226@42 { /* u92 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + vcco_501: ina226@43 { /* u94 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + vcco_502: ina226@44 { /* u96 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; + }; + vcco_503: ina226@45 { /* u98 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + vcc_1v8: ina226@46 { /* u100 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <5000>; + }; + vcc_3v3: ina226@47 { /* u103 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + vcc_1v2_ddr4: ina226@48 { /* u105 */ + compatible = "ti,ina226"; + reg = <0x48>; + shunt-resistor = <1000>; + }; + vcc1v1_lp4: ina226@49 { /* u107 */ + compatible = "ti,ina226"; + reg = <0x49>; + shunt-resistor = <5000>; + }; + vadj_fmc: ina226@4a { /* u110 */ + compatible = "ti,ina226"; + reg = <0x4a>; + shunt-resistor = <5000>; + }; + mgtyavcc: ina226@4b { /* u112 */ + compatible = "ti,ina226"; + reg = <0x4b>; + shunt-resistor = <1000>; + }; + mgtyavtt: ina226@4c { /* u113 */ + compatible = "ti,ina226"; + reg = <0x4c>; + shunt-resistor = <1000>; + }; + mgtyvccaux: ina226@4d { /* u116 */ + compatible = "ti,ina226"; + reg = <0x4d>; + shunt-resistor = <5000>; + }; + vcc_bat: ina226@4e { /* u12 */ + compatible = "ti,ina226"; + reg = <0x4e>; + shunt-resistor = <10000000>; /* 10 ohm */ + }; + }; + i2c@4 { /* LP_I2C_SM */ + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* connected to J212G */ + /* zynqmp sm alert or samtec J212H */ + }; + /* 5-7 unused */ + }; +}; + +&i2c1 { /* i2c1 MIO 36-37 */ + status = "okay"; + clock-frequency = <400000>; + + /* Must be enabled via J242 */ + eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ + compatible = "atmel,24c02"; + reg = <0x51>; + }; + + i2c-mux@74 { /* u35 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ + dc_i2c: i2c@0 { /* DC_I2C */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* Use for storing information about SC board */ + eeprom: eeprom@54 { /* u34 - m24128 16kB */ + compatible = "st,24c128", "atmel,24c128"; + reg = <0x54>; + }; + si570_ref_clk: clock-generator@5d { /* u32 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; /* 570JAC000900DG */ + temperature-stability = <50>; + factory-fout = <156250000>; /* FIXME every chip can be different */ + clock-frequency = <33333333>; + clock-output-names = "REF_CLK"; /* FIXME */ + }; + /* Connection via Samtec J212D */ + /* Use for storing information about X-PRC card */ + x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ + compatible = "atmel,24c02"; + reg = <0x52>; + }; + + /* Use for setting up certain features on X-PRC card */ + x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; /* IRQ not connected */ + #gpio-cells = <2>; + gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", + "", "", "", ""; + gtr_sel0 { + gpio-hog; + gpios = <0 0>; + input; /* FIXME add meaning */ + line-name = "sw4_1"; + }; + gtr_sel1 { + gpio-hog; + gpios = <1 0>; + input; /* FIXME add meaning */ + line-name = "sw4_2"; + }; + gtr_sel2 { + gpio-hog; + gpios = <2 0>; + input; /* FIXME add meaning */ + line-name = "sw4_3"; + }; + gtr_sel3 { + gpio-hog; + gpios = <3 0>; + input; /* FIXME add meaning */ + line-name = "sw4_4"; + }; + }; + }; + i2c@1 { /* FMCP1_IIC */ + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* FIXME connection to Samtec J51C */ + /* expected eeprom 0x50 SE cards */ + }; + i2c@2 { /* FMCP2_IIC */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* FIXME connection to Samtec J53C */ + /* expected eeprom 0x50 SE cards */ + }; + i2c@3 { /* DDR4_DIMM1 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + si570_ddr_dimm1: clock-generator@60 { /* u2 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; /* 570BAB000299DG */ + temperature-stability = <50>; + factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ + clock-frequency = <33333333>; + clock-output-names = "REF_CLK"; /* FIXME */ + }; + /* 0x50 SPD? */ + }; + i2c@4 { /* DDR4_DIMM2 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + si570_ddr_dimm2: clock-generator@60 { /* u3 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; /* 570BAB000299DG */ + temperature-stability = <50>; + factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ + clock-frequency = <33333333>; + clock-output-names = "REF_CLK"; /* FIXME */ + }; + /* 0x50 SPD? */ + }; + i2c@5 { /* LPDDR4_SI570_CLK */ + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + si570_lpddr4: clock-generator@60 { /* u4 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x60>; /* 570BAB000299DG */ + temperature-stability = <50>; + factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ + clock-frequency = <33333333>; + clock-output-names = "LPDDR4_SI570_CLK"; + }; + }; + i2c@6 { /* HSDP_SI570 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + si570_hsdp: clock-generator@5d { /* u5 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; /* 570JAC000900DG */ + temperature-stability = <50>; + factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ + clock-frequency = <33333333>; + clock-output-names = "HSDP_SI570"; + }; + }; + i2c@7 { /* PCIE_CLK */ + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ + /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ + /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ + clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ + #clock-cells = <1>; /* author David Cater */ + compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ + reg = <0xd8>; + /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ + /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ + + }; + + }; + }; +}; + +&usb0 { + status = "okay"; + xlnx,usb-polarity = <0>; + xlnx,usb-reset-mode = <0>; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "peripheral"; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + maximum-speed = "super-speed"; +}; + +&usb1 { + status = "okay"; + xlnx,usb-polarity = <0>; + xlnx,usb-reset-mode = <0>; +}; + +&dwc3_1 { + /delete-property/ phy-names ; + /delete-property/ phys ; + dr_mode = "host"; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk ; + snps,dis_u3_susphy_quirk ; + status = "okay"; +}; + +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + +&ams_pl { + status = "okay"; +}; diff --git a/board/xilinx/zynqmp/zynqmp-a2197-g-revA b/board/xilinx/zynqmp/zynqmp-a2197-g-revA new file mode 120000 index 0000000000..a64c140b86 --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-a2197-g-revA @@ -0,0 +1 @@ +zynqmp-a2197-revA \ No newline at end of file diff --git a/board/xilinx/zynqmp/zynqmp-a2197-p-revA b/board/xilinx/zynqmp/zynqmp-a2197-p-revA new file mode 120000 index 0000000000..a64c140b86 --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-a2197-p-revA @@ -0,0 +1 @@ +zynqmp-a2197-revA \ No newline at end of file diff --git a/configs/xilinx_zynqmp_a2197_g_revA_defconfig b/configs/xilinx_zynqmp_a2197_g_revA_defconfig new file mode 100644 index 0000000000..2f6dc7641a --- /dev/null +++ b/configs/xilinx_zynqmp_a2197_g_revA_defconfig @@ -0,0 +1,116 @@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal" +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_ZYNQMP_USB=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y +CONFIG_SYS_PROMPT="ZynqMP> " +CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SDRAM=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-g-revA" +CONFIG_ENV_IS_IN_FAT=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_CLK_ZYNQMP=y +CONFIG_DFU_RAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_DM_GPIO=y +CONFIG_XILINX_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_MARVELL=y +CONFIG_PHY_NATSEMI=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_TI=y +CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y +CONFIG_PHY_GIGE=y +CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_ZYNQMP_GQSPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_ZYNQMP=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Xilinx" +CONFIG_USB_GADGET_VENDOR_NUM=0x03FD +CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 +CONFIG_USB_FUNCTION_THOR=y +CONFIG_SPL_GZIP=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_a2197_p_revA_defconfig b/configs/xilinx_zynqmp_a2197_p_revA_defconfig new file mode 100644 index 0000000000..4ce634cdaa --- /dev/null +++ b/configs/xilinx_zynqmp_a2197_p_revA_defconfig @@ -0,0 +1,117 @@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal" +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_ZYNQMP_USB=y +CONFIG_SPL_ZYNQMP_TWO_SDHCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y +CONFIG_SYS_PROMPT="ZynqMP> " +CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SDRAM=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-p-revA" +CONFIG_ENV_IS_IN_FAT=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_CLK_ZYNQMP=y +CONFIG_DFU_RAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_DM_GPIO=y +CONFIG_XILINX_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_MARVELL=y +CONFIG_PHY_NATSEMI=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_TI=y +CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y +CONFIG_PHY_GIGE=y +CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_ZYNQMP_GQSPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_ZYNQMP=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Xilinx" +CONFIG_USB_GADGET_VENDOR_NUM=0x03FD +CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 +CONFIG_USB_FUNCTION_THOR=y +CONFIG_SPL_GZIP=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_a2197_revA_defconfig b/configs/xilinx_zynqmp_a2197_revA_defconfig index 2d70805dc3..2859ef553e 100644 --- a/configs/xilinx_zynqmp_a2197_revA_defconfig +++ b/configs/xilinx_zynqmp_a2197_revA_defconfig @@ -44,6 +44,7 @@ CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-revA" +CONFIG_OF_LIST="zynqmp-a2197-revA zynqmp-a2197-g-revA zynqmp-a2197-p-revA" CONFIG_ENV_IS_IN_FAT=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y From 64eb13bfd7247269a82756e7d8dc3d68af4ea8ad Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 12 Apr 2019 12:19:22 +0200 Subject: [PATCH 53/85] arm64: zynqmp: Add a2197 memory board revA Similar to processor board but i2c structure is completely different. Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 1 + arch/arm/dts/zynqmp-a2197-m-revA.dts | 461 +++++++++++++++++++ board/xilinx/zynqmp/zynqmp-a2197-m-revA | 1 + configs/xilinx_zynqmp_a2197_m_revA_defconfig | 116 +++++ configs/xilinx_zynqmp_a2197_revA_defconfig | 2 +- 5 files changed, 580 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/zynqmp-a2197-m-revA.dts create mode 120000 board/xilinx/zynqmp/zynqmp-a2197-m-revA create mode 100644 configs/xilinx_zynqmp_a2197_m_revA_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index dd1060acd6..2d95a99d26 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -249,6 +249,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb \ zynqmp-a2197-revA.dtb \ zynqmp-a2197-g-revA.dtb \ + zynqmp-a2197-m-revA.dtb \ zynqmp-a2197-p-revA.dtb \ zynqmp-mini.dtb \ zynqmp-mini-emmc0.dtb \ diff --git a/arch/arm/dts/zynqmp-a2197-m-revA.dts b/arch/arm/dts/zynqmp-a2197-m-revA.dts new file mode 100644 index 0000000000..e4b45eafe4 --- /dev/null +++ b/arch/arm/dts/zynqmp-a2197-m-revA.dts @@ -0,0 +1,461 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal a2197 RevA System Controller + * + * (C) Copyright 2019, Xilinx, Inc. + * + * Michal Simek + */ +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include + +/ { + model = "Versal System Controller on a2197 Memory Char board RevA"; + compatible = "xlnx,zynqmp-a2197-m-revA", "xlnx,zynqmp-a2197-revA", + "xlnx,zynqmp-a2197", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem0; + gpio0 = &gpio; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &dcc; + usb0 = &usb0; + usb1 = &usb1; + spi0 = &qspi; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + xlnx,eeprom = <&eeprom>; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */ + }; +}; + +&qspi { + status = "okay"; + is-dual = <1>; + flash@0 { + compatible = "m25p80", "spi-flash"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + }; +}; + +&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ + status = "okay"; + non-removable; + disable-wp; + bus-width = <8>; + xlnx,mio_bank = <0>; /* FIXME tap delay */ +}; + +&uart0 { /* uart0 MIO38-39 */ + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&uart1 { /* uart1 MIO40-41 */ + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&sdhci1 { /* sd1 MIO45-51 cd in place */ + status = "disable"; + no-1-8-v; + disable-wp; + xlnx,mio_bank = <1>; +}; + +&gem0 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "sgmii"; /* DTG generates this properly 1512 */ + phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; + phy0: phy@0 { /* marwell m88e1512 - SGMII */ + reg = <0>; +/* xlnx,phy-type = ; */ + }; +/* phy-names = "..."; + phys = <&lane0 PHY_TYPE_SGMII ... > + Note: lane0 sgmii/lane1 usb3 */ +}; + +&gpio { + status = "okay"; + gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ + "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ + "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ + "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ + "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ + "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ + "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ + "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ + "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ + "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ + "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ + "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ + "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ + "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ + "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ + "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ + "", "", "", "", "", /* 78 - 79 */ + "", "", "", "", "", /* 80 - 84 */ + "", "", "", "", "", /* 85 -89 */ + "", "", "", "", "", /* 90 - 94 */ + "", "", "", "", "", /* 95 - 99 */ + "", "", "", "", "", /* 100 - 104 */ + "", "", "", "", "", /* 105 - 109 */ + "", "", "", "", "", /* 110 - 114 */ + "", "", "", "", "", /* 115 - 119 */ + "", "", "", "", "", /* 120 - 124 */ + "", "", "", "", "", /* 125 - 129 */ + "", "", "", "", "", /* 130 - 134 */ + "", "", "", "", "", /* 135 - 139 */ + "", "", "", "", "", /* 140 - 144 */ + "", "", "", "", "", /* 145 - 149 */ + "", "", "", "", "", /* 150 - 154 */ + "", "", "", "", "", /* 155 - 159 */ + "", "", "", "", "", /* 160 - 164 */ + "", "", "", "", "", /* 165 - 169 */ + "", "", "", ""; /* 170 - 174 */ +}; + +&i2c0 { /* MIO 34-35 - can't stay here */ + status = "okay"; + clock-frequency = <400000>; + i2c-mux@74 { /* u46 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ + i2c@0 { /* PMBUS must be enabled via SW21 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + reg_vcc1v2_lp4: tps544@15 { /* u97 */ + compatible = "ti,tps544b25"; + reg = <0x15>; + }; + reg_vcc1v1_lp4: tps544@16 { /* u95 */ + compatible = "ti,tps544b25"; + reg = <0x16>; + }; + reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ + compatible = "ti,tps544b25"; + reg = <0x17>; + }; + /* UTIL_PMBUS connection */ + reg_vcc1v8: tps544@13 { /* u92 */ + compatible = "ti,tps544b25"; + reg = <0x13>; + }; + reg_vcc3v3: tps544@14 { /* u93 */ + compatible = "ti,tps544b25"; + reg = <0x14>; + }; + reg_vcc5v0: tps544@1e { /* u94 */ + compatible = "ti,tps544b25"; + reg = <0x1e>; + }; + }; + i2c@1 { /* PMBUS_INA226 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + vcc_aux: ina226@42 { /* u86 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + vcc_ram: ina226@43 { /* u81 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + vcc1v1_lp4: ina226@46 { /* u96 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <5000>; + }; + vcc1v2_lp4: ina226@47 { /* u98 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + vdd1_1v8_lp4: ina226@48 { /* u100 */ + compatible = "ti,ina226"; + reg = <0x48>; + shunt-resistor = <5000>; + }; + vcc0v6_lp4: ina226@49 { /* u101 */ + compatible = "ti,ina226"; + reg = <0x49>; + shunt-resistor = <5000>; + }; + }; + i2c@2 { /* PMBUS1 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + reg_vccint: tps53681@c0 { /* u69 */ + compatible = "ti,tps53681"; /* FIXME no linux driver */ + reg = <0xc0>; + }; + reg_vcc_pmc: tps544@7 { /* u80 */ + compatible = "ti,tps544b25"; + reg = <0x7>; + }; + reg_vcc_ram: tps544@8 { /* u82 */ + compatible = "ti,tps544b25"; + reg = <0x8>; + }; + reg_vcc_pslp: tps544@9 { /* u83 */ + compatible = "ti,tps544b25"; + reg = <0x9>; + }; + reg_vcc_psfp: tps544@a { /* u84 */ + compatible = "ti,tps544b25"; + reg = <0xa>; + }; + reg_vccaux: tps544@d { /* u85 */ + compatible = "ti,tps544b25"; + reg = <0xd>; + }; + reg_vccaux_pmc: tps544@e { /* u87 */ + compatible = "ti,tps544b25"; + reg = <0xe>; + }; + reg_vcco_500: tps544@f { /* u88 */ + compatible = "ti,tps544b25"; + reg = <0xf>; + }; + reg_vcco_501: tps544@10 { /* u89 */ + compatible = "ti,tps544b25"; + reg = <0x10>; + }; + reg_vcco_502: tps544@11 { /* u90 */ + compatible = "ti,tps544b25"; + reg = <0x11>; + }; + reg_vcco_503: tps544@12 { /* u91 */ + compatible = "ti,tps544b25"; + reg = <0x12>; + }; + }; + i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ + #address-cells = <1>; + #size-cells = <0>; + /* reg = <3>; */ + }; + i2c@4 { /* LP_I2C_SM */ + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* connected to U20G */ + }; + /* 5-7 unused */ + }; +}; + +/* TODO sysctrl via J239 */ +/* TODO samtec J212G/H via J242 */ +/* TODO teensy via U30 PCA9543A bus 1 */ +&i2c1 { /* i2c1 MIO 36-37 */ + status = "okay"; + clock-frequency = <400000>; + + /* Must be enabled via J242 */ + eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ + compatible = "atmel,24c02"; + reg = <0x51>; + }; + + i2c-mux@74 { /* u35 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ + dc_i2c: i2c@0 { /* DC_I2C */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* Use for storing information about SC board */ + eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ + compatible = "atmel,24c08"; + reg = <0x54>; + }; + si570_ref_clk: clock-generator@5d { /* u26 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; /* FIXME addr */ + temperature-stability = <50>; + factory-fout = <156250000>; /* FIXME every chip can be different */ + clock-frequency = <33333333>; + clock-output-names = "REF_CLK"; /* FIXME */ + }; + /* Connection via Samtec U20D */ + /* Use for storing information about X-PRC card */ + x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ + compatible = "atmel,24c02"; + reg = <0x52>; + }; + + /* Use for setting up certain features on X-PRC card */ + x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; /* IRQ not connected */ + #gpio-cells = <2>; + gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", + "", "", "", ""; + gtr_sel0 { + gpio-hog; + gpios = <0 0>; + input; /* FIXME add meaning */ + line-name = "sw4_1"; + }; + gtr_sel1 { + gpio-hog; + gpios = <1 0>; + input; /* FIXME add meaning */ + line-name = "sw4_2"; + }; + gtr_sel2 { + gpio-hog; + gpios = <2 0>; + input; /* FIXME add meaning */ + line-name = "sw4_3"; + }; + gtr_sel3 { + gpio-hog; + gpios = <3 0>; + input; /* FIXME add meaning */ + line-name = "sw4_4"; + }; + }; + }; + i2c@1 { /* UTIL_PMBUS - FIXME incorrect schematics */ + #address-cells = <1>; + #size-cells = <0>; + /* reg = <1>; */ + }; + i2c@2 { /* C0_LP4 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + si570_c0_lp4: clock-generator@5d { /* u10 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; /* FIXME addr */ + temperature-stability = <50>; + factory-fout = <30000000>; + clock-frequency = <30000000>; + clock-output-names = "C0_LP4_SI570_CLK"; + }; + }; + i2c@3 { /* C1_LP4 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + si570_c1_lp4: clock-generator@5d { /* u10 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; /* FIXME addr */ + temperature-stability = <50>; + factory-fout = <30000000>; + clock-frequency = <30000000>; + clock-output-names = "C1_LP4_SI570_CLK"; + }; + }; + i2c@4 { /* C2_LP4 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + si570_c2_lp4: clock-generator@5d { /* u10 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; /* FIXME addr */ + temperature-stability = <50>; + factory-fout = <30000000>; + clock-frequency = <30000000>; + clock-output-names = "C2_LP4_SI570_CLK"; + }; + }; + i2c@5 { /* C3_LP4 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + si570_c3_lp4: clock-generator@5d { /* u15 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; /* FIXME addr */ + temperature-stability = <50>; + factory-fout = <30000000>; + clock-frequency = <30000000>; + clock-output-names = "C3_LP4_SI570_CLK"; + }; + }; + i2c@6 { /* HSDP_SI570 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + si570_hsdp: clock-generator@5d { /* u19 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; /* FIXME addr */ + temperature-stability = <50>; + factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ + clock-frequency = <33333333>; + clock-output-names = "HSDP_SI570"; + }; + }; + }; +}; + +&usb0 { + status = "okay"; + xlnx,usb-polarity = <0>; + xlnx,usb-reset-mode = <0>; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + /* dr_mode = "peripheral"; */ + maximum-speed = "high-speed"; +}; + +&usb1 { + status = "disabled"; /* not at mem board */ + xlnx,usb-polarity = <0>; + xlnx,usb-reset-mode = <0>; +}; + +&dwc3_1 { + /delete-property/ phy-names ; + /delete-property/ phys ; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk ; + snps,dis_u3_susphy_quirk ; + status = "disabled"; +}; diff --git a/board/xilinx/zynqmp/zynqmp-a2197-m-revA b/board/xilinx/zynqmp/zynqmp-a2197-m-revA new file mode 120000 index 0000000000..a64c140b86 --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-a2197-m-revA @@ -0,0 +1 @@ +zynqmp-a2197-revA \ No newline at end of file diff --git a/configs/xilinx_zynqmp_a2197_m_revA_defconfig b/configs/xilinx_zynqmp_a2197_m_revA_defconfig new file mode 100644 index 0000000000..d9107d6bb8 --- /dev/null +++ b/configs/xilinx_zynqmp_a2197_m_revA_defconfig @@ -0,0 +1,116 @@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal" +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_ZYNQMP_USB=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y +CONFIG_SYS_PROMPT="ZynqMP> " +CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SDRAM=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-m-revA" +CONFIG_ENV_IS_IN_FAT=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_CLK_ZYNQMP=y +CONFIG_DFU_RAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_DM_GPIO=y +CONFIG_XILINX_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_MARVELL=y +CONFIG_PHY_NATSEMI=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_TI=y +CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y +CONFIG_PHY_GIGE=y +CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_ZYNQMP_GQSPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_ZYNQMP=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Xilinx" +CONFIG_USB_GADGET_VENDOR_NUM=0x03FD +CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 +CONFIG_USB_FUNCTION_THOR=y +CONFIG_SPL_GZIP=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_a2197_revA_defconfig b/configs/xilinx_zynqmp_a2197_revA_defconfig index 2859ef553e..ace0114232 100644 --- a/configs/xilinx_zynqmp_a2197_revA_defconfig +++ b/configs/xilinx_zynqmp_a2197_revA_defconfig @@ -44,7 +44,7 @@ CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-revA" -CONFIG_OF_LIST="zynqmp-a2197-revA zynqmp-a2197-g-revA zynqmp-a2197-p-revA" +CONFIG_OF_LIST="zynqmp-a2197-revA zynqmp-a2197-g-revA zynqmp-a2197-p-revA zynqmp-a2197-m-revA" CONFIG_ENV_IS_IN_FAT=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y From 336c730150481566a23527e6553c45a4c3360ed6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 25 Sep 2019 11:06:50 +0200 Subject: [PATCH 54/85] configs: apalis-tk1: Do not define CONFIG_SYS_BOOT_RAMDISK_HIGH again CONFIG_SYS_BOOT_RAMDISK_HIGH is already defined in arch/arm/include/asm/config.h:10:#define CONFIG_SYS_BOOT_RAMDISK_HIGH that's why there is no reason to define it again in board file. Signed-off-by: Michal Simek --- include/configs/apalis-tk1.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index dacf36bf79..fe45917b88 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -138,8 +138,6 @@ #define CONFIG_CMD_TIME -#define CONFIG_SYS_BOOT_RAMDISK_HIGH - #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" From a91feaee0fa8ab3835061b04ca895be1d1281589 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 25 Sep 2019 12:32:41 +0200 Subject: [PATCH 55/85] ARM: zynq: Define default SYS_PROMPT All boards are using the same prompt that's why add it as default value to Kconfig to simplify defconfigs. Signed-off-by: Michal Simek --- cmd/Kconfig | 1 + configs/syzygy_hub_defconfig | 1 - configs/zynq_cc108_defconfig | 1 - configs/zynq_cse_nand_defconfig | 1 - configs/zynq_cse_nor_defconfig | 1 - configs/zynq_cse_qspi_defconfig | 1 - configs/zynq_dlc20_rev1_0_defconfig | 1 - configs/zynq_microzed_defconfig | 1 - configs/zynq_minized_defconfig | 1 - configs/zynq_picozed_defconfig | 1 - configs/zynq_z_turn_defconfig | 1 - configs/zynq_zc702_defconfig | 1 - configs/zynq_zc706_defconfig | 1 - configs/zynq_zc770_xm010_defconfig | 1 - configs/zynq_zc770_xm011_defconfig | 1 - configs/zynq_zc770_xm011_x16_defconfig | 1 - configs/zynq_zc770_xm012_defconfig | 1 - configs/zynq_zc770_xm013_defconfig | 1 - configs/zynq_zed_defconfig | 1 - configs/zynq_zybo_defconfig | 1 - configs/zynq_zybo_z7_defconfig | 1 - 21 files changed, 1 insertion(+), 20 deletions(-) diff --git a/cmd/Kconfig b/cmd/Kconfig index 4e61565aab..78865eb8b6 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -48,6 +48,7 @@ config SYS_LONGHELP config SYS_PROMPT string "Shell prompt" + default "Zynq> " if ARCH_ZYNQ default "=> " help This string is displayed in the command line to the left of the diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig index 8b72983b23..6f89372ccf 100644 --- a/configs/syzygy_hub_defconfig +++ b/configs/syzygy_hub_defconfig @@ -19,7 +19,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y -CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y diff --git a/configs/zynq_cc108_defconfig b/configs/zynq_cc108_defconfig index 9bfe5ce996..495c5df608 100644 --- a/configs/zynq_cc108_defconfig +++ b/configs/zynq_cc108_defconfig @@ -18,7 +18,6 @@ CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 -CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig index 0910d3bf9d..8740997a82 100644 --- a/configs/zynq_cse_nand_defconfig +++ b/configs/zynq_cse_nand_defconfig @@ -17,7 +17,6 @@ CONFIG_SPL_STACK_R=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set -CONFIG_SYS_PROMPT="Zynq> " # CONFIG_AUTOBOOT is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig index 0a6b172b7e..a786fa2e23 100644 --- a/configs/zynq_cse_nor_defconfig +++ b/configs/zynq_cse_nor_defconfig @@ -17,7 +17,6 @@ CONFIG_SPL_STACK_R=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set -CONFIG_SYS_PROMPT="Zynq> " # CONFIG_AUTOBOOT is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index 4972d70805..0cc6976c76 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -26,7 +26,6 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set -CONFIG_SYS_PROMPT="Zynq> " # CONFIG_AUTOBOOT is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set diff --git a/configs/zynq_dlc20_rev1_0_defconfig b/configs/zynq_dlc20_rev1_0_defconfig index b6751ad35b..00d1a598dd 100644 --- a/configs/zynq_dlc20_rev1_0_defconfig +++ b/configs/zynq_dlc20_rev1_0_defconfig @@ -21,7 +21,6 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 -CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index d30581b241..751d3735ba 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -16,7 +16,6 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 -CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/zynq_minized_defconfig b/configs/zynq_minized_defconfig index 3c95f0aceb..d9657f9621 100644 --- a/configs/zynq_minized_defconfig +++ b/configs/zynq_minized_defconfig @@ -16,7 +16,6 @@ CONFIG_FIT_VERBOSE=y CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y -CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig index 6457876ce4..c72307a89d 100644 --- a/configs/zynq_picozed_defconfig +++ b/configs/zynq_picozed_defconfig @@ -10,7 +10,6 @@ CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y -CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/zynq_z_turn_defconfig b/configs/zynq_z_turn_defconfig index d133fea395..799277c58e 100644 --- a/configs/zynq_z_turn_defconfig +++ b/configs/zynq_z_turn_defconfig @@ -19,7 +19,6 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 -CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index 6b670aefc9..74e8b3e32e 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -20,7 +20,6 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 -CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index 3d0cd314c6..f831039158 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -23,7 +23,6 @@ CONFIG_SPL_FPGA_SUPPORT=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 -CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index 53108ff03c..301bc2dffd 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -20,7 +20,6 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 -CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig index feedb327bd..8bc49ea066 100644 --- a/configs/zynq_zc770_xm011_defconfig +++ b/configs/zynq_zc770_xm011_defconfig @@ -19,7 +19,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y -CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y diff --git a/configs/zynq_zc770_xm011_x16_defconfig b/configs/zynq_zc770_xm011_x16_defconfig index 28d63c9ec5..70429a2f25 100644 --- a/configs/zynq_zc770_xm011_x16_defconfig +++ b/configs/zynq_zc770_xm011_x16_defconfig @@ -19,7 +19,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y -CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig index 01e3d5fb84..78cdd9c9c7 100644 --- a/configs/zynq_zc770_xm012_defconfig +++ b/configs/zynq_zc770_xm012_defconfig @@ -16,7 +16,6 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y -CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_IMLS=y CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index 30bb0ef3f2..c6678784af 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -18,7 +18,6 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 -CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index 9b6d754872..38bf3e45e6 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -19,7 +19,6 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 -CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 2abc6db0d0..71d1638d45 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -19,7 +19,6 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 -CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/zynq_zybo_z7_defconfig b/configs/zynq_zybo_z7_defconfig index eda1416a9b..0cc525c637 100644 --- a/configs/zynq_zybo_z7_defconfig +++ b/configs/zynq_zybo_z7_defconfig @@ -19,7 +19,6 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 -CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set From 3c3886d75bd314ec3fe333abe16e99cd76829648 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 25 Sep 2019 12:37:15 +0200 Subject: [PATCH 56/85] arm64: zynqmp: Define default SYS_PROMPT All boards are using the same prompt that's why add it as default value to Kconfig to simplify defconfigs. Signed-off-by: Michal Simek Reviewed-by: Luca Ceresoli --- cmd/Kconfig | 1 + configs/avnet_ultra96_rev1_defconfig | 1 - configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig | 1 - configs/xilinx_zynqmp_a2197_g_revA_defconfig | 1 - configs/xilinx_zynqmp_a2197_m_revA_defconfig | 1 - configs/xilinx_zynqmp_a2197_p_revA_defconfig | 1 - configs/xilinx_zynqmp_a2197_revA_defconfig | 1 - configs/xilinx_zynqmp_mini_defconfig | 1 - configs/xilinx_zynqmp_mini_emmc0_defconfig | 1 - configs/xilinx_zynqmp_mini_emmc1_defconfig | 1 - configs/xilinx_zynqmp_mini_nand_defconfig | 1 - configs/xilinx_zynqmp_mini_qspi_defconfig | 1 - configs/xilinx_zynqmp_zc1232_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1254_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 1 - configs/xilinx_zynqmp_zcu100_revC_defconfig | 1 - configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 - configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 - configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu111_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu1275_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu1275_revB_defconfig | 1 - 29 files changed, 1 insertion(+), 28 deletions(-) diff --git a/cmd/Kconfig b/cmd/Kconfig index 78865eb8b6..80849ba7df 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -49,6 +49,7 @@ config SYS_LONGHELP config SYS_PROMPT string "Shell prompt" default "Zynq> " if ARCH_ZYNQ + default "ZynqMP> " if ARCH_ZYNQMP default "=> " help This string is displayed in the command line to the left of the diff --git a/configs/avnet_ultra96_rev1_defconfig b/configs/avnet_ultra96_rev1_defconfig index 9241530811..b5e61e621a 100644 --- a/configs/avnet_ultra96_rev1_defconfig +++ b/configs/avnet_ultra96_rev1_defconfig @@ -17,7 +17,6 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y -CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_BIND=y diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig index f463318565..b9bb0c9b11 100644 --- a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig +++ b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig @@ -16,7 +16,6 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_BOOTDELAY=0 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_OS_BOOT=y -CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_MEMTEST=y CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y diff --git a/configs/xilinx_zynqmp_a2197_g_revA_defconfig b/configs/xilinx_zynqmp_a2197_g_revA_defconfig index 2f6dc7641a..47a98c6d4d 100644 --- a/configs/xilinx_zynqmp_a2197_g_revA_defconfig +++ b/configs/xilinx_zynqmp_a2197_g_revA_defconfig @@ -21,7 +21,6 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y -CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y diff --git a/configs/xilinx_zynqmp_a2197_m_revA_defconfig b/configs/xilinx_zynqmp_a2197_m_revA_defconfig index d9107d6bb8..fb4020b2df 100644 --- a/configs/xilinx_zynqmp_a2197_m_revA_defconfig +++ b/configs/xilinx_zynqmp_a2197_m_revA_defconfig @@ -21,7 +21,6 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y -CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y diff --git a/configs/xilinx_zynqmp_a2197_p_revA_defconfig b/configs/xilinx_zynqmp_a2197_p_revA_defconfig index 4ce634cdaa..d19c6b34ca 100644 --- a/configs/xilinx_zynqmp_a2197_p_revA_defconfig +++ b/configs/xilinx_zynqmp_a2197_p_revA_defconfig @@ -22,7 +22,6 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y -CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y diff --git a/configs/xilinx_zynqmp_a2197_revA_defconfig b/configs/xilinx_zynqmp_a2197_revA_defconfig index ace0114232..3498483f4b 100644 --- a/configs/xilinx_zynqmp_a2197_revA_defconfig +++ b/configs/xilinx_zynqmp_a2197_revA_defconfig @@ -21,7 +21,6 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y -CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig index 93fa7d8f6b..4b7fe5dd40 100644 --- a/configs/xilinx_zynqmp_mini_defconfig +++ b/configs/xilinx_zynqmp_mini_defconfig @@ -13,7 +13,6 @@ CONFIG_ZYNQMP_PSU_INIT_ENABLED=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set -CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_AUTOBOOT is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig index b4162abdd7..282e93f03c 100644 --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig @@ -14,7 +14,6 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_AUTOBOOT is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig index 76d5aa6c71..be70988698 100644 --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig @@ -14,7 +14,6 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_AUTOBOOT is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig index 2b896f79a7..35776ab208 100644 --- a/configs/xilinx_zynqmp_mini_nand_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_defconfig @@ -14,7 +14,6 @@ CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set -CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_AUTOBOOT is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index a20534a488..383f868625 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -17,7 +17,6 @@ CONFIG_ZYNQMP_NO_DDR=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set -CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_AUTOBOOT is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set diff --git a/configs/xilinx_zynqmp_zc1232_revA_defconfig b/configs/xilinx_zynqmp_zc1232_revA_defconfig index 80a310fb1c..255217df4b 100644 --- a/configs/xilinx_zynqmp_zc1232_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1232_revA_defconfig @@ -17,7 +17,6 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y -CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y # CONFIG_CMD_FLASH is not set diff --git a/configs/xilinx_zynqmp_zc1254_revA_defconfig b/configs/xilinx_zynqmp_zc1254_revA_defconfig index 75ec572827..e058195842 100644 --- a/configs/xilinx_zynqmp_zc1254_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1254_revA_defconfig @@ -17,7 +17,6 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y -CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y # CONFIG_CMD_FLASH is not set diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index ce1ea089ce..bbf387a6b0 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -19,7 +19,6 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y -CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index 01c29c0e70..d5434eee85 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -19,7 +19,6 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y -CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y diff --git a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig index 877f5b230d..4ff52292fb 100644 --- a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig @@ -17,7 +17,6 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y -CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig index 6f14234a59..a5a7fc2aeb 100644 --- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig @@ -16,7 +16,6 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y -CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_CLK=y diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig index f1970aadf4..5b8cf77085 100644 --- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig @@ -16,7 +16,6 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y -CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_CLK=y diff --git a/configs/xilinx_zynqmp_zcu100_revC_defconfig b/configs/xilinx_zynqmp_zcu100_revC_defconfig index cd7d2f5376..fc917f0b5d 100644 --- a/configs/xilinx_zynqmp_zcu100_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu100_revC_defconfig @@ -17,7 +17,6 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y -CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_BIND=y diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig index 52ee2f2a0b..b64956d5f6 100644 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig @@ -20,7 +20,6 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y -CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig index 2b7cab8add..8b1a1ce0a2 100644 --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@ -20,7 +20,6 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y -CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index ce271b5a31..2aab26dd3f 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -20,7 +20,6 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y -CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y diff --git a/configs/xilinx_zynqmp_zcu104_revA_defconfig b/configs/xilinx_zynqmp_zcu104_revA_defconfig index eacf75d9f8..07e58b192a 100644 --- a/configs/xilinx_zynqmp_zcu104_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revA_defconfig @@ -17,7 +17,6 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y -CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y diff --git a/configs/xilinx_zynqmp_zcu104_revC_defconfig b/configs/xilinx_zynqmp_zcu104_revC_defconfig index 2f269009df..4829df62b4 100644 --- a/configs/xilinx_zynqmp_zcu104_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revC_defconfig @@ -20,7 +20,6 @@ CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_ATF=y -CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y diff --git a/configs/xilinx_zynqmp_zcu106_revA_defconfig b/configs/xilinx_zynqmp_zcu106_revA_defconfig index 1b685ca049..72b3ce16a8 100644 --- a/configs/xilinx_zynqmp_zcu106_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu106_revA_defconfig @@ -19,7 +19,6 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y -CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y diff --git a/configs/xilinx_zynqmp_zcu111_revA_defconfig b/configs/xilinx_zynqmp_zcu111_revA_defconfig index 74106d7ea8..de739ed3b5 100644 --- a/configs/xilinx_zynqmp_zcu111_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu111_revA_defconfig @@ -17,7 +17,6 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y -CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y diff --git a/configs/xilinx_zynqmp_zcu1275_revA_defconfig b/configs/xilinx_zynqmp_zcu1275_revA_defconfig index b9110ca3b9..d86c5d1a76 100644 --- a/configs/xilinx_zynqmp_zcu1275_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu1275_revA_defconfig @@ -17,7 +17,6 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y -CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y # CONFIG_CMD_FLASH is not set diff --git a/configs/xilinx_zynqmp_zcu1275_revB_defconfig b/configs/xilinx_zynqmp_zcu1275_revB_defconfig index 03372c77e6..957b883abd 100644 --- a/configs/xilinx_zynqmp_zcu1275_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu1275_revB_defconfig @@ -17,7 +17,6 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y -CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y # CONFIG_CMD_FLASH is not set From da2a4909bd1a5540a2e33d12bf1a53cdbd030747 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 25 Sep 2019 08:13:15 +0200 Subject: [PATCH 57/85] microblaze: Remove unused variable ram_base This variable is completely unused that's why remove it. Signed-off-by: Michal Simek --- board/xilinx/microblaze-generic/microblaze-generic.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index ba82292e35..4e038ddf0c 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -24,8 +24,6 @@ DECLARE_GLOBAL_DATA_PTR; -ulong ram_base; - int dram_init_banksize(void) { return fdtdec_setup_memory_banksize(); From 9d877c2f5404be82d90e8bc624a20a35d21e429d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 25 Sep 2019 08:32:27 +0200 Subject: [PATCH 58/85] microblaze: Move CONFIG_LMB from board file to config.h It is common for the whole architecture that's why move it there. Signed-off-by: Michal Simek --- arch/microblaze/include/asm/config.h | 2 ++ include/configs/microblaze-generic.h | 3 --- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/microblaze/include/asm/config.h b/arch/microblaze/include/asm/config.h index 45966eef91..d522669f66 100644 --- a/arch/microblaze/include/asm/config.h +++ b/arch/microblaze/include/asm/config.h @@ -6,6 +6,8 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +#define CONFIG_LMB + #ifndef CONFIG_SPL_BUILD #define CONFIG_NEEDS_MANUAL_RELOC #endif diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 814fec5b33..f66f63e074 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -152,9 +152,6 @@ "setenv stdin serial\0" #endif -/* Enable flat device tree support */ -#define CONFIG_LMB 1 - #if defined(CONFIG_XILINX_AXIEMAC) # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 #endif From a750ded4667496b367bc1275246752a3092b2ca2 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 25 Sep 2019 09:11:48 +0200 Subject: [PATCH 59/85] microblaze: Fix lmb memory initialization Microblaze as Arm is using multiple memory banks which are read from DT that's why there is a need to initialized LMB based on bd->bi_dram[]. Without this fix memory base/size is all the time 0 and image relocation is not possible. Signed-off-by: Michal Simek --- common/image.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/common/image.c b/common/image.c index 179eef0bd2..fc0ebe338b 100644 --- a/common/image.c +++ b/common/image.c @@ -582,7 +582,7 @@ ulong env_get_bootm_low(void) #if defined(CONFIG_SYS_SDRAM_BASE) return CONFIG_SYS_SDRAM_BASE; -#elif defined(CONFIG_ARM) +#elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE) return gd->bd->bi_dram[0].start; #else return 0; @@ -599,7 +599,8 @@ phys_size_t env_get_bootm_size(void) return tmp; } -#if defined(CONFIG_ARM) && defined(CONFIG_NR_DRAM_BANKS) +#if (defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE)) && \ + defined(CONFIG_NR_DRAM_BANKS) start = gd->bd->bi_dram[0].start; size = gd->bd->bi_dram[0].size; #else From 6131a36be6f046c1db044fdf449436fbe3fa8d21 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 25 Sep 2019 10:45:51 +0200 Subject: [PATCH 60/85] microblaze: Define arch_lmb_reserve arch_lmb_reserve() protects U-Boot relocated code with stack not to be used for image relocation. Signed-off-by: Michal Simek --- arch/microblaze/lib/bootm.c | 41 +++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index ec332944d8..a74f1d1e55 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -15,6 +15,47 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + +static ulong get_sp(void) +{ + ulong ret; + + asm("addik %0, r1, 0" : "=r"(ret) : ); + return ret; +} + +void arch_lmb_reserve(struct lmb *lmb) +{ + ulong sp, bank_end; + int bank; + + /* + * Booting a (Linux) kernel image + * + * Allocate space for command line and board info - the + * address should be as high as possible within the reach of + * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused + * memory, which means far enough below the current stack + * pointer. + */ + sp = get_sp(); + debug("## Current stack ends at 0x%08lx ", sp); + + /* adjust sp by 4K to be safe */ + sp -= 4096; + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + if (sp < gd->bd->bi_dram[bank].start) + continue; + bank_end = gd->bd->bi_dram[bank].start + + gd->bd->bi_dram[bank].size; + if (sp >= bank_end) + continue; + lmb_reserve(lmb, sp, bank_end - sp); + break; + } +} + int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images) { From 0905046050b041784869762824f6266c593fec67 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 25 Sep 2019 09:47:02 +0200 Subject: [PATCH 61/85] microblaze: Switch to generic bootm implementation There is no reason to use private code for standard bootm command. Current implementation is also broken and don't support image relocation properly. Switching to generic bootm implementation is fixing these issues. cmdline and bdt bootm subcommands are returning -1 because they are not implemented. Similar change was done long time ago by for example commit 2bb5b638791d ("MIPS: bootm: rework and fix broken bootm code") Signed-off-by: Michal Simek --- arch/microblaze/include/asm/config.h | 2 + arch/microblaze/lib/bootm.c | 105 +++++++++++++-------------- 2 files changed, 54 insertions(+), 53 deletions(-) diff --git a/arch/microblaze/include/asm/config.h b/arch/microblaze/include/asm/config.h index d522669f66..1124272915 100644 --- a/arch/microblaze/include/asm/config.h +++ b/arch/microblaze/include/asm/config.h @@ -12,4 +12,6 @@ #define CONFIG_NEEDS_MANUAL_RELOC #endif +#define CONFIG_SYS_BOOT_RAMDISK_HIGH + #endif diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index a74f1d1e55..11e534715d 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -56,71 +56,70 @@ void arch_lmb_reserve(struct lmb *lmb) } } -int do_bootm_linux(int flag, int argc, char * const argv[], - bootm_headers_t *images) +static void boot_jump_linux(bootm_headers_t *images, int flag) { - /* First parameter is mapped to $r5 for kernel boot args */ - void (*thekernel) (char *, ulong, ulong); - char *commandline = env_get("bootargs"); - ulong rd_data_start, rd_data_end; - - /* - * allow the PREP bootm subcommand, it is required for bootm to work - */ - if (flag & BOOTM_STATE_OS_PREP) - return 0; - - if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) - return 1; - - int ret; - - char *of_flat_tree = NULL; -#if defined(CONFIG_OF_LIBFDT) - /* did generic code already find a device tree? */ - if (images->ft_len) - of_flat_tree = images->ft_addr; -#endif + void (*thekernel)(char *cmdline, ulong rd, ulong dt); + ulong dt = (ulong)images->ft_addr; + ulong rd_start = images->initrd_start; + ulong cmdline = images->cmdline_start; + int fake = (flag & BOOTM_STATE_OS_FAKE_GO); thekernel = (void (*)(char *, ulong, ulong))images->ep; - /* find ramdisk */ - ret = boot_get_ramdisk(argc, argv, images, IH_ARCH_MICROBLAZE, - &rd_data_start, &rd_data_end); - if (ret) - return 1; - - bootstage_mark(BOOTSTAGE_ID_RUN_OS); - - if (!of_flat_tree && argc > 1) - of_flat_tree = (char *)simple_strtoul(argv[1], NULL, 16); - - /* fixup the initrd now that we know where it should be */ - if (images->rd_start && images->rd_end && of_flat_tree) { - ret = fdt_initrd(of_flat_tree, images->rd_start, - images->rd_end); - if (ret) - return 1; - } - #ifdef DEBUG printf("## Transferring control to Linux (at address 0x%08lx) ", (ulong)thekernel); - printf("ramdisk 0x%08lx, FDT 0x%08lx...\n", - rd_data_start, (ulong) of_flat_tree); + printf("cmdline 0x%08lx, ramdisk 0x%08lx, FDT 0x%08lx...\n", + cmdline, rd_start, dt); #endif #ifdef XILINX_USE_DCACHE flush_cache(0, XILINX_DCACHE_BYTE_SIZE); #endif - /* - * Linux Kernel Parameters (passing device tree): - * r5: pointer to command line - * r6: pointer to ramdisk - * r7: pointer to the fdt, followed by the board info data - */ - thekernel(commandline, rd_data_start, (ulong)of_flat_tree); - /* does not return */ + if (!fake) { + /* + * Linux Kernel Parameters (passing device tree): + * r5: pointer to command line + * r6: pointer to ramdisk + * r7: pointer to the fdt, followed by the board info data + */ + thekernel((char *)cmdline, rd_start, dt); + /* does not return */ + } +} + +static void boot_prep_linux(bootm_headers_t *images) +{ + if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { + printf("using: FDT\n"); + if (image_setup_linux(images)) { + printf("FDT creation failed! hanging..."); + hang(); + } + } +} + +int do_bootm_linux(int flag, int argc, char * const argv[], + bootm_headers_t *images) +{ + images->cmdline_start = (ulong)env_get("bootargs"); + + /* cmdline init is the part of 'prep' and nothing to do for 'bdt' */ + if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE) + return -1; + + if (flag & BOOTM_STATE_OS_PREP) { + boot_prep_linux(images); + return 0; + } + + if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) { + boot_jump_linux(images, flag); + return 0; + } + + boot_prep_linux(images); + boot_jump_linux(images, flag); return 1; } From c5ba6357b322581f2b408e039c459379e4aae5e3 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 25 Sep 2019 11:12:37 +0200 Subject: [PATCH 62/85] microblaze: Enable cache by default The whole cache code needs to be redesign to read information about cache from DT instead of macro selection. Enable caches by default because systems have caches on by default for Linux. Also enable CMD_CACHE to be able to disable cache if there is any issue. Signed-off-by: Michal Simek --- configs/microblaze-generic_defconfig | 1 + include/configs/microblaze-generic.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 94b9c78a6c..1857562cd7 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -37,6 +37,7 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y CONFIG_CMD_JFFS2=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index f66f63e074..ce18ee73c2 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -100,6 +100,9 @@ #endif /* !SPIFLASH */ #endif /* !FLASH */ +#define XILINX_USE_ICACHE 1 +#define XILINX_USE_DCACHE 1 + #if defined(XILINX_USE_ICACHE) # define CONFIG_ICACHE #else From 8272f31036c3128e0787183e214389744bea61ee Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 25 Sep 2019 11:12:40 +0200 Subject: [PATCH 63/85] microblaze: Setup reasonable maximum bootm len We are far from 8MB default size. Setup 64MB for now. Signed-off-by: Michal Simek --- include/configs/microblaze-generic.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index ce18ee73c2..f1d0def3c1 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -13,6 +13,8 @@ /* MicroBlaze CPU */ #define MICROBLAZE_V5 1 +#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) + /* linear and spi flash memory */ #ifdef XILINX_FLASH_START #define FLASH From e0418347f9aa0f5099dfc1dac8eafceb98e38ccf Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 25 Sep 2019 11:00:17 +0200 Subject: [PATCH 64/85] microblaze: Setup initrd_high and fdt_high at run time Setup initrd_high and fdt_high to be placed in lowmem space for kernel to be able to reach it. Values are setup at run time to ensure that the same setting can be used on different memory setup. Do this setting only when variables are not Similar run time detection was done for Zynqmp and Versal. Signed-off-by: Michal Simek --- arch/microblaze/Kconfig | 8 ++++++++ .../microblaze-generic/microblaze-generic.c | 19 +++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 5cc68d63c4..5ce8261451 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -20,6 +20,14 @@ config TARGET_MICROBLAZE_GENERIC endchoice +config STACK_SIZE + hex "Define max stack size that can be used by u-boot" + default 0x200000 + help + Defines Max stack size that can be used by u-boot so that the + initrd_high will be calculated as base stack pointer minus this + stack size. + source "board/xilinx/microblaze-generic/Kconfig" config SPL_LDSCRIPT diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index 4e038ddf0c..30be0150f3 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -21,6 +21,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -39,6 +40,8 @@ int dram_init(void) int board_late_init(void) { + ulong max_size, lowmem_size; + #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SYSRESET_MICROBLAZE) int ret; @@ -47,5 +50,21 @@ int board_late_init(void) if (ret) printf("Warning: No reset driver: ret=%d\n", ret); #endif + + if (!(gd->flags & GD_FLG_ENV_DEFAULT)) { + debug("Saved variables - Skipping\n"); + return 0; + } + + max_size = gd->start_addr_sp - CONFIG_STACK_SIZE; + max_size = round_down(max_size, SZ_16M); + + /* Linux default LOWMEM_SIZE is 0x30000000 = 768MB */ + lowmem_size = gd->ram_base + 768 * 1024 * 1024; + + env_set_addr("initrd_high", (void *)min_t(ulong, max_size, + lowmem_size)); + env_set_addr("fdt_high", (void *)min_t(ulong, max_size, lowmem_size)); + return 0; } From c0c33d9b9b8f73c4f07d33242b80233eac146cd8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 25 Sep 2019 13:14:36 +0200 Subject: [PATCH 65/85] microblaze: Remove additional headers There were several changes in past in this file without removing headers (watchdog cleanup, soft reset, etc). That's why remove additional useless headers. Signed-off-by: Michal Simek --- board/xilinx/microblaze-generic/microblaze-generic.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index 30be0150f3..7e784d1078 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -12,15 +12,8 @@ #include #include -#include #include #include -#include -#include -#include -#include -#include -#include #include DECLARE_GLOBAL_DATA_PTR; From f9e40add62b6db216e0e4a6d79d5a9217cebb454 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 25 Sep 2019 13:17:50 +0200 Subject: [PATCH 66/85] microblaze: Enable random mac generation In case that mac address is not found it is generated randomly. Signed-off-by: Michal Simek --- configs/microblaze-generic_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 1857562cd7..7d2859c5c3 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -42,6 +42,7 @@ CONFIG_CMD_JFFS2=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic" +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETCONSOLE=y CONFIG_SPL_DM=y CONFIG_XILINX_GPIO=y From ff1b0da4edfe58c08055816f34337e375dfff486 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 4 Oct 2019 13:58:47 +0200 Subject: [PATCH 67/85] arm64: versal: Enable clock driver Enable clock driver for Versal. Signed-off-by: Michal Simek --- configs/xilinx_versal_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 75f8b98308..f924d3e542 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -45,6 +45,7 @@ CONFIG_OF_BOARD=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_CLK_VERSAL=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y From 22673b4d53fc5ad82f632d6cdaae2950190ef214 Mon Sep 17 00:00:00 2001 From: Ibai Erkiaga Date: Fri, 27 Sep 2019 11:36:54 +0100 Subject: [PATCH 68/85] mailbox: check ops prior calling Check if request and free operations are present prior calling to the functions. Signed-off-by: Ibai Erkiaga Signed-off-by: Michal Simek --- drivers/mailbox/mailbox-uclass.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/mailbox/mailbox-uclass.c b/drivers/mailbox/mailbox-uclass.c index 1b4a5863c9..809f26b202 100644 --- a/drivers/mailbox/mailbox-uclass.c +++ b/drivers/mailbox/mailbox-uclass.c @@ -63,7 +63,8 @@ int mbox_get_by_index(struct udevice *dev, int index, struct mbox_chan *chan) return ret; } - ret = ops->request(chan); + if (ops->request) + ret = ops->request(chan); if (ret) { debug("ops->request() failed: %d\n", ret); return ret; @@ -94,7 +95,10 @@ int mbox_free(struct mbox_chan *chan) debug("%s(chan=%p)\n", __func__, chan); - return ops->free(chan); + if (ops->free) + return ops->free(chan); + + return 0; } int mbox_send(struct mbox_chan *chan, const void *data) From 05f683a3e2dea5e0700fd1e7b540ae024135545a Mon Sep 17 00:00:00 2001 From: Ibai Erkiaga Date: Fri, 27 Sep 2019 11:36:55 +0100 Subject: [PATCH 69/85] mailbox: allow subnode for mbox regs The following patch allows the mailbox node in DT to host subnodes with mailbox definitions. If the client phandle to the mailbox is not the mailbox driver node, just checks parents as well. Signed-off-by: Ibai Erkiaga Signed-off-by: Michal Simek --- drivers/mailbox/mailbox-uclass.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/mailbox/mailbox-uclass.c b/drivers/mailbox/mailbox-uclass.c index 809f26b202..9fdb6279e4 100644 --- a/drivers/mailbox/mailbox-uclass.c +++ b/drivers/mailbox/mailbox-uclass.c @@ -49,7 +49,16 @@ int mbox_get_by_index(struct udevice *dev, int index, struct mbox_chan *chan) if (ret) { debug("%s: uclass_get_device_by_of_offset failed: %d\n", __func__, ret); - return ret; + + /* Test with parent node */ + ret = uclass_get_device_by_ofnode(UCLASS_MAILBOX, + ofnode_get_parent(args.node), + &dev_mbox); + if (ret) { + debug("%s: mbox node from parent failed: %d\n", + __func__, ret); + return ret; + }; } ops = mbox_dev_ops(dev_mbox); From 660b0c77d81603c7911a3e5c024d646a801cd0ac Mon Sep 17 00:00:00 2001 From: Ibai Erkiaga Date: Fri, 27 Sep 2019 11:36:56 +0100 Subject: [PATCH 70/85] mailbox: zynqmp: ipi mailbox driver ZynqMP mailbox driver implementing IPI communication with PMU. This would allow U-Boot SPL to communicate with PMUFW to request privileged operations. Signed-off-by: Ibai Erkiaga Signed-off-by: Michal Simek --- MAINTAINERS | 1 + arch/arm/mach-zynqmp/include/mach/sys_proto.h | 5 + drivers/mailbox/Kconfig | 6 + drivers/mailbox/Makefile | 1 + drivers/mailbox/zynqmp-ipi.c | 134 ++++++++++++++++++ 5 files changed, 147 insertions(+) create mode 100644 drivers/mailbox/zynqmp-ipi.c diff --git a/MAINTAINERS b/MAINTAINERS index 59c766f206..6af9816a4a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -449,6 +449,7 @@ F: drivers/gpio/zynq_gpio.c F: drivers/i2c/i2c-cdns.c F: drivers/i2c/muxes/pca954x.c F: drivers/i2c/zynq_i2c.c +F: drivers/mailbox/zynqmp-ipi.c F: drivers/mmc/zynq_sdhci.c F: drivers/mtd/nand/raw/zynq_nand.c F: drivers/net/phy/xilinx_phy.c diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index 915badc6fb..f25d414dcb 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -54,6 +54,11 @@ enum { TCM_SPLIT, }; +struct zynqmp_ipi_msg { + size_t len; + u32 *buf; +}; + int zynq_board_read_rom_ethaddr(unsigned char *ethaddr); unsigned int zynqmp_get_silicon_version(void); diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 11bf5522db..85c2a829ae 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -41,4 +41,10 @@ config K3_SEC_PROXY Select this driver if your platform has support for this hardware block. +config ZYNQMP_IPI + bool "Xilinx ZynqMP IPI controller support" + depends on DM_MAILBOX && ARCH_ZYNQMP + help + This enables support for the Xilinx ZynqMP Inter Processor Interrupt + communication controller. endmenu diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index a753cc4e68..d2ace8cd21 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o obj-$(CONFIG_TEGRA_HSP) += tegra-hsp.o obj-$(CONFIG_K3_SEC_PROXY) += k3-sec-proxy.o +obj-$(CONFIG_ZYNQMP_IPI) += zynqmp-ipi.o diff --git a/drivers/mailbox/zynqmp-ipi.c b/drivers/mailbox/zynqmp-ipi.c new file mode 100644 index 0000000000..c181a7b817 --- /dev/null +++ b/drivers/mailbox/zynqmp-ipi.c @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx Zynq MPSoC Mailbox driver + * + * Copyright (C) 2018-2019 Xilinx, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* IPI bitmasks, register base */ +/* TODO: move reg base to DT */ +#define IPI_BIT_MASK_PMU0 0x10000 +#define IPI_INT_REG_BASE_APU 0xFF300000 + +struct ipi_int_regs { + u32 trig; /* 0x0 */ + u32 obs; /* 0x4 */ + u32 ist; /* 0x8 */ + u32 imr; /* 0xC */ + u32 ier; /* 0x10 */ + u32 idr; /* 0x14 */ +}; + +#define ipi_int_apu ((struct ipi_int_regs *)IPI_INT_REG_BASE_APU) + +struct zynqmp_ipi { + void __iomem *local_req_regs; + void __iomem *local_res_regs; + void __iomem *remote_req_regs; + void __iomem *remote_res_regs; +}; + +static int zynqmp_ipi_send(struct mbox_chan *chan, const void *data) +{ + const struct zynqmp_ipi_msg *msg = (struct zynqmp_ipi_msg *)data; + struct zynqmp_ipi *zynqmp = dev_get_priv(chan->dev); + u32 ret; + u32 *mbx = (u32 *)zynqmp->local_req_regs; + + for (size_t i = 0; i < msg->len; i++) + writel(msg->buf[i], &mbx[i]); + + /* Write trigger interrupt */ + writel(IPI_BIT_MASK_PMU0, &ipi_int_apu->trig); + + /* Wait until observation bit is cleared */ + ret = wait_for_bit_le32(&ipi_int_apu->obs, IPI_BIT_MASK_PMU0, false, + 100, false); + + debug("%s, send %ld bytes\n", __func__, msg->len); + return ret; +}; + +static int zynqmp_ipi_recv(struct mbox_chan *chan, void *data) +{ + struct zynqmp_ipi_msg *msg = (struct zynqmp_ipi_msg *)data; + struct zynqmp_ipi *zynqmp = dev_get_priv(chan->dev); + u32 *mbx = (u32 *)zynqmp->local_res_regs; + + for (size_t i = 0; i < msg->len; i++) + msg->buf[i] = readl(&mbx[i]); + + debug("%s, recv %ld bytes\n", __func__, msg->len); + return 0; +}; + +static int zynqmp_ipi_probe(struct udevice *dev) +{ + struct zynqmp_ipi *zynqmp = dev_get_priv(dev); + struct resource res; + ofnode node; + + debug("%s(dev=%p)\n", __func__, dev); + + /* Get subnode where the regs are defined */ + /* Note IPI mailbox node needs to be the first one in DT */ + node = ofnode_first_subnode(dev_ofnode(dev)); + + if (ofnode_read_resource_byname(node, "local_request_region", &res)) { + dev_err(dev, "No reg property for local_request_region\n"); + return -EINVAL; + }; + zynqmp->local_req_regs = devm_ioremap(dev, res.start, + (res.start - res.end)); + + if (ofnode_read_resource_byname(node, "local_response_region", &res)) { + dev_err(dev, "No reg property for local_response_region\n"); + return -EINVAL; + }; + zynqmp->local_res_regs = devm_ioremap(dev, res.start, + (res.start - res.end)); + + if (ofnode_read_resource_byname(node, "remote_request_region", &res)) { + dev_err(dev, "No reg property for remote_request_region\n"); + return -EINVAL; + }; + zynqmp->remote_req_regs = devm_ioremap(dev, res.start, + (res.start - res.end)); + + if (ofnode_read_resource_byname(node, "remote_response_region", &res)) { + dev_err(dev, "No reg property for remote_response_region\n"); + return -EINVAL; + }; + zynqmp->remote_res_regs = devm_ioremap(dev, res.start, + (res.start - res.end)); + + return 0; +}; + +static const struct udevice_id zynqmp_ipi_ids[] = { + { .compatible = "xlnx,zynqmp-ipi-mailbox" }, + { } +}; + +struct mbox_ops zynqmp_ipi_mbox_ops = { + .send = zynqmp_ipi_send, + .recv = zynqmp_ipi_recv, +}; + +U_BOOT_DRIVER(zynqmp_ipi) = { + .name = "zynqmp-ipi", + .id = UCLASS_MAILBOX, + .of_match = zynqmp_ipi_ids, + .probe = zynqmp_ipi_probe, + .priv_auto_alloc_size = sizeof(struct zynqmp_ipi), + .ops = &zynqmp_ipi_mbox_ops, +}; From 1327d1678bd2d1897fb321465e24a05466c80f16 Mon Sep 17 00:00:00 2001 From: Ibai Erkiaga Date: Fri, 27 Sep 2019 12:51:41 +0200 Subject: [PATCH 71/85] firmware: zynqmp: Add zynqmp-power support zynqmp-power driver for ZynqMP to handle the communication with the PMU firmware. Firmware driver just probes subnodes and power driver handles communication with PMU using the IPI mailbox driver. Signed-off-by: Ibai Erkiaga Signed-off-by: Michal Simek --- arch/arm/Kconfig | 2 ++ drivers/firmware/firmware-zynqmp.c | 47 ++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 257a98d795..0c41bc3e5b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1051,6 +1051,7 @@ config ARCH_ZYNQMP select CLK select DM select DM_ETH if NET + select DM_MAILBOX select DM_MMC if MMC select DM_SERIAL select DM_SPI if SPI @@ -1061,6 +1062,7 @@ config ARCH_ZYNQMP select SPL_CLK if SPL select SPL_SEPARATE_BSS if SPL select SUPPORT_SPL + select ZYNQMP_IPI imply BOARD_LATE_INIT imply CMD_DM imply FAT_WRITE diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 4077126581..5ed2b32c11 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -1,7 +1,54 @@ // SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Zynq MPSoC Firmware driver + * + * Copyright (C) 2018-2019 Xilinx, Inc. + */ +#include #include +#if defined(CONFIG_ZYNQMP_IPI) +#include +#include + +struct zynqmp_power { + struct mbox_chan tx_chan; + struct mbox_chan rx_chan; +} zynqmp_power; + +static int zynqmp_power_probe(struct udevice *dev) +{ + int ret = 0; + + debug("%s, (dev=%p)\n", __func__, dev); + + ret = mbox_get_by_name(dev, "tx", &zynqmp_power.tx_chan); + if (ret) { + debug("%s, cannot tx mailbox\n", __func__); + return ret; + } + + ret = mbox_get_by_name(dev, "rx", &zynqmp_power.rx_chan); + if (ret) + debug("%s, cannot rx mailbox\n", __func__); + + return ret; +}; + +static const struct udevice_id zynqmp_power_ids[] = { + { .compatible = "xlnx,zynqmp-power" }, + { } +}; + +U_BOOT_DRIVER(zynqmp_power) = { + .name = "zynqmp_power", + .id = UCLASS_FIRMWARE, + .of_match = zynqmp_power_ids, + .probe = zynqmp_power_probe, +}; +#endif + static const struct udevice_id zynqmp_firmware_ids[] = { { .compatible = "xlnx,zynqmp-firmware" }, { .compatible = "xlnx,versal-firmware"}, From 95497afada586f7370f44092ba62d55d4647fe03 Mon Sep 17 00:00:00 2001 From: Ibai Erkiaga Date: Fri, 27 Sep 2019 11:36:58 +0100 Subject: [PATCH 72/85] arm64: zynqmp: add firmware and mailbox node to DT The following patch adds a mailbox node and firmware node to following the mainline DT. Signed-off-by: Ibai Erkiaga Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp.dtsi | 44 +++++++++++++++++++++++++++++++++++----- 1 file changed, 39 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index dfb6ebc64c..8e35171dd0 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -96,6 +96,29 @@ }; }; + zynqmp_ipi { + u-boot,dm-pre-reloc; + compatible = "xlnx,zynqmp-ipi-mailbox"; + interrupt-parent = <&gic>; + interrupts = <0 35 4>; + xlnx,ipi-id = <0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipi_mailbox_pmu1: mailbox@ff990400 { + u-boot,dm-pre-reloc; + reg = <0x0 0xff9905c0 0x0 0x20>, + <0x0 0xff9905e0 0x0 0x20>, + <0x0 0xff990e80 0x0 0x20>, + <0x0 0xff990ea0 0x0 0x20>; + reg-names = "local_request_region" , "local_response_region", + "remote_request_region", "remote_response_region"; + #mbox-cells = <1>; + xlnx,ipi-id = <4>; + }; + }; + dcc: dcc { compatible = "arm,dcc"; status = "disabled"; @@ -116,11 +139,22 @@ method = "smc"; }; - pmufw: firmware { - compatible = "xlnx,zynqmp-pm"; - method = "smc"; - interrupt-parent = <&gic>; - interrupts = <0 35 4>; + firmware { + zynqmp-firmware { + compatible = "xlnx,zynqmp-firmware"; + method = "smc"; + #power-domain-cells = <0x1>; + u-boot,dm-pre-reloc; + + zynqmp_power: zynqmp-power { + u-boot,dm-pre-reloc; + compatible = "xlnx,zynqmp-power"; + interrupt-parent = <&gic>; + interrupts = <0 35 4>; + mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; + mbox-names = "tx", "rx"; + }; + }; }; timer { From 17eb88e4e59111199279c5f53bbdb2b34fcedadd Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 27 Sep 2019 11:36:59 +0100 Subject: [PATCH 73/85] arm64: zynqmp: Cleanup PM SMC macro composition Cleanup PM ID handling by using enum values. Signed-off-by: Michal Simek Signed-off-by: Ibai Erkiaga Signed-off-by: Michal Simek --- arch/arm/mach-zynqmp/include/mach/sys_proto.h | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index f25d414dcb..573c4ffcee 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -10,7 +10,8 @@ #define PAYLOAD_ARG_CNT 5 #define ZYNQMP_CSU_SILICON_VER_MASK 0xF -#define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD 0xC200002D +#define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD \ + (PM_SIP_SVC + PM_SECURE_IMAGE) #define KEY_PTR_LEN 32 #define ZYNQMP_FPGA_BIT_AUTH_DDR 1 @@ -21,7 +22,8 @@ #define ZYNQMP_FPGA_AUTH_DDR 1 -#define ZYNQMP_SIP_SVC_GET_API_VERSION 0xC2000001 +#define ZYNQMP_SIP_SVC_GET_API_VERSION \ + (PM_SIP_SVC + PM_GET_API_VERSION) #define ZYNQMP_PM_VERSION_MAJOR 1 #define ZYNQMP_PM_VERSION_MINOR 0 @@ -36,6 +38,13 @@ #define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0) +#define PM_SIP_SVC 0xc2000000 + +enum pm_api_id { + PM_GET_API_VERSION = 1, + PM_SECURE_IMAGE = 45, +}; + enum { IDCODE, VERSION, From 490f6273168287139bd7a1c703d1c7eef65e5a05 Mon Sep 17 00:00:00 2001 From: Ibai Erkiaga Date: Fri, 27 Sep 2019 11:37:00 +0100 Subject: [PATCH 74/85] firmware: zynqmp: get fw version with mailbox driver Implements the function to get PMU Firmware version using the mailbox driver or smc call based on if running SPL or not. Additionally gets version as part of the ZynqMP Firmware driver probing Signed-off-by: Ibai Erkiaga Signed-off-by: Michal Simek --- drivers/firmware/firmware-zynqmp.c | 76 +++++++++++++++++++++++++++++- 1 file changed, 74 insertions(+), 2 deletions(-) diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 5ed2b32c11..d1fff328e8 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -12,11 +12,76 @@ #include #include +#define PMUFW_PAYLOAD_ARG_CNT 8 + struct zynqmp_power { struct mbox_chan tx_chan; struct mbox_chan rx_chan; } zynqmp_power; +static int ipi_req(const u32 *req, size_t req_len, u32 *res, size_t res_maxlen) +{ + struct zynqmp_ipi_msg msg; + int ret; + + if (req_len > PMUFW_PAYLOAD_ARG_CNT || + res_maxlen > PMUFW_PAYLOAD_ARG_CNT) + return -EINVAL; + + if (!(zynqmp_power.tx_chan.dev) || !(&zynqmp_power.rx_chan.dev)) + return -EINVAL; + + msg.buf = (u32 *)req; + msg.len = req_len; + ret = mbox_send(&zynqmp_power.tx_chan, &msg); + if (ret) { + debug("%s: Sending message failed\n", __func__); + return ret; + } + + msg.buf = res; + msg.len = res_maxlen; + ret = mbox_recv(&zynqmp_power.rx_chan, &msg, 100); + if (ret) + debug("%s: Receiving message failed\n", __func__); + + return ret; +} + +unsigned int zynqmp_firmware_version(void) +{ + int ret; + u32 ret_payload[PAYLOAD_ARG_CNT]; + static u32 pm_api_version = ZYNQMP_PM_VERSION_INVALID; + + /* + * Get PMU version only once and later + * just return stored values instead of + * asking PMUFW again. + **/ + if (pm_api_version == ZYNQMP_PM_VERSION_INVALID) { + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + const u32 request[] = { PM_GET_API_VERSION }; + + ret = ipi_req(request, ARRAY_SIZE(request), + ret_payload, 2); + } else { + ret = invoke_smc(ZYNQMP_SIP_SVC_GET_API_VERSION, 0, 0, + 0, 0, ret_payload); + }; + + if (ret) + panic("PMUFW is not found - Please load it!\n"); + + pm_api_version = ret_payload[1]; + if (pm_api_version < ZYNQMP_PM_VERSION) + panic("PMUFW version error. Expected: v%d.%d\n", + ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR); + } + + return pm_api_version; +}; + static int zynqmp_power_probe(struct udevice *dev) { int ret = 0; @@ -30,10 +95,17 @@ static int zynqmp_power_probe(struct udevice *dev) } ret = mbox_get_by_name(dev, "rx", &zynqmp_power.rx_chan); - if (ret) + if (ret) { debug("%s, cannot rx mailbox\n", __func__); + return ret; + } - return ret; + ret = zynqmp_firmware_version(); + printf("PMUFW:\tv%d.%d\n", + ret >> ZYNQMP_PM_VERSION_MAJOR_SHIFT, + ret & ZYNQMP_PM_VERSION_MINOR_MASK); + + return 0; }; static const struct udevice_id zynqmp_power_ids[] = { From 009ab7b93abac255a3dbfa76a9d7ebe69d846e98 Mon Sep 17 00:00:00 2001 From: Ibai Erkiaga Date: Fri, 27 Sep 2019 11:37:01 +0100 Subject: [PATCH 75/85] firmware: zynqmp: create firmware header New firmware header to place firmware specific macro and function declarations. The patch also moves the macros defining PM operations as well as some helper macros. Signed-off-by: Ibai Erkiaga Signed-off-by: Michal Simek --- MAINTAINERS | 1 + arch/arm/mach-zynqmp/cpu.c | 1 + arch/arm/mach-zynqmp/include/mach/sys_proto.h | 25 ------------ board/xilinx/zynqmp/cmds.c | 1 + board/xilinx/zynqmp/zynqmp.c | 1 + drivers/firmware/firmware-zynqmp.c | 1 + drivers/fpga/zynqmppl.c | 1 + include/zynqmp_firmware.h | 38 +++++++++++++++++++ 8 files changed, 44 insertions(+), 25 deletions(-) create mode 100644 include/zynqmp_firmware.h diff --git a/MAINTAINERS b/MAINTAINERS index 6af9816a4a..2ef2976855 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -461,6 +461,7 @@ F: drivers/timer/cadence-ttc.c F: drivers/usb/host/ehci-zynq.c F: drivers/watchdog/cdns_wdt.c F: include/zynqmppl.h +F: include/zynqmp_firmware.h F: tools/zynqmp* N: ultra96 N: zynqmp diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index 5ef1a52862..f28b964a15 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -9,6 +9,7 @@ #include #include #include +#include #define ZYNQ_SILICON_VER_MASK 0xF000 #define ZYNQ_SILICON_VER_SHIFT 12 diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index 573c4ffcee..6589744454 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -10,8 +10,6 @@ #define PAYLOAD_ARG_CNT 5 #define ZYNQMP_CSU_SILICON_VER_MASK 0xF -#define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD \ - (PM_SIP_SVC + PM_SECURE_IMAGE) #define KEY_PTR_LEN 32 #define ZYNQMP_FPGA_BIT_AUTH_DDR 1 @@ -22,29 +20,6 @@ #define ZYNQMP_FPGA_AUTH_DDR 1 -#define ZYNQMP_SIP_SVC_GET_API_VERSION \ - (PM_SIP_SVC + PM_GET_API_VERSION) - -#define ZYNQMP_PM_VERSION_MAJOR 1 -#define ZYNQMP_PM_VERSION_MINOR 0 -#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16 -#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF - -#define ZYNQMP_PM_VERSION \ - ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \ - ZYNQMP_PM_VERSION_MINOR) - -#define ZYNQMP_PM_VERSION_INVALID ~0 - -#define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0) - -#define PM_SIP_SVC 0xc2000000 - -enum pm_api_id { - PM_GET_API_VERSION = 1, - PM_SECURE_IMAGE = 45, -}; - enum { IDCODE, VERSION, diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c index ed7ba58c64..f53a1b63be 100644 --- a/board/xilinx/zynqmp/cmds.c +++ b/board/xilinx/zynqmp/cmds.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 6524badf29..d9186f463f 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index d1fff328e8..8327214290 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -10,6 +10,7 @@ #if defined(CONFIG_ZYNQMP_IPI) #include +#include #include #define PMUFW_PAYLOAD_ARG_CNT 8 diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index f6d9d50ef1..6168626aee 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h new file mode 100644 index 0000000000..30bf870b02 --- /dev/null +++ b/include/zynqmp_firmware.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Xilinx Zynq MPSoC Firmware driver + * + * Copyright (C) 2018-2019 Xilinx, Inc. + */ + +#ifndef _ZYNQMP_FIRMWARE_H_ +#define _ZYNQMP_FIRMWARE_H_ + +enum pm_api_id { + PM_GET_API_VERSION = 1, + PM_SET_CONFIGURATION, + PM_SECURE_IMAGE = 45, +}; + +#define PM_SIP_SVC 0xc2000000 +#define ZYNQMP_SIP_SVC_GET_API_VERSION \ + (PM_SIP_SVC + PM_GET_API_VERSION) +#define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD \ + (PM_SIP_SVC + PM_SECURE_IMAGE) + +#define ZYNQMP_PM_VERSION_MAJOR 1 +#define ZYNQMP_PM_VERSION_MINOR 0 +#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16 +#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF + +#define ZYNQMP_PM_VERSION \ + ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \ + ZYNQMP_PM_VERSION_MINOR) + +#define ZYNQMP_PM_VERSION_INVALID ~0 + +#define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0) + +unsigned int zynqmp_firmware_version(void); + +#endif /* _ZYNQMP_FIRMWARE_H_ */ From 5743981e27f7b22b9b0edef8618e61157b16c65a Mon Sep 17 00:00:00 2001 From: Ibai Erkiaga Date: Fri, 27 Sep 2019 11:37:02 +0100 Subject: [PATCH 76/85] arm64: zynqmp: use firmware driver to get version Use the new function from firmware version to get the firmware version. Signed-off-by: Ibai Erkiaga Signed-off-by: Michal Simek --- board/xilinx/zynqmp/zynqmp.c | 2 +- drivers/fpga/zynqmppl.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index d9186f463f..8a66d3e50a 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -321,7 +321,7 @@ int board_early_init_f(void) #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP) u32 pm_api_version; - pm_api_version = zynqmp_pmufw_version(); + pm_api_version = zynqmp_firmware_version(); printf("PMUFW:\tv%d.%d\n", pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT, pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK); diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index 6168626aee..c2670271c8 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -152,7 +152,7 @@ static ulong zynqmp_align_dma_buffer(u32 *buf, u32 len, u32 swap) buf = new_buf; } else if ((swap != SWAP_DONE) && - (zynqmp_pmufw_version() <= PMUFW_V1_0)) { + (zynqmp_firmware_version() <= PMUFW_V1_0)) { /* For bitstream which are aligned */ new_buf = buf; @@ -205,7 +205,7 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, u32 ret_payload[PAYLOAD_ARG_CNT]; bool xilfpga_old = false; - if (zynqmp_pmufw_version() <= PMUFW_V1_0) { + if (zynqmp_firmware_version() <= PMUFW_V1_0) { puts("WARN: PMUFW v1.0 or less is detected\n"); puts("WARN: Not all bitstream formats are supported\n"); puts("WARN: Please upgrade PMUFW\n"); From 283d81acba00828366bbb4a38f62b035ba36d003 Mon Sep 17 00:00:00 2001 From: Ibai Erkiaga Date: Fri, 27 Sep 2019 11:37:03 +0100 Subject: [PATCH 77/85] arm64: zynqmp: remove old fw version function Removes the old function to get the firmware version. Signed-off-by: Ibai Erkiaga Signed-off-by: Michal Simek --- arch/arm/mach-zynqmp/cpu.c | 23 ------------------- arch/arm/mach-zynqmp/include/mach/sys_proto.h | 1 - 2 files changed, 24 deletions(-) diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index f28b964a15..bb21cbcadf 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -180,29 +180,6 @@ int __maybe_unused invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, return regs.regs[0]; } -unsigned int __maybe_unused zynqmp_pmufw_version(void) -{ - int ret; - u32 ret_payload[PAYLOAD_ARG_CNT]; - static u32 pm_api_version = ZYNQMP_PM_VERSION_INVALID; - - /* - * Get PMU version only once and later - * just return stored values instead of - * asking PMUFW again. - */ - if (pm_api_version == ZYNQMP_PM_VERSION_INVALID) { - ret = invoke_smc(ZYNQMP_SIP_SVC_GET_API_VERSION, 0, 0, 0, 0, - ret_payload); - pm_api_version = ret_payload[1]; - - if (ret) - panic("PMUFW is not found - Please load it!\n"); - } - - return pm_api_version; -} - static int zynqmp_mmio_rawwrite(const u32 address, const u32 mask, const u32 value) diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index 6589744454..27603a60ff 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -48,7 +48,6 @@ unsigned int zynqmp_get_silicon_version(void); void handoff_setup(void); -unsigned int zynqmp_pmufw_version(void); int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); int zynqmp_mmio_read(const u32 address, u32 *value); int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, From 325a22dc196a8738ba8389b8a4086345ff5e98db Mon Sep 17 00:00:00 2001 From: Ibai Erkiaga Date: Fri, 27 Sep 2019 11:37:04 +0100 Subject: [PATCH 78/85] arm64: zynqmp: probe firmware driver Probe ZynqMP firmware driver on the board initialization phase and ensure that firmware is in place to continue execution. The probing is done on board_init so it can be used for both SPL and U-Boot proper. Signed-off-by: Ibai Erkiaga Signed-off-by: Michal Simek --- arch/arm/Kconfig | 3 +++ board/xilinx/zynqmp/zynqmp.c | 18 ++++++------------ 2 files changed, 9 insertions(+), 12 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0c41bc3e5b..90bcc8d644 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1057,9 +1057,12 @@ config ARCH_ZYNQMP select DM_SPI if SPI select DM_SPI_FLASH if DM_SPI select DM_USB if USB + select FIRMWARE select OF_CONTROL select SPL_BOARD_INIT if SPL select SPL_CLK if SPL + select SPL_DM_MAILBOX if SPL + select SPL_FIRMWARE if SPL select SPL_SEPARATE_BSS if SPL select SUPPORT_SPL select ZYNQMP_IPI diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 8a66d3e50a..b94936474d 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -318,18 +318,6 @@ static char *zynqmp_get_silicon_idcode_name(void) int board_early_init_f(void) { int ret = 0; -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP) - u32 pm_api_version; - - pm_api_version = zynqmp_firmware_version(); - printf("PMUFW:\tv%d.%d\n", - pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT, - pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK); - - if (pm_api_version < ZYNQMP_PM_VERSION) - panic("PMUFW version error. Expected: v%d.%d\n", - ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR); -#endif #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED) ret = psu_init(); @@ -340,6 +328,12 @@ int board_early_init_f(void) int board_init(void) { + struct udevice *dev; + + uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev); + if (!dev) + panic("PMU Firmware device not found - Enable it"); + #if defined(CONFIG_SPL_BUILD) /* Check *at build time* if the filename is an non-empty string */ if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1) From b6039aad2d233622729282d1ecd9963366dbf0b4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 27 Sep 2019 14:08:41 +0200 Subject: [PATCH 79/85] firmware: zynqmp: Separate function for sending message via mailbox U-Boot running in EL3 can't use SMC that's why there is a need to talk to PMUFW directly via mailbox. The same logic is applied to all functions which need to talk to PMUFW that's why move this logic to separate function to avoid code duplication. Also SMC request ID can be composed from PM_SIP_SVC offset that's why ZYNQMP_SIP_SVC_GET_API_VERSION macro can be removed completely. Signed-off-by: Michal Simek --- drivers/firmware/firmware-zynqmp.c | 19 ++++++++++--------- include/zynqmp_firmware.h | 2 -- 2 files changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 8327214290..304398fed6 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -49,6 +49,14 @@ static int ipi_req(const u32 *req, size_t req_len, u32 *res, size_t res_maxlen) return ret; } +static int send_req(const u32 *req, size_t req_len, u32 *res, size_t res_maxlen) +{ + if (IS_ENABLED(CONFIG_SPL_BUILD)) + return ipi_req(req, req_len, res, res_maxlen); + + return invoke_smc(req[0] + PM_SIP_SVC, 0, 0, 0, 0, res); +} + unsigned int zynqmp_firmware_version(void) { int ret; @@ -61,16 +69,9 @@ unsigned int zynqmp_firmware_version(void) * asking PMUFW again. **/ if (pm_api_version == ZYNQMP_PM_VERSION_INVALID) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) { - const u32 request[] = { PM_GET_API_VERSION }; - - ret = ipi_req(request, ARRAY_SIZE(request), - ret_payload, 2); - } else { - ret = invoke_smc(ZYNQMP_SIP_SVC_GET_API_VERSION, 0, 0, - 0, 0, ret_payload); - }; + const u32 request[] = { PM_GET_API_VERSION }; + ret = send_req(request, ARRAY_SIZE(request), ret_payload, 2); if (ret) panic("PMUFW is not found - Please load it!\n"); diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 30bf870b02..cebac74e91 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -15,8 +15,6 @@ enum pm_api_id { }; #define PM_SIP_SVC 0xc2000000 -#define ZYNQMP_SIP_SVC_GET_API_VERSION \ - (PM_SIP_SVC + PM_GET_API_VERSION) #define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD \ (PM_SIP_SVC + PM_SECURE_IMAGE) From a3e552b53fb85abce33a8e00bc430d014d7ee733 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 27 Sep 2019 14:20:00 +0200 Subject: [PATCH 80/85] arm64: zynqmp: Use mailbox driver for PMUFW config loading With new mailbox driver PMUFW configuration object can be loaded via the same interface and there is no need to have pmu_ipc.c completely. Signed-off-by: Michal Simek Reviewed-by: Luca Ceresoli --- arch/arm/mach-zynqmp/Makefile | 4 - arch/arm/mach-zynqmp/include/mach/sys_proto.h | 2 - arch/arm/mach-zynqmp/pmu_ipc.c | 112 ------------------ drivers/firmware/firmware-zynqmp.c | 24 ++++ include/zynqmp_firmware.h | 1 + 5 files changed, 25 insertions(+), 118 deletions(-) delete mode 100644 arch/arm/mach-zynqmp/pmu_ipc.c diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile index f3765e45b1..8a3b074724 100644 --- a/arch/arm/mach-zynqmp/Makefile +++ b/arch/arm/mach-zynqmp/Makefile @@ -8,7 +8,3 @@ obj-y += cpu.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o obj-$(CONFIG_ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o - -ifneq ($(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE),"") -obj-$(CONFIG_SPL_BUILD) += pmu_ipc.o -endif diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index 27603a60ff..69e729fb76 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -60,6 +60,4 @@ int chip_id(unsigned char id); void tcm_init(u8 mode); #endif -void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size); - #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/mach-zynqmp/pmu_ipc.c b/arch/arm/mach-zynqmp/pmu_ipc.c deleted file mode 100644 index d8858ea3ff..0000000000 --- a/arch/arm/mach-zynqmp/pmu_ipc.c +++ /dev/null @@ -1,112 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Inter-Processor Communication with the Platform Management Unit (PMU) - * firmware. - * - * (C) Copyright 2019 Luca Ceresoli - * Luca Ceresoli - */ - -#include -#include -#include - -/* IPI bitmasks, register base and register offsets */ -#define IPI_BIT_MASK_APU 0x00001 -#define IPI_BIT_MASK_PMU0 0x10000 -#define IPI_REG_BASE_APU 0xFF300000 -#define IPI_REG_BASE_PMU0 0xFF330000 -#define IPI_REG_OFFSET_TRIG 0x00 -#define IPI_REG_OFFSET_OBR 0x04 - -/* IPI mailbox buffer offsets */ -#define IPI_BUF_BASE_APU 0xFF990400 -#define IPI_BUF_OFFSET_TARGET_PMU 0x1C0 -#define IPI_BUF_OFFSET_REQ 0x00 -#define IPI_BUF_OFFSET_RESP 0x20 - -#define PMUFW_PAYLOAD_ARG_CNT 8 - -/* PMUFW commands */ -#define PMUFW_CMD_SET_CONFIGURATION 2 - -static void pmu_ipc_send_request(const u32 *req, size_t req_len) -{ - u32 *mbx = (u32 *)(IPI_BUF_BASE_APU + - IPI_BUF_OFFSET_TARGET_PMU + - IPI_BUF_OFFSET_REQ); - size_t i; - - for (i = 0; i < req_len; i++) - writel(req[i], &mbx[i]); -} - -static void pmu_ipc_read_response(unsigned int *value, size_t count) -{ - u32 *mbx = (u32 *)(IPI_BUF_BASE_APU + - IPI_BUF_OFFSET_TARGET_PMU + - IPI_BUF_OFFSET_RESP); - size_t i; - - for (i = 0; i < count; i++) - value[i] = readl(&mbx[i]); -} - -/** - * Send request to PMU and get the response. - * - * @req: Request buffer. Byte 0 is the API ID, other bytes are optional - * parameters. - * @req_len: Request length in number of 32-bit words. - * @res: Response buffer. Byte 0 is the error code, other bytes are - * optional parameters. Optional, if @res_maxlen==0 the parameters - * will not be read. - * @res_maxlen: Space allocated for the response in number of 32-bit words. - * - * @return Error code returned by the PMU (i.e. the first word of the response) - */ -static int pmu_ipc_request(const u32 *req, size_t req_len, - u32 *res, size_t res_maxlen) -{ - u32 status; - - if (req_len > PMUFW_PAYLOAD_ARG_CNT || - res_maxlen > PMUFW_PAYLOAD_ARG_CNT) - return -EINVAL; - - pmu_ipc_send_request(req, req_len); - - /* Raise Inter-Processor Interrupt to PMU and wait for response */ - writel(IPI_BIT_MASK_PMU0, IPI_REG_BASE_APU + IPI_REG_OFFSET_TRIG); - do { - status = readl(IPI_REG_BASE_APU + IPI_REG_OFFSET_OBR); - } while (status & IPI_BIT_MASK_PMU0); - - pmu_ipc_read_response(res, res_maxlen); - - return 0; -} - -/** - * Send a configuration object to the PMU firmware. - * - * @cfg_obj: Pointer to the configuration object - * @size: Size of @cfg_obj in bytes - */ -void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size) -{ - const u32 request[] = { - PMUFW_CMD_SET_CONFIGURATION, - (u32)((u64)cfg_obj) - }; - u32 response; - int err; - - printf("Loading PMUFW cfg obj (%ld bytes)\n", size); - - err = pmu_ipc_request(request, ARRAY_SIZE(request), &response, 1); - if (err) - panic("Cannot load PMUFW configuration object (%d)\n", err); - if (response != 0) - panic("PMUFW returned 0x%08x status!\n", response); -} diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 304398fed6..15e82ac3b3 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -84,6 +84,30 @@ unsigned int zynqmp_firmware_version(void) return pm_api_version; }; +/** + * Send a configuration object to the PMU firmware. + * + * @cfg_obj: Pointer to the configuration object + * @size: Size of @cfg_obj in bytes + */ +void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size) +{ + const u32 request[] = { + PM_SET_CONFIGURATION, + (u32)((u64)cfg_obj) + }; + u32 response; + int err; + + printf("Loading new PMUFW cfg obj (%ld bytes)\n", size); + + err = send_req(request, ARRAY_SIZE(request), &response, 1); + if (err) + panic("Cannot load PMUFW configuration object (%d)\n", err); + if (response != 0) + panic("PMUFW returned 0x%08x status!\n", response); +} + static int zynqmp_power_probe(struct udevice *dev) { int ret = 0; diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index cebac74e91..a20cbcdb86 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -32,5 +32,6 @@ enum pm_api_id { #define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0) unsigned int zynqmp_firmware_version(void); +void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size); #endif /* _ZYNQMP_FIRMWARE_H_ */ From fec657bebd77d789a7f9708b79f95225a9c4eeef Mon Sep 17 00:00:00 2001 From: Ibai Erkiaga Date: Wed, 2 Oct 2019 15:57:36 +0100 Subject: [PATCH 81/85] arm64: versal: Move common board dtb search Move the exisiting function of getting board dtb from versal to a common Xilinx folder. Signed-off-by: Ibai Erkiaga Signed-off-by: Michal Simek --- arch/arm/mach-versal/Kconfig | 5 ----- arch/arm/mach-versal/cpu.c | 14 -------------- board/xilinx/Kconfig | 7 +++++++ board/xilinx/common/board.c | 14 ++++++++++++++ board/xilinx/versal/Makefile | 1 + 5 files changed, 22 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig index 06a0352924..a08e5ae414 100644 --- a/arch/arm/mach-versal/Kconfig +++ b/arch/arm/mach-versal/Kconfig @@ -36,11 +36,6 @@ config COUNTER_FREQUENCY config ZYNQ_SDHCI_MAX_FREQ default 200000000 -config VERSAL_OF_BOARD_DTB_ADDR - hex - default 0x1000 - depends on OF_BOARD - config IOU_SWITCH_DIVISOR0 hex "IOU switch divisor0" default 0x20 diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index db96225827..49f1e51c8e 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -108,20 +108,6 @@ int reserve_mmu(void) } #endif -#if defined(CONFIG_OF_BOARD) -void *board_fdt_blob_setup(void) -{ - static void *fw_dtb = (void *)CONFIG_VERSAL_OF_BOARD_DTB_ADDR; - - if (fdt_magic(fw_dtb) != FDT_MAGIC) { - printf("DTB is not passed via %llx\n", (u64)fw_dtb); - return NULL; - } - - return fw_dtb; -} -#endif - int versal_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 *ret_payload) { diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig index 37bec5fae2..4f290339a0 100644 --- a/board/xilinx/Kconfig +++ b/board/xilinx/Kconfig @@ -39,3 +39,10 @@ config XILINX_PS_INIT_FILE before the build. endif + +config VERSAL_OF_BOARD_DTB_ADDR + hex + default 0x1000 + depends on OF_BOARD + help + Offset in the memory where the board configuration DTB is placed. diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 7e6340bad6..f66973bc66 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -36,3 +36,17 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) return ret; } + +#if defined(CONFIG_OF_BOARD) +void *board_fdt_blob_setup(void) +{ + static void *fw_dtb = (void *)CONFIG_VERSAL_OF_BOARD_DTB_ADDR; + + if (fdt_magic(fw_dtb) != FDT_MAGIC) { + printf("DTB is not passed via %p\n", fw_dtb); + return NULL; + } + + return fw_dtb; +} +#endif diff --git a/board/xilinx/versal/Makefile b/board/xilinx/versal/Makefile index 2b812765ee..e9307d7fa6 100644 --- a/board/xilinx/versal/Makefile +++ b/board/xilinx/versal/Makefile @@ -5,3 +5,4 @@ # obj-y := board.o +obj-y += ../common/board.o From f4e7e611936942fb15994d22a398707028416081 Mon Sep 17 00:00:00 2001 From: Ibai Erkiaga Date: Wed, 2 Oct 2019 15:57:37 +0100 Subject: [PATCH 82/85] arm64: xilinx: Enable generic of_board_dtb Modify the configuration naming to be generic to xilinx rather than specific to Versal. The offset value is different for Zynq and ZynqMP to avoid overlapping with FSBL. Signed-off-by: Ibai Erkiaga Signed-off-by: Michal Simek --- board/xilinx/Kconfig | 5 +++-- board/xilinx/common/board.c | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig index 4f290339a0..cb272eafda 100644 --- a/board/xilinx/Kconfig +++ b/board/xilinx/Kconfig @@ -40,9 +40,10 @@ config XILINX_PS_INIT_FILE endif -config VERSAL_OF_BOARD_DTB_ADDR +config XILINX_OF_BOARD_DTB_ADDR hex - default 0x1000 + default 0x1000 if ARCH_VERSAL + default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP depends on OF_BOARD help Offset in the memory where the board configuration DTB is placed. diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index f66973bc66..1c28263cb8 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -40,7 +40,7 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) #if defined(CONFIG_OF_BOARD) void *board_fdt_blob_setup(void) { - static void *fw_dtb = (void *)CONFIG_VERSAL_OF_BOARD_DTB_ADDR; + static void *fw_dtb = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR; if (fdt_magic(fw_dtb) != FDT_MAGIC) { printf("DTB is not passed via %p\n", fw_dtb); From 4b37c13dc3531c6d32c6f247944e5b2b4f7fe55e Mon Sep 17 00:00:00 2001 From: Ibai Erkiaga Date: Wed, 2 Oct 2019 15:57:38 +0100 Subject: [PATCH 83/85] arm64: zynqmp: Introduce virtual defconfig Add virtual defconfig for ZynqMP architecture using of_board dtb. This defconfig should become generic config for all ZynqMP boards. Signed-off-by: Ibai Erkiaga Signed-off-by: Michal Simek --- configs/xilinx_zynqmp_virt_defconfig | 108 +++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) create mode 100644 configs/xilinx_zynqmp_virt_defconfig diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig new file mode 100644 index 0000000000..14eb06a405 --- /dev/null +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -0,0 +1,108 @@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_ZYNQMP_USB=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y +CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SDRAM=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_BOARD=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_CLK_ZYNQMP=y +CONFIG_DFU_RAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_DM_GPIO=y +CONFIG_XILINX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 +CONFIG_SYS_I2C_EEPROM_ADDR=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_MARVELL=y +CONFIG_PHY_NATSEMI=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_TI=y +CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y +CONFIG_PHY_GIGE=y +CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_ZYNQMP_GQSPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_ZYNQMP=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Xilinx" +CONFIG_USB_GADGET_VENDOR_NUM=0x03FD +CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 +CONFIG_USB_FUNCTION_THOR=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y From 8ebd601541d70d11839f80fec29ab24716e8c010 Mon Sep 17 00:00:00 2001 From: Ibai Erkiaga Date: Wed, 2 Oct 2019 15:57:39 +0100 Subject: [PATCH 84/85] ARM: zynq: Introduce virtual defconfig Add virtual defconfig for Zynq architecture using of_board dtb. This defconfig should become generic config for all Zynq boards. Signed-off-by: Ibai Erkiaga Signed-off-by: Michal Simek --- configs/zynq_virt_defconfig | 79 +++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 configs/zynq_virt_defconfig diff --git a/configs/zynq_virt_defconfig b/configs/zynq_virt_defconfig new file mode 100644 index 0000000000..58ce970a1b --- /dev/null +++ b/configs/zynq_virt_defconfig @@ -0,0 +1,79 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_ZYNQ=y +CONFIG_SYS_TEXT_BASE=0x4000000 +CONFIG_SPL_STACK_R_ADDR=0x200000 +CONFIG_SPL=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_CUSTOM_LDSCRIPT=y +CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_USE_PREBOOT=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 +CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADFS=y +CONFIG_CMD_FPGA_LOADMK=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_BOARD=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQPL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x0 +CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=30000000 +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_MARVELL=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_XILINX=y +CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Xilinx" +CONFIG_USB_GADGET_VENDOR_NUM=0x03fd +CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_THOR=y From bcaa0e3302e384ad65c352b385678acdf3f20c0a Mon Sep 17 00:00:00 2001 From: Ibai Erkiaga Date: Wed, 2 Oct 2019 15:57:40 +0100 Subject: [PATCH 85/85] arm64: versal: remove debug uart for versal virt Remove the debug uart configuration from versal virtual defconfig. Signed-off-by: Ibai Erkiaga Signed-off-by: Michal Simek --- configs/xilinx_versal_virt_defconfig | 5 ----- 1 file changed, 5 deletions(-) diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index f924d3e542..3ff23a2b2b 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -2,10 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_VERSAL=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=0 CONFIG_COUNTER_FREQUENCY=62500000 -CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -68,8 +65,6 @@ CONFIG_PHY_FIXED=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART_PL011=y -CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_PL01X_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y