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Merge branch 'fpga' of git://www.denx.de/git/u-boot-microblaze

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This commit is contained in:
Tom Rini 2015-01-22 09:48:22 -05:00
commit 4608f37918
9 changed files with 158 additions and 67 deletions
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4
board/xilinx/zynq/board.c
View file

@ -24,6 +24,7 @@ static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
#endif
@ -49,6 +50,9 @@ int board_init(void)
case XILINX_ZYNQ_7030:
fpga = fpga030;
break;
case XILINX_ZYNQ_7035:
fpga = fpga035;
break;
case XILINX_ZYNQ_7045:
fpga = fpga045;
break;

5
common/cmd_fpga.c
View file

@ -211,6 +211,7 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
comp = image_get_comp(hdr);
if (comp == IH_COMP_GZIP) {
#if defined(CONFIG_GZIP)
ulong image_buf = image_get_data(hdr);
data = image_get_load(hdr);
ulong image_size = ~0UL;
@ -222,6 +223,10 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
return 1;
}
data_size = image_size;
#else
puts("Gunzip image is not supported\n");
return 1;
#endif
} else {
data = (ulong)image_get_data(hdr);
data_size = image_get_data_size(hdr);

2
drivers/fpga/fpga.c
View file

@ -38,7 +38,7 @@ static void fpga_no_sup(char *fn, char *msg)
/* fpga_get_desc
* map a device number to a descriptor
*/
static const fpga_desc *const fpga_get_desc(int devnum)
const fpga_desc *const fpga_get_desc(int devnum)
{
fpga_desc *desc = (fpga_desc *)NULL;

22
drivers/fpga/xilinx.c
View file

@ -139,6 +139,11 @@ int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize,
return FPGA_FAIL;
}
if (!desc->operations || !desc->operations->load) {
printf("%s: Missing load operation\n", __func__);
return FPGA_FAIL;
}
return desc->operations->load(desc, buf, bsize, bstype);
}
@ -151,8 +156,10 @@ int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
return FPGA_FAIL;
}
if (!desc->operations->loadfs)
if (!desc->operations || !desc->operations->loadfs) {
printf("%s: Missing loadfs operation\n", __func__);
return FPGA_FAIL;
}
return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo);
}
@ -165,6 +172,11 @@ int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
return FPGA_FAIL;
}
if (!desc->operations || !desc->operations->dump) {
printf("%s: Missing dump operation\n", __func__);
return FPGA_FAIL;
}
return desc->operations->dump(desc, buf, bsize);
}
@ -226,12 +238,14 @@ int xilinx_info(xilinx_desc *desc)
if (desc->name)
printf("Device name: \t%s\n", desc->name);
if (desc->iface_fns) {
if (desc->iface_fns)
printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
desc->operations->info(desc);
} else
else
printf ("No Device Function Table.\n");
if (desc->operations && desc->operations->info)
desc->operations->info(desc);
ret_val = FPGA_SUCCESS;
} else {
printf ("%s: Invalid device descriptor\n", __FUNCTION__);

27
include/fpga.h
View file

@ -49,18 +49,19 @@ typedef enum {
} bitstream_type;
/* root function definitions */
extern void fpga_init(void);
extern int fpga_add(fpga_type devtype, void *desc);
extern int fpga_count(void);
extern int fpga_load(int devnum, const void *buf, size_t bsize,
bitstream_type bstype);
extern int fpga_fsload(int devnum, const void *buf, size_t size,
fpga_fs_info *fpga_fsinfo);
extern int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
bitstream_type bstype);
extern int fpga_dump(int devnum, const void *buf, size_t bsize);
extern int fpga_info(int devnum);
extern const fpga_desc *const fpga_validate(int devnum, const void *buf,
size_t bsize, char *fn);
void fpga_init(void);
int fpga_add(fpga_type devtype, void *desc);
int fpga_count(void);
const fpga_desc *const fpga_get_desc(int devnum);
int fpga_load(int devnum, const void *buf, size_t bsize,
bitstream_type bstype);
int fpga_fsload(int devnum, const void *buf, size_t size,
fpga_fs_info *fpga_fsinfo);
int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
bitstream_type bstype);
int fpga_dump(int devnum, const void *buf, size_t bsize);
int fpga_info(int devnum);
const fpga_desc *const fpga_validate(int devnum, const void *buf,
size_t bsize, char *fn);
#endif /* _FPGA_H_ */

38
include/spartan2.h
View file

@ -38,7 +38,12 @@ typedef struct {
xilinx_post_fn post;
} xilinx_spartan2_slave_serial_fns;
#if defined(CONFIG_FPGA_SPARTAN2)
extern struct xilinx_fpga_op spartan2_op;
# define FPGA_SPARTAN2_OPS &spartan2_op
#else
# define FPGA_SPARTAN2_OPS NULL
#endif
/* Device Image Sizes
*********************************************************************/
@ -61,36 +66,47 @@ extern struct xilinx_fpga_op spartan2_op;
*********************************************************************/
/* Spartan-II devices */
#define XILINX_XC2S15_DESC(iface, fn_table, cookie) \
{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, &spartan2_op }
{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, \
FPGA_SPARTAN2_OPS }
#define XILINX_XC2S30_DESC(iface, fn_table, cookie) \
{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, &spartan2_op }
{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, \
FPGA_SPARTAN2_OPS }
#define XILINX_XC2S50_DESC(iface, fn_table, cookie) \
{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, &spartan2_op }
{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, \
FPGA_SPARTAN2_OPS }
#define XILINX_XC2S100_DESC(iface, fn_table, cookie) \
{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, &spartan2_op }
{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, \
FPGA_SPARTAN2_OPS }
#define XILINX_XC2S150_DESC(iface, fn_table, cookie) \
{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, &spartan2_op }
{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, \
FPGA_SPARTAN2_OPS }
#define XILINX_XC2S200_DESC(iface, fn_table, cookie) \
{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, &spartan2_op }
{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, \
FPGA_SPARTAN2_OPS }
#define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, &spartan2_op }
{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, \
FPGA_SPARTAN2_OPS }
#define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, &spartan2_op }
{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, \
FPGA_SPARTAN2_OPS }
#define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, &spartan2_op }
{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, \
FPGA_SPARTAN2_OPS }
#define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, &spartan2_op }
{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, \
FPGA_SPARTAN2_OPS }
#define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, &spartan2_op }
{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, \
FPGA_SPARTAN2_OPS }
#endif /* _SPARTAN2_H_ */

45
include/spartan3.h
View file

@ -40,7 +40,12 @@ typedef struct {
xilinx_abort_fn abort;
} xilinx_spartan3_slave_serial_fns;
#if defined(CONFIG_FPGA_SPARTAN3)
extern struct xilinx_fpga_op spartan3_op;
# define FPGA_SPARTAN3_OPS &spartan3_op
#else
# define FPGA_SPARTAN3_OPS NULL
#endif
/* Device Image Sizes
*********************************************************************/
@ -71,48 +76,60 @@ extern struct xilinx_fpga_op spartan3_op;
*********************************************************************/
/* Spartan-III devices */
#define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, &spartan3_op }
{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, \
FPGA_SPARTAN3_OPS }
#define XILINX_XC3S200_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, &spartan3_op }
{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, \
FPGA_SPARTAN3_OPS }
#define XILINX_XC3S400_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, &spartan3_op }
{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, \
FPGA_SPARTAN3_OPS }
#define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, &spartan3_op }
{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, \
FPGA_SPARTAN3_OPS }
#define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, &spartan3_op }
{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, \
FPGA_SPARTAN3_OPS }
#define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, &spartan3_op }
{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, \
FPGA_SPARTAN3_OPS }
#define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, &spartan3_op }
{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, \
FPGA_SPARTAN3_OPS }
#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, &spartan3_op }
{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, \
FPGA_SPARTAN3_OPS }
/* Spartan-3E devices */
#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, &spartan3_op }
{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, \
FPGA_SPARTAN3_OPS }
#define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, &spartan3_op }
{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, \
FPGA_SPARTAN3_OPS }
#define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, &spartan3_op }
{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, \
FPGA_SPARTAN3_OPS }
#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie, \
&spartan3_op }
FPGA_SPARTAN3_OPS }
#define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie, \
&spartan3_op }
FPGA_SPARTAN3_OPS }
#define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, &spartan3_op }
{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, \
FPGA_SPARTAN3_OPS }
#endif /* _SPARTAN3_H_ */

53
include/virtex2.h
View file

@ -11,8 +11,6 @@
#include <xilinx.h>
extern struct xilinx_fpga_op virtex2_op;
/*
* Slave SelectMap Implementation function table.
*/
@ -40,12 +38,19 @@ typedef struct {
xilinx_wdata_fn wdata;
} xilinx_virtex2_slave_serial_fns;
#if defined(CONFIG_FPGA_VIRTEX2)
extern struct xilinx_fpga_op virtex2_op;
# define FPGA_VIRTEX2_OPS &virtex2_op
#else
# define FPGA_VIRTEX2_OPS NULL
#endif
/* Device Image Sizes (in bytes)
*********************************************************************/
#define XILINX_XC2V40_SIZE (338208 / 8)
#define XILINX_XC2V80_SIZE (597408 / 8)
#define XILINX_XC2V250_SIZE (1591584 / 8)
#define XILINX_XC2V500_SIZE (2557857 / 8)
#define XILINX_XC2V40_SIZE (338208 / 8)
#define XILINX_XC2V80_SIZE (597408 / 8)
#define XILINX_XC2V250_SIZE (1591584 / 8)
#define XILINX_XC2V500_SIZE (2557857 / 8)
#define XILINX_XC2V1000_SIZE (3749408 / 8)
#define XILINX_XC2V1500_SIZE (5166240 / 8)
#define XILINX_XC2V2000_SIZE (6808352 / 8)
@ -58,39 +63,51 @@ typedef struct {
/* Descriptor Macros
*********************************************************************/
#define XILINX_XC2V40_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, &virtex2_op }
{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, \
FPGA_VIRTEX2_OPS }
#define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, &virtex2_op }
{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, \
FPGA_VIRTEX2_OPS }
#define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, &virtex2_op }
{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, \
FPGA_VIRTEX2_OPS }
#define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, &virtex2_op }
{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, \
FPGA_VIRTEX2_OPS }
#define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, &virtex2_op }
{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, \
FPGA_VIRTEX2_OPS }
#define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, &virtex2_op }
{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, \
FPGA_VIRTEX2_OPS }
#define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, &virtex2_op }
{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, \
FPGA_VIRTEX2_OPS }
#define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, &virtex2_op }
{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, \
FPGA_VIRTEX2_OPS }
#define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, &virtex2_op }
{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, \
FPGA_VIRTEX2_OPS }
#define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, &virtex2_op }
{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, \
FPGA_VIRTEX2_OPS }
#define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, &virtex2_op }
{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, \
FPGA_VIRTEX2_OPS }
#define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, &virtex2_op }
{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, \
FPGA_VIRTEX2_OPS }
#endif /* _VIRTEX2_H_ */

29
include/zynqpl.h
View file

@ -12,12 +12,18 @@
#include <xilinx.h>
#if defined(CONFIG_FPGA_ZYNQPL)
extern struct xilinx_fpga_op zynq_op;
# define FPGA_ZYNQPL_OPS &zynq_op
#else
# define FPGA_ZYNQPL_OPS NULL
#endif
#define XILINX_ZYNQ_7010 0x2
#define XILINX_ZYNQ_7015 0x1b
#define XILINX_ZYNQ_7020 0x7
#define XILINX_ZYNQ_7030 0xc
#define XILINX_ZYNQ_7035 0x12
#define XILINX_ZYNQ_7045 0x11
#define XILINX_ZYNQ_7100 0x16
@ -26,26 +32,37 @@ extern struct xilinx_fpga_op zynq_op;
#define XILINX_XC7Z015_SIZE 28085344/8
#define XILINX_XC7Z020_SIZE 32364512/8
#define XILINX_XC7Z030_SIZE 47839328/8
#define XILINX_XC7Z035_SIZE 106571232/8
#define XILINX_XC7Z045_SIZE 106571232/8
#define XILINX_XC7Z100_SIZE 139330784/8
/* Descriptor Macros */
#define XILINX_XC7Z010_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, &zynq_op, "7z010" }
{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
"7z010" }
#define XILINX_XC7Z015_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, &zynq_op, "7z015" }
{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
"7z015" }
#define XILINX_XC7Z020_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, &zynq_op, "7z020" }
{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
"7z020" }
#define XILINX_XC7Z030_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, &zynq_op, "7z030" }
{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
"7z030" }
#define XILINX_XC7Z035_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
"7z035" }
#define XILINX_XC7Z045_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, &zynq_op, "7z045" }
{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
"7z045" }
#define XILINX_XC7Z100_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, &zynq_op, "7z100" }
{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
"7z100" }
#endif /* _ZYNQPL_H_ */