mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 13:11:31 +00:00
Merge branch 'fpga' of git://www.denx.de/git/u-boot-microblaze
This commit is contained in:
commit
4608f37918
9 changed files with 158 additions and 67 deletions
|
@ -24,6 +24,7 @@ static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
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static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
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static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
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static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
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static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
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static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
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static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
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#endif
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@ -49,6 +50,9 @@ int board_init(void)
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case XILINX_ZYNQ_7030:
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fpga = fpga030;
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break;
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case XILINX_ZYNQ_7035:
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fpga = fpga035;
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break;
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case XILINX_ZYNQ_7045:
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fpga = fpga045;
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break;
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@ -211,6 +211,7 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
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comp = image_get_comp(hdr);
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if (comp == IH_COMP_GZIP) {
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#if defined(CONFIG_GZIP)
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ulong image_buf = image_get_data(hdr);
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data = image_get_load(hdr);
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ulong image_size = ~0UL;
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@ -222,6 +223,10 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
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return 1;
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}
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data_size = image_size;
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#else
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puts("Gunzip image is not supported\n");
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return 1;
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#endif
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} else {
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data = (ulong)image_get_data(hdr);
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data_size = image_get_data_size(hdr);
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@ -38,7 +38,7 @@ static void fpga_no_sup(char *fn, char *msg)
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/* fpga_get_desc
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* map a device number to a descriptor
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*/
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static const fpga_desc *const fpga_get_desc(int devnum)
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const fpga_desc *const fpga_get_desc(int devnum)
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{
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fpga_desc *desc = (fpga_desc *)NULL;
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@ -139,6 +139,11 @@ int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize,
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return FPGA_FAIL;
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}
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if (!desc->operations || !desc->operations->load) {
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printf("%s: Missing load operation\n", __func__);
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return FPGA_FAIL;
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}
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return desc->operations->load(desc, buf, bsize, bstype);
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}
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@ -151,8 +156,10 @@ int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
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return FPGA_FAIL;
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}
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if (!desc->operations->loadfs)
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if (!desc->operations || !desc->operations->loadfs) {
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printf("%s: Missing loadfs operation\n", __func__);
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return FPGA_FAIL;
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}
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return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo);
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}
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@ -165,6 +172,11 @@ int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
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return FPGA_FAIL;
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}
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if (!desc->operations || !desc->operations->dump) {
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printf("%s: Missing dump operation\n", __func__);
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return FPGA_FAIL;
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}
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return desc->operations->dump(desc, buf, bsize);
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}
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@ -226,12 +238,14 @@ int xilinx_info(xilinx_desc *desc)
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if (desc->name)
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printf("Device name: \t%s\n", desc->name);
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if (desc->iface_fns) {
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if (desc->iface_fns)
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printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
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desc->operations->info(desc);
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} else
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else
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printf ("No Device Function Table.\n");
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if (desc->operations && desc->operations->info)
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desc->operations->info(desc);
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ret_val = FPGA_SUCCESS;
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} else {
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printf ("%s: Invalid device descriptor\n", __FUNCTION__);
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@ -49,18 +49,19 @@ typedef enum {
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} bitstream_type;
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/* root function definitions */
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extern void fpga_init(void);
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extern int fpga_add(fpga_type devtype, void *desc);
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extern int fpga_count(void);
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extern int fpga_load(int devnum, const void *buf, size_t bsize,
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bitstream_type bstype);
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extern int fpga_fsload(int devnum, const void *buf, size_t size,
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fpga_fs_info *fpga_fsinfo);
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extern int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
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bitstream_type bstype);
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extern int fpga_dump(int devnum, const void *buf, size_t bsize);
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extern int fpga_info(int devnum);
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extern const fpga_desc *const fpga_validate(int devnum, const void *buf,
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size_t bsize, char *fn);
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void fpga_init(void);
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int fpga_add(fpga_type devtype, void *desc);
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int fpga_count(void);
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const fpga_desc *const fpga_get_desc(int devnum);
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int fpga_load(int devnum, const void *buf, size_t bsize,
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bitstream_type bstype);
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int fpga_fsload(int devnum, const void *buf, size_t size,
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fpga_fs_info *fpga_fsinfo);
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int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
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bitstream_type bstype);
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int fpga_dump(int devnum, const void *buf, size_t bsize);
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int fpga_info(int devnum);
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const fpga_desc *const fpga_validate(int devnum, const void *buf,
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size_t bsize, char *fn);
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#endif /* _FPGA_H_ */
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@ -38,7 +38,12 @@ typedef struct {
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xilinx_post_fn post;
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} xilinx_spartan2_slave_serial_fns;
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#if defined(CONFIG_FPGA_SPARTAN2)
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extern struct xilinx_fpga_op spartan2_op;
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# define FPGA_SPARTAN2_OPS &spartan2_op
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#else
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# define FPGA_SPARTAN2_OPS NULL
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#endif
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/* Device Image Sizes
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*********************************************************************/
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@ -61,36 +66,47 @@ extern struct xilinx_fpga_op spartan2_op;
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*********************************************************************/
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/* Spartan-II devices */
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#define XILINX_XC2S15_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, &spartan2_op }
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{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, \
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FPGA_SPARTAN2_OPS }
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#define XILINX_XC2S30_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, &spartan2_op }
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{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, \
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FPGA_SPARTAN2_OPS }
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#define XILINX_XC2S50_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, &spartan2_op }
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{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, \
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FPGA_SPARTAN2_OPS }
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#define XILINX_XC2S100_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, &spartan2_op }
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{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, \
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FPGA_SPARTAN2_OPS }
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#define XILINX_XC2S150_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, &spartan2_op }
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{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, \
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FPGA_SPARTAN2_OPS }
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#define XILINX_XC2S200_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, &spartan2_op }
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{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, \
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FPGA_SPARTAN2_OPS }
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#define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, &spartan2_op }
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{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, \
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FPGA_SPARTAN2_OPS }
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#define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, &spartan2_op }
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{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, \
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FPGA_SPARTAN2_OPS }
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#define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, &spartan2_op }
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{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, \
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FPGA_SPARTAN2_OPS }
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#define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, &spartan2_op }
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{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, \
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FPGA_SPARTAN2_OPS }
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#define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, &spartan2_op }
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{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, \
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FPGA_SPARTAN2_OPS }
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#endif /* _SPARTAN2_H_ */
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@ -40,7 +40,12 @@ typedef struct {
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xilinx_abort_fn abort;
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} xilinx_spartan3_slave_serial_fns;
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#if defined(CONFIG_FPGA_SPARTAN3)
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extern struct xilinx_fpga_op spartan3_op;
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# define FPGA_SPARTAN3_OPS &spartan3_op
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#else
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# define FPGA_SPARTAN3_OPS NULL
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#endif
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/* Device Image Sizes
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*********************************************************************/
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@ -71,48 +76,60 @@ extern struct xilinx_fpga_op spartan3_op;
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*********************************************************************/
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/* Spartan-III devices */
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#define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, &spartan3_op }
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{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, \
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FPGA_SPARTAN3_OPS }
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#define XILINX_XC3S200_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, &spartan3_op }
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{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, \
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FPGA_SPARTAN3_OPS }
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#define XILINX_XC3S400_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, &spartan3_op }
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{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, \
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FPGA_SPARTAN3_OPS }
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#define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, &spartan3_op }
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{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, \
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FPGA_SPARTAN3_OPS }
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#define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, &spartan3_op }
|
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{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, \
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FPGA_SPARTAN3_OPS }
|
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|
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#define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, &spartan3_op }
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{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, \
|
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FPGA_SPARTAN3_OPS }
|
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|
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#define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
|
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{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, &spartan3_op }
|
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{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, \
|
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FPGA_SPARTAN3_OPS }
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|
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#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, &spartan3_op }
|
||||
{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, \
|
||||
FPGA_SPARTAN3_OPS }
|
||||
|
||||
/* Spartan-3E devices */
|
||||
#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
|
||||
{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, &spartan3_op }
|
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{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, \
|
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FPGA_SPARTAN3_OPS }
|
||||
|
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#define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, &spartan3_op }
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{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, \
|
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FPGA_SPARTAN3_OPS }
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||||
|
||||
#define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
|
||||
{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, &spartan3_op }
|
||||
{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, \
|
||||
FPGA_SPARTAN3_OPS }
|
||||
|
||||
#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
|
||||
{ xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie, \
|
||||
&spartan3_op }
|
||||
FPGA_SPARTAN3_OPS }
|
||||
|
||||
#define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
|
||||
{ xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie, \
|
||||
&spartan3_op }
|
||||
FPGA_SPARTAN3_OPS }
|
||||
|
||||
#define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \
|
||||
{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, &spartan3_op }
|
||||
{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, \
|
||||
FPGA_SPARTAN3_OPS }
|
||||
|
||||
#endif /* _SPARTAN3_H_ */
|
||||
|
|
|
@ -11,8 +11,6 @@
|
|||
|
||||
#include <xilinx.h>
|
||||
|
||||
extern struct xilinx_fpga_op virtex2_op;
|
||||
|
||||
/*
|
||||
* Slave SelectMap Implementation function table.
|
||||
*/
|
||||
|
@ -40,12 +38,19 @@ typedef struct {
|
|||
xilinx_wdata_fn wdata;
|
||||
} xilinx_virtex2_slave_serial_fns;
|
||||
|
||||
#if defined(CONFIG_FPGA_VIRTEX2)
|
||||
extern struct xilinx_fpga_op virtex2_op;
|
||||
# define FPGA_VIRTEX2_OPS &virtex2_op
|
||||
#else
|
||||
# define FPGA_VIRTEX2_OPS NULL
|
||||
#endif
|
||||
|
||||
/* Device Image Sizes (in bytes)
|
||||
*********************************************************************/
|
||||
#define XILINX_XC2V40_SIZE (338208 / 8)
|
||||
#define XILINX_XC2V80_SIZE (597408 / 8)
|
||||
#define XILINX_XC2V250_SIZE (1591584 / 8)
|
||||
#define XILINX_XC2V500_SIZE (2557857 / 8)
|
||||
#define XILINX_XC2V40_SIZE (338208 / 8)
|
||||
#define XILINX_XC2V80_SIZE (597408 / 8)
|
||||
#define XILINX_XC2V250_SIZE (1591584 / 8)
|
||||
#define XILINX_XC2V500_SIZE (2557857 / 8)
|
||||
#define XILINX_XC2V1000_SIZE (3749408 / 8)
|
||||
#define XILINX_XC2V1500_SIZE (5166240 / 8)
|
||||
#define XILINX_XC2V2000_SIZE (6808352 / 8)
|
||||
|
@ -58,39 +63,51 @@ typedef struct {
|
|||
/* Descriptor Macros
|
||||
*********************************************************************/
|
||||
#define XILINX_XC2V40_DESC(iface, fn_table, cookie) \
|
||||
{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, &virtex2_op }
|
||||
{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, \
|
||||
FPGA_VIRTEX2_OPS }
|
||||
|
||||
#define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
|
||||
{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, &virtex2_op }
|
||||
{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, \
|
||||
FPGA_VIRTEX2_OPS }
|
||||
|
||||
#define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
|
||||
{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, &virtex2_op }
|
||||
{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, \
|
||||
FPGA_VIRTEX2_OPS }
|
||||
|
||||
#define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
|
||||
{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, &virtex2_op }
|
||||
{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, \
|
||||
FPGA_VIRTEX2_OPS }
|
||||
|
||||
#define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
|
||||
{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, &virtex2_op }
|
||||
{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, \
|
||||
FPGA_VIRTEX2_OPS }
|
||||
|
||||
#define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
|
||||
{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, &virtex2_op }
|
||||
{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, \
|
||||
FPGA_VIRTEX2_OPS }
|
||||
|
||||
#define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
|
||||
{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, &virtex2_op }
|
||||
{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, \
|
||||
FPGA_VIRTEX2_OPS }
|
||||
|
||||
#define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
|
||||
{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, &virtex2_op }
|
||||
{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, \
|
||||
FPGA_VIRTEX2_OPS }
|
||||
|
||||
#define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
|
||||
{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, &virtex2_op }
|
||||
{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, \
|
||||
FPGA_VIRTEX2_OPS }
|
||||
|
||||
#define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
|
||||
{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, &virtex2_op }
|
||||
{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, \
|
||||
FPGA_VIRTEX2_OPS }
|
||||
|
||||
#define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
|
||||
{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, &virtex2_op }
|
||||
{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, \
|
||||
FPGA_VIRTEX2_OPS }
|
||||
|
||||
#define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
|
||||
{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, &virtex2_op }
|
||||
{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, \
|
||||
FPGA_VIRTEX2_OPS }
|
||||
|
||||
#endif /* _VIRTEX2_H_ */
|
||||
|
|
|
@ -12,12 +12,18 @@
|
|||
|
||||
#include <xilinx.h>
|
||||
|
||||
#if defined(CONFIG_FPGA_ZYNQPL)
|
||||
extern struct xilinx_fpga_op zynq_op;
|
||||
# define FPGA_ZYNQPL_OPS &zynq_op
|
||||
#else
|
||||
# define FPGA_ZYNQPL_OPS NULL
|
||||
#endif
|
||||
|
||||
#define XILINX_ZYNQ_7010 0x2
|
||||
#define XILINX_ZYNQ_7015 0x1b
|
||||
#define XILINX_ZYNQ_7020 0x7
|
||||
#define XILINX_ZYNQ_7030 0xc
|
||||
#define XILINX_ZYNQ_7035 0x12
|
||||
#define XILINX_ZYNQ_7045 0x11
|
||||
#define XILINX_ZYNQ_7100 0x16
|
||||
|
||||
|
@ -26,26 +32,37 @@ extern struct xilinx_fpga_op zynq_op;
|
|||
#define XILINX_XC7Z015_SIZE 28085344/8
|
||||
#define XILINX_XC7Z020_SIZE 32364512/8
|
||||
#define XILINX_XC7Z030_SIZE 47839328/8
|
||||
#define XILINX_XC7Z035_SIZE 106571232/8
|
||||
#define XILINX_XC7Z045_SIZE 106571232/8
|
||||
#define XILINX_XC7Z100_SIZE 139330784/8
|
||||
|
||||
/* Descriptor Macros */
|
||||
#define XILINX_XC7Z010_DESC(cookie) \
|
||||
{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, &zynq_op, "7z010" }
|
||||
{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
|
||||
"7z010" }
|
||||
|
||||
#define XILINX_XC7Z015_DESC(cookie) \
|
||||
{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, &zynq_op, "7z015" }
|
||||
{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
|
||||
"7z015" }
|
||||
|
||||
#define XILINX_XC7Z020_DESC(cookie) \
|
||||
{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, &zynq_op, "7z020" }
|
||||
{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
|
||||
"7z020" }
|
||||
|
||||
#define XILINX_XC7Z030_DESC(cookie) \
|
||||
{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, &zynq_op, "7z030" }
|
||||
{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
|
||||
"7z030" }
|
||||
|
||||
#define XILINX_XC7Z035_DESC(cookie) \
|
||||
{ xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
|
||||
"7z035" }
|
||||
|
||||
#define XILINX_XC7Z045_DESC(cookie) \
|
||||
{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, &zynq_op, "7z045" }
|
||||
{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
|
||||
"7z045" }
|
||||
|
||||
#define XILINX_XC7Z100_DESC(cookie) \
|
||||
{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, &zynq_op, "7z100" }
|
||||
{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
|
||||
"7z100" }
|
||||
|
||||
#endif /* _ZYNQPL_H_ */
|
||||
|
|
Loading…
Add table
Reference in a new issue