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net: sh_eth: Add R8A77980 V3H gether support
The R8A77980 V3H gether needs a few minor adjustments to the sh_eth driver, add them to support ethernet on R8A77980. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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commit
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2 changed files with 16 additions and 5 deletions
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@ -374,10 +374,16 @@ static void sh_eth_write_hwaddr(struct sh_eth_info *port_info,
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static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
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static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
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{
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{
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struct sh_eth_info *port_info = ð->port_info[eth->port];
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struct sh_eth_info *port_info = ð->port_info[eth->port];
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unsigned long edmr;
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/* Configure e-dmac registers */
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/* Configure e-dmac registers */
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sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) |
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edmr = sh_eth_read(port_info, EDMR);
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(EMDR_DESC | EDMR_EL), EDMR);
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edmr &= ~EMDR_DESC_R;
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edmr |= EMDR_DESC | EDMR_EL;
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#if defined(CONFIG_R8A77980)
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edmr |= EDMR_NBST;
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#endif
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sh_eth_write(port_info, edmr, EDMR);
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sh_eth_write(port_info, 0, EESIPR);
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sh_eth_write(port_info, 0, EESIPR);
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sh_eth_write(port_info, 0, TRSCER);
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sh_eth_write(port_info, 0, TRSCER);
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@ -407,7 +413,7 @@ static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
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#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
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#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
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sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
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sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
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#elif defined(CONFIG_RCAR_GEN2)
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#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
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sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
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sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
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#endif
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#endif
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}
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}
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@ -426,7 +432,7 @@ static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
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sh_eth_write(port_info, GECMR_100B, GECMR);
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sh_eth_write(port_info, GECMR_100B, GECMR);
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#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
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#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
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sh_eth_write(port_info, 1, RTRATE);
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sh_eth_write(port_info, 1, RTRATE);
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#elif defined(CONFIG_RCAR_GEN2)
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#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
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val = ECMR_RTM;
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val = ECMR_RTM;
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#endif
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#endif
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} else if (phy->speed == 10) {
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} else if (phy->speed == 10) {
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@ -931,6 +937,7 @@ static const struct udevice_id sh_ether_ids[] = {
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{ .compatible = "renesas,ether-r8a7791" },
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{ .compatible = "renesas,ether-r8a7791" },
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{ .compatible = "renesas,ether-r8a7793" },
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{ .compatible = "renesas,ether-r8a7793" },
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{ .compatible = "renesas,ether-r8a7794" },
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{ .compatible = "renesas,ether-r8a7794" },
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{ .compatible = "renesas,gether-r8a77980" },
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{ }
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{ }
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};
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};
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@ -358,6 +358,9 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
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#elif defined(CONFIG_R7S72100)
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#elif defined(CONFIG_R7S72100)
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#define SH_ETH_TYPE_RZ
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#define SH_ETH_TYPE_RZ
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#define BASE_IO_ADDR 0xE8203000
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#define BASE_IO_ADDR 0xE8203000
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#elif defined(CONFIG_R8A77980)
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#define SH_ETH_TYPE_GETHER
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#define BASE_IO_ADDR 0xE7400000
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#endif
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#endif
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/*
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/*
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@ -374,6 +377,7 @@ enum EDSR_BIT {
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/* EDMR */
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/* EDMR */
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enum DMAC_M_BIT {
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enum DMAC_M_BIT {
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EDMR_NBST = 0x80, /* DMA transfer burst mode */
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EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
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EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
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#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
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#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
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EDMR_SRST = 0x03, /* Receive/Send reset */
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EDMR_SRST = 0x03, /* Receive/Send reset */
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@ -563,7 +567,7 @@ enum FELIC_MODE_BIT {
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ECMR_PRM = 0x00000001,
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ECMR_PRM = 0x00000001,
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#ifdef CONFIG_CPU_SH7724
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#ifdef CONFIG_CPU_SH7724
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ECMR_RTM = 0x00000010,
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ECMR_RTM = 0x00000010,
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#elif defined(CONFIG_RCAR_GEN2)
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#elif defined(CONFIG_RCAR_GEN2) || defined (CONFIG_R8A77980)
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ECMR_RTM = 0x00000004,
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ECMR_RTM = 0x00000004,
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#endif
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#endif
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