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mx31: provide readable WEIM CS accessor
setup_weimcs() and some macros are added to support the setup for i.MX31 WEIM chip selects. As a compromise between verbosity and readability an ASCII-art'ish bit comment is used instead of bitfields. All i.MX31 boards have been patched to use this approach using a helper program to verify the changes. Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> Acked-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
parent
43883dc3e5
commit
47c5455a48
8 changed files with 186 additions and 76 deletions
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@ -25,6 +25,7 @@
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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static u32 mx31_decode_pll(u32 reg, u32 infreq)
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{
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@ -140,6 +141,16 @@ void mx31_set_pad(enum iomux_pins pin, u32 config)
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}
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void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs)
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{
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struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE;
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struct mx31_weim_cscr *cscr = &weim->cscr[cs];
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writel(weimcs->upper, &cscr->upper);
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writel(weimcs->lower, &cscr->lower);
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writel(weimcs->additional, &cscr->additional);
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}
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struct mx3_cpu_type mx31_cpu_type[] = {
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{ .srev = 0x00, .v = 0x10 },
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{ .srev = 0x10, .v = 0x11 },
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@ -472,6 +472,18 @@ enum iomux_pins {
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#define CCM_RCSR_NF16B (1 << 31)
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#define CCM_RCSR_NFMS (1 << 30)
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/* WEIM CS control registers */
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struct mx31_weim_cscr {
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u32 upper;
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u32 lower;
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u32 additional;
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u32 reserved;
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};
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struct mx31_weim {
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struct mx31_weim_cscr cscr[6];
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};
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#endif
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#define __REG(x) (*((volatile u32 *)(x)))
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@ -550,10 +562,27 @@ enum iomux_pins {
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#define ESDCTL_BL(x) ((x) << 7)
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#define ESDCTL_PRCT(x) ((x) << 0)
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/* 13 fields of the upper CS control register */
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#define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
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cnc, wsc, ew, wws, edc) \
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((sp) << 31 | (wp) << 30 | (bcd) << 28 | (psz) << 22 | (pme) << 21 |\
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(sync) << 20 | (dol) << 16 | (cnc) << 14 | (wsc) << 8 | (ew) << 7 |\
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(wws) << 4 | (edc) << 0)
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/* 12 fields of the lower CS control register */
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#define CSCR_L(oea, oen, ebwa, ebwn, \
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csa, ebc, dsz, csn, psr, cre, wrap, csen) \
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((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\
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(csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\
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(psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
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/* 14 fields of the additional CS control register */
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#define CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \
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wwu, age, cnc2, fce) \
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((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\
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(mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\
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(dww) << 6 | (dct) << 4 | (wwu) << 3 |\
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(age) << 2 | (cnc2) << 1 | (fce) << 0)
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#define WEIM_BASE 0xb8002000
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#define CSCR_U(x) (WEIM_BASE + (x) * 0x10)
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#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
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#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)
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#define IOMUXC_BASE 0x43FAC000
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#define IOMUXC_GPR (IOMUXC_BASE + 0x8)
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35
arch/arm/include/asm/arch-mx31/sys_proto.h
Normal file
35
arch/arm/include/asm/arch-mx31/sys_proto.h
Normal file
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@ -0,0 +1,35 @@
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/*
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* (C) Copyright 2011
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* Helmut Raiger, HALE electronic GmbH, helmut.raiger@hale.at
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _SYS_PROTO_H_
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#define _SYS_PROTO_H_
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struct mxc_weimcs {
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u32 upper;
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u32 lower;
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u32 additional;
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};
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void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs);
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#endif
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@ -25,6 +25,7 @@
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#include <netdev.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <nand.h>
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#include <fsl_pmic.h>
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@ -61,11 +62,17 @@ static void qong_fpga_reset(void)
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int board_early_init_f (void)
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{
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#ifdef CONFIG_QONG_FPGA
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/* CS1: FPGA/Network Controller/GPIO */
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/* 16-bit, no DTACK */
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__REG(CSCR_U(1)) = 0x00000A01;
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__REG(CSCR_L(1)) = 0x20040501;
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__REG(CSCR_A(1)) = 0x04020C00;
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/* CS1: FPGA/Network Controller/GPIO, 16-bit, no DTACK */
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static const struct mxc_weimcs cs1 = {
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 1),
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
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CSCR_L(2, 0, 0, 4, 0, 0, 5, 0, 0, 0, 0, 1),
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
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CSCR_A(0, 4, 0, 2, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0)
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};
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mxc_setup_weimcs(1, &cs1);
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/* setup pins for FPGA */
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mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
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@ -146,50 +153,16 @@ int board_init (void)
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/* Chip selects */
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/* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
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/* Assumptions: HCLK = 133 MHz, tACC = 130ns */
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__REG(CSCR_U(0)) = ((0 << 31) | /* SP */
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(0 << 30) | /* WP */
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(0 << 28) | /* BCD */
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(0 << 24) | /* BCS */
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(0 << 22) | /* PSZ */
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(0 << 21) | /* PME */
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(0 << 20) | /* SYNC */
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(0 << 16) | /* DOL */
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(3 << 14) | /* CNC */
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(21 << 8) | /* WSC */
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(0 << 7) | /* EW */
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(0 << 4) | /* WWS */
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(6 << 0) /* EDC */
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);
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static const struct mxc_weimcs cs0 = {
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 21, 0, 0, 6),
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
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CSCR_L(0, 1, 3, 3, 1, 1, 5, 1, 0, 0, 0, 1),
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
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CSCR_A(0, 1, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
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};
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__REG(CSCR_L(0)) = ((2 << 28) | /* OEA */
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(1 << 24) | /* OEN */
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(3 << 20) | /* EBWA */
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(3 << 16) | /* EBWN */
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(1 << 12) | /* CSA */
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(1 << 11) | /* EBC */
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(5 << 8) | /* DSZ */
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(1 << 4) | /* CSN */
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(0 << 3) | /* PSR */
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(0 << 2) | /* CRE */
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(0 << 1) | /* WRAP */
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(1 << 0) /* CSEN */
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);
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__REG(CSCR_A(0)) = ((2 << 28) | /* EBRA */
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(1 << 24) | /* EBRN */
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(2 << 20) | /* RWA */
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(2 << 16) | /* RWN */
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(0 << 15) | /* MUM */
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(0 << 13) | /* LAH */
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(2 << 10) | /* LBN */
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(0 << 8) | /* LBA */
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(0 << 6) | /* DWW */
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(0 << 4) | /* DCT */
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(0 << 3) | /* WWU */
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(0 << 2) | /* AGE */
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(0 << 1) | /* CNC2 */
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(0 << 0) /* FCE */
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);
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mxc_setup_weimcs(0, &cs0);
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/* board id for linux */
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gd->bd->bi_arch_number = MACH_TYPE_QONG;
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@ -247,11 +220,18 @@ int board_eth_init(bd_t *bis)
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#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT)
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static void board_nand_setup(void)
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{
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/* CS3: NAND 8-bit */
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__REG(CSCR_U(3)) = 0x00004f00;
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__REG(CSCR_L(3)) = 0x20013b31;
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__REG(CSCR_A(3)) = 0x00020800;
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static const struct mxc_weimcs cs3 = {
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 1, 15, 0, 0, 0),
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
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CSCR_L(2, 0, 0, 1, 3, 1, 3, 3, 0, 0, 0, 1),
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
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CSCR_A(0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
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};
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mxc_setup_weimcs(3, &cs3);
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__REG(IOMUXC_GPR) |= 1 << 13;
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
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@ -25,6 +25,7 @@
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -48,9 +49,16 @@ int board_early_init_f(void)
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* the only non-zero field "Wait State Control" is set to half the
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* default value.
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*/
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__REG(CSCR_U(0)) = 0x00000f00;
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__REG(CSCR_L(0)) = 0x10000D03;
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__REG(CSCR_A(0)) = 0x00720900;
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static const struct mxc_weimcs cs0 = {
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0),
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
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CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1),
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
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CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0)
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};
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mxc_setup_weimcs(0, &cs0);
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/* setup pins for UART1 */
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mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
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@ -28,6 +28,7 @@
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#include <netdev.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <watchdog.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -50,9 +51,16 @@ int dram_init(void)
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int board_early_init_f(void)
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{
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/* CS5: CPLD incl. network controller */
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__REG(CSCR_U(5)) = 0x0000d843;
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__REG(CSCR_L(5)) = 0x22252521;
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__REG(CSCR_A(5)) = 0x22220a00;
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static const struct mxc_weimcs cs5 = {
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3),
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
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CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1),
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
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CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0)
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};
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mxc_setup_weimcs(5, &cs5);
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/* Setup UART1 and SPI2 pins */
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mx31_uart1_hw_init();
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@ -27,6 +27,7 @@
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#include <netdev.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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__REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
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__REG(CSCR_L(0)) = 0x10000d03;
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__REG(CSCR_A(0)) = 0x00720900;
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/* CS0: Nor Flash */
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static const struct mxc_weimcs cs0 = {
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3),
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
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CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1),
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
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CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0)
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};
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__REG(CSCR_U(1)) = 0x0000df06; /* CS1: Network Controller */
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__REG(CSCR_L(1)) = 0x444a4541;
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__REG(CSCR_A(1)) = 0x44443302;
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/* CS1: Network Controller */
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static const struct mxc_weimcs cs1 = {
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 31, 0, 0, 6),
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
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CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
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CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
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};
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__REG(CSCR_U(4)) = 0x0000d843; /* CS4: SRAM */
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__REG(CSCR_L(4)) = 0x22252521;
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__REG(CSCR_A(4)) = 0x22220a00;
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/* CS4: SRAM */
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static const struct mxc_weimcs cs4 = {
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3),
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
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CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1),
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
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CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0)
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};
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mxc_setup_weimcs(0, &cs0);
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mxc_setup_weimcs(1, &cs1);
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mxc_setup_weimcs(4, &cs4);
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/* setup pins for UART1 */
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mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
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@ -26,6 +26,7 @@
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#include <netdev.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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__REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
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__REG(CSCR_L(0)) = 0xa0330d01;
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__REG(CSCR_A(0)) = 0x00220800;
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/* CS0: Nor Flash */
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static const struct mxc_weimcs cs0 = {
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3),
|
||||
/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
|
||||
CSCR_L(10, 0, 3, 3, 0, 1, 5, 0, 0, 0, 0, 1),
|
||||
/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
|
||||
CSCR_A(0, 0, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
|
||||
};
|
||||
|
||||
__REG(CSCR_U(4)) = 0x0000dcf6; /* CS4: Network Controller */
|
||||
__REG(CSCR_L(4)) = 0x444a4541;
|
||||
__REG(CSCR_A(4)) = 0x44443302;
|
||||
/* CS4: Network Controller */
|
||||
static const struct mxc_weimcs cs4 = {
|
||||
/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
|
||||
CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6),
|
||||
/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
|
||||
CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
|
||||
/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
|
||||
CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
|
||||
};
|
||||
|
||||
mxc_setup_weimcs(0, &cs0);
|
||||
mxc_setup_weimcs(4, &cs4);
|
||||
|
||||
/* setup pins for UART1 */
|
||||
mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
|
||||
|
|
Loading…
Add table
Reference in a new issue