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xpedite5370: Enable multi-core support
Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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parent
5ccd29c367
commit
48618126f7
2 changed files with 17 additions and 4 deletions
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@ -61,32 +61,37 @@ struct fsl_e_tlb_entry tlb_table[] = {
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 2, BOOKE_PAGESZ_1M, 1),
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/* **M** - Boot page for secondary processors */
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SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
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0, 3, BOOKE_PAGESZ_4K, 1),
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#ifdef CONFIG_PCIE1
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/* *I*G* - PCIe */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 3, BOOKE_PAGESZ_1G, 1),
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0, 4, BOOKE_PAGESZ_1G, 1),
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#endif
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#ifdef CONFIG_PCIE2
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/* *I*G* - PCIe */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 4, BOOKE_PAGESZ_256M, 1),
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0, 5, BOOKE_PAGESZ_256M, 1),
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#endif
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#ifdef CONFIG_PCIE3
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/* *I*G* - PCIe */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 5, BOOKE_PAGESZ_256M, 1),
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0, 6, BOOKE_PAGESZ_256M, 1),
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#endif
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#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
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/* *I*G* - PCIe */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 6, BOOKE_PAGESZ_64M, 1),
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0, 7, BOOKE_PAGESZ_64M, 1),
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#endif
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};
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@ -48,6 +48,13 @@
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#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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/*
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* Multicore config
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*/
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#define CONFIG_MP
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#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
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#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
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/*
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* DDR config
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*/
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@ -109,6 +116,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
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* 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
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* 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
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* 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
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* 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
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* 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
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* 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
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* 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
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