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imx: imx8mp_evk: enable eth support
Add board code to configure the network interface Add net defconfig Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
parent
184aa65041
commit
48b90f86c5
5 changed files with 94 additions and 2 deletions
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@ -139,3 +139,7 @@
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&wdog1 {
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u-boot,dm-spl;
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};
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&fec {
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phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
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};
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@ -62,6 +62,8 @@
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#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
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#define DDR_CSD1_BASE_ADDR 0x40000000
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#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000
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#if !defined(__ASSEMBLY__)
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#include <asm/types.h>
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#include <linux/bitops.h>
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@ -7,9 +7,13 @@
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#include <env.h>
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#include <errno.h>
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#include <init.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <linux/delay.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm-generic/gpio.h>
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#include <asm/arch/imx8mp_pins.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/gpio.h>
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@ -40,9 +44,68 @@ int board_early_init_f(void)
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return 0;
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}
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static void setup_fec(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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/* Enable RGMII TX clk output */
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setbits_le32(&gpr->gpr[1], BIT(22));
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}
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#define EQOS_RST_PAD IMX_GPIO_NR(4, 22)
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static iomux_v3_cfg_t const eqos_rst_pads[] = {
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MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_iomux_eqos(void)
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{
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imx_iomux_v3_setup_multiple_pads(eqos_rst_pads,
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ARRAY_SIZE(eqos_rst_pads));
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gpio_request(EQOS_RST_PAD, "eqos_rst");
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gpio_direction_output(EQOS_RST_PAD, 0);
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mdelay(15);
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gpio_direction_output(EQOS_RST_PAD, 1);
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mdelay(100);
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}
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static int setup_eqos(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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setup_iomux_eqos();
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/* set INTF as RGMII, enable RGMII TXC clock */
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clrsetbits_le32(&gpr->gpr[1],
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IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
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setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
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return set_clk_eqos(ENET_125MHZ);
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}
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#if CONFIG_IS_ENABLED(NET)
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int board_phy_config(struct phy_device *phydev)
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{
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#endif
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int board_init(void)
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{
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return 0;
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int ret = 0;
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if (CONFIG_IS_ENABLED(FEC_MXC)) {
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setup_fec();
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if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
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ret = setup_eqos();
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}
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return ret;
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}
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int board_late_init(void)
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@ -45,6 +45,9 @@ CONFIG_CMD_FUSE=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_REGULATOR=y
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CONFIG_CMD_EXT2=y
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@ -74,8 +77,12 @@ CONFIG_MMC_UHS_SUPPORT=y
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CONFIG_MMC_HS400_ES_SUPPORT=y
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CONFIG_MMC_HS400_SUPPORT=y
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CONFIG_FSL_ESDHC_IMX=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_REALTEK=y
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CONFIG_DM_ETH=y
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CONFIG_PHY_GIGE=y
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CONFIG_DWC_ETH_QOS=y
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_PINCTRL=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_PINCTRL_IMX8M=y
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@ -44,6 +44,22 @@
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#endif
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#if defined(CONFIG_CMD_NET)
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#define CONFIG_ETHPRIME "eth1" /* Set eqos to primary since we use its MDIO */
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_FEC_MXC_PHYADDR 1
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#define FEC_QUIRK_ENET_MAC
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#define DWC_NET_PHYADDR 1
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#ifdef CONFIG_DWC_ETH_QOS
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#define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */
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#endif
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#define PHY_ANEG_TIMEOUT 20000
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#endif
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"script=boot.scr\0" \
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